Generated from crates: core, alloc, std.
| Index | Module Path | API Name | Kind | Safety Doc | Mark |
|---|---|---|---|---|---|
| 1 | alloc::alloc | alloc | function | See [`GlobalAlloc::alloc`]. | |
| 2 | alloc::alloc | alloc_zeroed | function | See [`GlobalAlloc::alloc_zeroed`]. | |
| 3 | alloc::alloc | dealloc | function | See [`GlobalAlloc::dealloc`]. | |
| 4 | alloc::alloc | realloc | function | See [`GlobalAlloc::realloc`]. | |
| 5 | alloc::boxed::Box | assume_init | function | As with [`MaybeUninit::assume_init`], it is up to the caller to guarantee that the value really is in an initialized state. Calling this when the content is not yet fully initialized causes immediate undefined behavior. [`MaybeUninit::assume_init`]: mem::MaybeUninit::assume_init As with [`MaybeUninit::assume_init`], it is up to the caller to guarantee that the values really are in an initialized state. Calling this when the content is not yet fully initialized causes immediate undefined behavior. [`MaybeUninit::assume_init`]: mem::MaybeUninit::assume_init | |
| 6 | alloc::boxed::Box | downcast_unchecked | function | The contained value must be of type `T`. Calling this method with the incorrect type is *undefined behavior*. [`downcast`]: Self::downcast | |
| 7 | alloc::boxed::Box | from_non_null | function | This function is unsafe because improper use may lead to memory problems. For example, a double-free may occur if the function is called twice on the same `NonNull` pointer. The non-null pointer must point to a block of memory allocated by the global allocator. The safety conditions are described in the [memory layout] section. Note that the [considerations for unsafe code] apply to all `Box<T>` values. | |
| 8 | alloc::boxed::Box | from_non_null_in | function | This function is unsafe because improper use may lead to memory problems. For example, a double-free may occur if the function is called twice on the same raw pointer. The non-null pointer must point to a block of memory allocated by `alloc`. The safety conditions are described in the [memory layout] section. Note that the [considerations for unsafe code] apply to all `Box<T, A>` values. | |
| 9 | alloc::boxed::Box | from_raw | function | This function is unsafe because improper use may lead to memory problems. For example, a double-free may occur if the function is called twice on the same raw pointer. The raw pointer must point to a block of memory allocated by the global allocator. The safety conditions are described in the [memory layout] section. Note that the [considerations for unsafe code] apply to all `Box<T>` values. | |
| 10 | alloc::boxed::Box | from_raw_in | function | This function is unsafe because improper use may lead to memory problems. For example, a double-free may occur if the function is called twice on the same raw pointer. The raw pointer must point to a block of memory allocated by `alloc`. The safety conditions are described in the [memory layout] section. Note that the [considerations for unsafe code] apply to all `Box<T, A>` values. | |
| 11 | alloc::collections::binary_heap::BinaryHeap | as_mut_slice | function | The caller must ensure that the slice remains a max-heap, i.e. for all indices `0 < i < slice.len()`, `slice[(i - 1) / 2] >= slice[i]`, before the borrow ends and the binary heap is used. | |
| 12 | alloc::collections::binary_heap::BinaryHeap | from_raw_vec | function | The supplied `vec` must be a max-heap, i.e. for all indices `0 < i < vec.len()`, `vec[(i - 1) / 2] >= vec[i]`. | |
| 13 | alloc::collections::btree::map::CursorMut | insert_after_unchecked | function | You must ensure that the `BTreeMap` invariants are maintained. Specifically: * The key of the newly inserted element must be unique in the tree. * All keys in the tree must remain in sorted order. | |
| 14 | alloc::collections::btree::map::CursorMut | insert_before_unchecked | function | You must ensure that the `BTreeMap` invariants are maintained. Specifically: * The key of the newly inserted element must be unique in the tree. * All keys in the tree must remain in sorted order. | |
| 15 | alloc::collections::btree::map::CursorMut | with_mutable_key | function | Since this cursor allows mutating keys, you must ensure that the `BTreeMap` invariants are maintained. Specifically: * The key of the newly inserted element must be unique in the tree. * All keys in the tree must remain in sorted order. | |
| 16 | alloc::collections::btree::map::CursorMutKey | insert_after_unchecked | function | You must ensure that the `BTreeMap` invariants are maintained. Specifically: * The key of the newly inserted element must be unique in the tree. * All keys in the tree must remain in sorted order. | |
| 17 | alloc::collections::btree::map::CursorMutKey | insert_before_unchecked | function | You must ensure that the `BTreeMap` invariants are maintained. Specifically: * The key of the newly inserted element must be unique in the tree. * All keys in the tree must remain in sorted order. | |
| 18 | alloc::collections::btree::set::CursorMut | insert_after_unchecked | function | You must ensure that the `BTreeSet` invariants are maintained. Specifically: * The newly inserted element must be unique in the tree. * All elements in the tree must remain in sorted order. | |
| 19 | alloc::collections::btree::set::CursorMut | insert_before_unchecked | function | You must ensure that the `BTreeSet` invariants are maintained. Specifically: * The newly inserted element must be unique in the tree. * All elements in the tree must remain in sorted order. | |
| 20 | alloc::collections::btree::set::CursorMut | with_mutable_key | function | Since this cursor allows mutating elements, you must ensure that the `BTreeSet` invariants are maintained. Specifically: * The newly inserted element must be unique in the tree. * All elements in the tree must remain in sorted order. | |
| 21 | alloc::collections::btree::set::CursorMutKey | insert_after_unchecked | function | You must ensure that the `BTreeSet` invariants are maintained. Specifically: * The key of the newly inserted element must be unique in the tree. * All elements in the tree must remain in sorted order. | |
| 22 | alloc::collections::btree::set::CursorMutKey | insert_before_unchecked | function | You must ensure that the `BTreeSet` invariants are maintained. Specifically: * The newly inserted element must be unique in the tree. * All elements in the tree must remain in sorted order. | |
| 23 | alloc::ffi::c_str::CString | from_raw | function | This should only ever be called with a pointer that was earlier obtained by calling [`CString::into_raw`], and the memory it points to must not be accessed through any other pointer during the lifetime of reconstructed `CString`. Other usage (e.g., trying to take ownership of a string that was allocated by foreign code) is likely to lead to undefined behavior or allocator corruption. This function does not validate ownership of the raw pointer's memory. A double-free may occur if the function is called twice on the same raw pointer. Additionally, the caller must ensure the pointer is not dangling. It should be noted that the length isn't just "recomputed," but that the recomputed length must match the original length from the [`CString::into_raw`] call. This means the [`CString::into_raw`]/`from_raw` methods should not be used when passing the string to C functions that can modify the string's length. > **Note:** If you need to borrow a string that was allocated by > foreign code, use [`CStr`]. If you need to take ownership of > a string that was allocated by foreign code, you will need to > make your own provisions for freeing it appropriately, likely > with the foreign code's API to do that. | |
| 24 | alloc::ffi::c_str::CString | from_vec_unchecked | function | The caller must ensure `v` contains no nul bytes in its contents. | |
| 25 | alloc::ffi::c_str::CString | from_vec_with_nul_unchecked | function | The given [`Vec`] **must** have one nul byte as its last element. This means it cannot be empty nor have any other nul byte anywhere else. | |
| 26 | alloc::rc::Rc | assume_init | function | As with [`MaybeUninit::assume_init`], it is up to the caller to guarantee that the inner value really is in an initialized state. Calling this when the content is not yet fully initialized causes immediate undefined behavior. [`MaybeUninit::assume_init`]: mem::MaybeUninit::assume_init | |
| 27 | alloc::rc::Rc | decrement_strong_count | function | The pointer must have been obtained through `Rc::into_raw` and must satisfy the same layout requirements specified in [`Rc::from_raw_in`][from_raw_in]. The associated `Rc` instance must be valid (i.e. the strong count must be at least 1) when invoking this method, and `ptr` must point to a block of memory allocated by the global allocator. This method can be used to release the final `Rc` and backing storage, but **should not** be called after the final `Rc` has been released. [from_raw_in]: Rc::from_raw_in | |
| 28 | alloc::rc::Rc | decrement_strong_count_in | function | The pointer must have been obtained through `Rc::into_raw`and must satisfy the same layout requirements specified in [`Rc::from_raw_in`][from_raw_in]. The associated `Rc` instance must be valid (i.e. the strong count must be at least 1) when invoking this method, and `ptr` must point to a block of memory allocated by `alloc`. This method can be used to release the final `Rc` and backing storage, but **should not** be called after the final `Rc` has been released. [from_raw_in]: Rc::from_raw_in | |
| 29 | alloc::rc::Rc | downcast_unchecked | function | The contained value must be of type `T`. Calling this method with the incorrect type is *undefined behavior*. [`downcast`]: Self::downcast | |
| 30 | alloc::rc::Rc | from_raw | function | * Creating a `Rc<T>` from a pointer other than one returned from [`Rc<U>::into_raw`][into_raw] or [`Rc<U>::into_raw_with_allocator`][into_raw_with_allocator] is undefined behavior. * If `U` is sized, it must have the same size and alignment as `T`. This is trivially true if `U` is `T`. * If `U` is unsized, its data pointer must have the same size and alignment as `T`. This is trivially true if `Rc<U>` was constructed through `Rc<T>` and then converted to `Rc<U>` through an [unsized coercion]. * Note that if `U` or `U`'s data pointer is not `T` but has the same size and alignment, this is basically like transmuting references of different types. See [`mem::transmute`][transmute] for more information on what restrictions apply in this case. * The raw pointer must point to a block of memory allocated by the global allocator * The user of `from_raw` has to make sure a specific value of `T` is only dropped once. This function is unsafe because improper use may lead to memory unsafety, even if the returned `Rc<T>` is never accessed. [into_raw]: Rc::into_raw [into_raw_with_allocator]: Rc::into_raw_with_allocator [transmute]: core::mem::transmute [unsized coercion]: https://doc.rust-lang.org/reference/type-coercions.html#unsized-coercions | |
| 31 | alloc::rc::Rc | from_raw_in | function | * Creating a `Rc<T, A>` from a pointer other than one returned from [`Rc<U, A>::into_raw`][into_raw] or [`Rc<U, A>::into_raw_with_allocator`][into_raw_with_allocator] is undefined behavior. * If `U` is sized, it must have the same size and alignment as `T`. This is trivially true if `U` is `T`. * If `U` is unsized, its data pointer must have the same size and alignment as `T`. This is trivially true if `Rc<U, A>` was constructed through `Rc<T, A>` and then converted to `Rc<U, A>` through an [unsized coercion]. * Note that if `U` or `U`'s data pointer is not `T` but has the same size and alignment, this is basically like transmuting references of different types. See [`mem::transmute`][transmute] for more information on what restrictions apply in this case. * The raw pointer must point to a block of memory allocated by `alloc` * The user of `from_raw` has to make sure a specific value of `T` is only dropped once. This function is unsafe because improper use may lead to memory unsafety, even if the returned `Rc<T, A>` is never accessed. [into_raw]: Rc::into_raw [into_raw_with_allocator]: Rc::into_raw_with_allocator [transmute]: core::mem::transmute [unsized coercion]: https://doc.rust-lang.org/reference/type-coercions.html#unsized-coercions | |
| 32 | alloc::rc::Rc | get_mut_unchecked | function | If any other `Rc` or [`Weak`] pointers to the same allocation exist, then they must not be dereferenced or have active borrows for the duration of the returned borrow, and their inner type must be exactly the same as the inner type of this Rc (including lifetimes). This is trivially the case if no such pointers exist, for example immediately after `Rc::new`. | |
| 33 | alloc::rc::Rc | increment_strong_count | function | The pointer must have been obtained through [`Rc::into_raw`] and must satisfy the same layout requirements specified in [`Rc::from_raw_in`]. The associated `Rc` instance must be valid (i.e. the strong count must be at least 1) for the duration of this method, and `ptr` must point to a block of memory allocated by the global allocator. | |
| 34 | alloc::rc::Rc | increment_strong_count_in | function | The pointer must have been obtained through `Rc::into_raw` and must satisfy the same layout requirements specified in [`Rc::from_raw_in`][from_raw_in]. The associated `Rc` instance must be valid (i.e. the strong count must be at least 1) for the duration of this method, and `ptr` must point to a block of memory allocated by `alloc`. [from_raw_in]: Rc::from_raw_in | |
| 35 | alloc::rc::Weak | from_raw | function | The pointer must have originated from the [`into_raw`] and must still own its potential weak reference, and `ptr` must point to a block of memory allocated by the global allocator. It is allowed for the strong count to be 0 at the time of calling this. Nevertheless, this takes ownership of one weak reference currently represented as a raw pointer (the weak count is not modified by this operation) and therefore it must be paired with a previous call to [`into_raw`]. | |
| 36 | alloc::rc::Weak | from_raw_in | function | The pointer must have originated from the [`into_raw`] and must still own its potential weak reference, and `ptr` must point to a block of memory allocated by `alloc`. It is allowed for the strong count to be 0 at the time of calling this. Nevertheless, this takes ownership of one weak reference currently represented as a raw pointer (the weak count is not modified by this operation) and therefore it must be paired with a previous call to [`into_raw`]. | |
| 37 | alloc::str | from_boxed_utf8_unchecked | function | * The provided bytes must contain a valid UTF-8 sequence. | |
| 38 | alloc::string::String | as_mut_vec | function | This function is unsafe because the returned `&mut Vec` allows writing bytes which are not valid UTF-8. If this constraint is violated, using the original `String` after dropping the `&mut Vec` may violate memory safety, as the rest of the standard library assumes that `String`s are valid UTF-8. | |
| 39 | alloc::string::String | from_raw_parts | function | This is highly unsafe, due to the number of invariants that aren't checked: * all safety requirements for [`Vec::<u8>::from_raw_parts`]. * all safety requirements for [`String::from_utf8_unchecked`]. Violating these may cause problems like corrupting the allocator's internal data structures. For example, it is normally **not** safe to build a `String` from a pointer to a C `char` array containing UTF-8 _unless_ you are certain that array was originally allocated by the Rust standard library's allocator. The ownership of `buf` is effectively transferred to the `String` which may then deallocate, reallocate or change the contents of memory pointed to by the pointer at will. Ensure that nothing else uses the pointer after calling this function. | |
| 40 | alloc::string::String | from_utf8_unchecked | function | This function is unsafe because it does not check that the bytes passed to it are valid UTF-8. If this constraint is violated, it may cause memory unsafety issues with future users of the `String`, as the rest of the standard library assumes that `String`s are valid UTF-8. | |
| 41 | alloc::sync::Arc | assume_init | function | As with [`MaybeUninit::assume_init`], it is up to the caller to guarantee that the inner value really is in an initialized state. Calling this when the content is not yet fully initialized causes immediate undefined behavior. [`MaybeUninit::assume_init`]: mem::MaybeUninit::assume_init | |
| 42 | alloc::sync::Arc | decrement_strong_count | function | The pointer must have been obtained through `Arc::into_raw` and must satisfy the same layout requirements specified in [`Arc::from_raw_in`][from_raw_in]. The associated `Arc` instance must be valid (i.e. the strong count must be at least 1) when invoking this method, and `ptr` must point to a block of memory allocated by the global allocator. This method can be used to release the final `Arc` and backing storage, but **should not** be called after the final `Arc` has been released. [from_raw_in]: Arc::from_raw_in | |
| 43 | alloc::sync::Arc | decrement_strong_count_in | function | The pointer must have been obtained through `Arc::into_raw` and must satisfy the same layout requirements specified in [`Arc::from_raw_in`][from_raw_in]. The associated `Arc` instance must be valid (i.e. the strong count must be at least 1) when invoking this method, and `ptr` must point to a block of memory allocated by `alloc`. This method can be used to release the final `Arc` and backing storage, but **should not** be called after the final `Arc` has been released. [from_raw_in]: Arc::from_raw_in | |
| 44 | alloc::sync::Arc | downcast_unchecked | function | The contained value must be of type `T`. Calling this method with the incorrect type is *undefined behavior*. [`downcast`]: Self::downcast | |
| 45 | alloc::sync::Arc | from_raw | function | * Creating a `Arc<T>` from a pointer other than one returned from [`Arc<U>::into_raw`][into_raw] or [`Arc<U>::into_raw_with_allocator`][into_raw_with_allocator] is undefined behavior. * If `U` is sized, it must have the same size and alignment as `T`. This is trivially true if `U` is `T`. * If `U` is unsized, its data pointer must have the same size and alignment as `T`. This is trivially true if `Arc<U>` was constructed through `Arc<T>` and then converted to `Arc<U>` through an [unsized coercion]. * Note that if `U` or `U`'s data pointer is not `T` but has the same size and alignment, this is basically like transmuting references of different types. See [`mem::transmute`][transmute] for more information on what restrictions apply in this case. * The raw pointer must point to a block of memory allocated by the global allocator. * The user of `from_raw` has to make sure a specific value of `T` is only dropped once. This function is unsafe because improper use may lead to memory unsafety, even if the returned `Arc<T>` is never accessed. [into_raw]: Arc::into_raw [into_raw_with_allocator]: Arc::into_raw_with_allocator [transmute]: core::mem::transmute [unsized coercion]: https://doc.rust-lang.org/reference/type-coercions.html#unsized-coercions | |
| 46 | alloc::sync::Arc | from_raw_in | function | * Creating a `Arc<T, A>` from a pointer other than one returned from [`Arc<U, A>::into_raw`][into_raw] or [`Arc<U, A>::into_raw_with_allocator`][into_raw_with_allocator] is undefined behavior. * If `U` is sized, it must have the same size and alignment as `T`. This is trivially true if `U` is `T`. * If `U` is unsized, its data pointer must have the same size and alignment as `T`. This is trivially true if `Arc<U, A>` was constructed through `Arc<T, A>` and then converted to `Arc<U, A>` through an [unsized coercion]. * Note that if `U` or `U`'s data pointer is not `T` but has the same size and alignment, this is basically like transmuting references of different types. See [`mem::transmute`][transmute] for more information on what restrictions apply in this case. * The raw pointer must point to a block of memory allocated by `alloc` * The user of `from_raw` has to make sure a specific value of `T` is only dropped once. This function is unsafe because improper use may lead to memory unsafety, even if the returned `Arc<T>` is never accessed. [into_raw]: Arc::into_raw [into_raw_with_allocator]: Arc::into_raw_with_allocator [transmute]: core::mem::transmute [unsized coercion]: https://doc.rust-lang.org/reference/type-coercions.html#unsized-coercions | |
| 47 | alloc::sync::Arc | get_mut_unchecked | function | If any other `Arc` or [`Weak`] pointers to the same allocation exist, then they must not be dereferenced or have active borrows for the duration of the returned borrow, and their inner type must be exactly the same as the inner type of this Arc (including lifetimes). This is trivially the case if no such pointers exist, for example immediately after `Arc::new`. | |
| 48 | alloc::sync::Arc | increment_strong_count | function | The pointer must have been obtained through `Arc::into_raw` and must satisfy the same layout requirements specified in [`Arc::from_raw_in`][from_raw_in]. The associated `Arc` instance must be valid (i.e. the strong count must be at least 1) for the duration of this method, and `ptr` must point to a block of memory allocated by the global allocator. [from_raw_in]: Arc::from_raw_in | |
| 49 | alloc::sync::Arc | increment_strong_count_in | function | The pointer must have been obtained through `Arc::into_raw` and must satisfy the same layout requirements specified in [`Arc::from_raw_in`][from_raw_in]. The associated `Arc` instance must be valid (i.e. the strong count must be at least 1) for the duration of this method, and `ptr` must point to a block of memory allocated by `alloc`. [from_raw_in]: Arc::from_raw_in | |
| 50 | alloc::sync::Weak | from_raw | function | The pointer must have originated from the [`into_raw`] and must still own its potential weak reference, and must point to a block of memory allocated by global allocator. It is allowed for the strong count to be 0 at the time of calling this. Nevertheless, this takes ownership of one weak reference currently represented as a raw pointer (the weak count is not modified by this operation) and therefore it must be paired with a previous call to [`into_raw`]. | |
| 51 | alloc::sync::Weak | from_raw_in | function | The pointer must have originated from the [`into_raw`] and must still own its potential weak reference, and must point to a block of memory allocated by `alloc`. It is allowed for the strong count to be 0 at the time of calling this. Nevertheless, this takes ownership of one weak reference currently represented as a raw pointer (the weak count is not modified by this operation) and therefore it must be paired with a previous call to [`into_raw`]. | |
| 52 | alloc::vec::Vec | from_parts | function | This is highly unsafe, due to the number of invariants that aren't checked: * `ptr` must have been allocated using the global allocator, such as via the [`alloc::alloc`] function. * `T` needs to have the same alignment as what `ptr` was allocated with. (`T` having a less strict alignment is not sufficient, the alignment really needs to be equal to satisfy the [`dealloc`] requirement that memory must be allocated and deallocated with the same layout.) * The size of `T` times the `capacity` (i.e. the allocated size in bytes) needs to be the same size as the pointer was allocated with. (Because similar to alignment, [`dealloc`] must be called with the same layout `size`.) * `length` needs to be less than or equal to `capacity`. * The first `length` values must be properly initialized values of type `T`. * `capacity` needs to be the capacity that the pointer was allocated with. * The allocated size in bytes must be no larger than `isize::MAX`. See the safety documentation of [`pointer::offset`]. These requirements are always upheld by any `ptr` that has been allocated via `Vec<T>`. Other allocation sources are allowed if the invariants are upheld. Violating these may cause problems like corrupting the allocator's internal data structures. For example it is normally **not** safe to build a `Vec<u8>` from a pointer to a C `char` array with length `size_t`, doing so is only safe if the array was initially allocated by a `Vec` or `String`. It's also not safe to build one from a `Vec<u16>` and its length, because the allocator cares about the alignment, and these two types have different alignments. The buffer was allocated with alignment 2 (for `u16`), but after turning it into a `Vec<u8>` it'll be deallocated with alignment 1. To avoid these issues, it is often preferable to do casting/transmuting using [`NonNull::slice_from_raw_parts`] instead. The ownership of `ptr` is effectively transferred to the `Vec<T>` which may then deallocate, reallocate or change the contents of memory pointed to by the pointer at will. Ensure that nothing else uses the pointer after calling this function. [`String`]: crate::string::String [`alloc::alloc`]: crate::alloc::alloc [`dealloc`]: crate::alloc::GlobalAlloc::dealloc | |
| 53 | alloc::vec::Vec | from_parts_in | function | This is highly unsafe, due to the number of invariants that aren't checked: * `ptr` must be [*currently allocated*] via the given allocator `alloc`. * `T` needs to have the same alignment as what `ptr` was allocated with. (`T` having a less strict alignment is not sufficient, the alignment really needs to be equal to satisfy the [`dealloc`] requirement that memory must be allocated and deallocated with the same layout.) * The size of `T` times the `capacity` (i.e. the allocated size in bytes) needs to be the same size as the pointer was allocated with. (Because similar to alignment, [`dealloc`] must be called with the same layout `size`.) * `length` needs to be less than or equal to `capacity`. * The first `length` values must be properly initialized values of type `T`. * `capacity` needs to [*fit*] the layout size that the pointer was allocated with. * The allocated size in bytes must be no larger than `isize::MAX`. See the safety documentation of [`pointer::offset`]. These requirements are always upheld by any `ptr` that has been allocated via `Vec<T, A>`. Other allocation sources are allowed if the invariants are upheld. Violating these may cause problems like corrupting the allocator's internal data structures. For example it is **not** safe to build a `Vec<u8>` from a pointer to a C `char` array with length `size_t`. It's also not safe to build one from a `Vec<u16>` and its length, because the allocator cares about the alignment, and these two types have different alignments. The buffer was allocated with alignment 2 (for `u16`), but after turning it into a `Vec<u8>` it'll be deallocated with alignment 1. The ownership of `ptr` is effectively transferred to the `Vec<T>` which may then deallocate, reallocate or change the contents of memory pointed to by the pointer at will. Ensure that nothing else uses the pointer after calling this function. [`String`]: crate::string::String [`dealloc`]: crate::alloc::GlobalAlloc::dealloc [*currently allocated*]: crate::alloc::Allocator#currently-allocated-memory [*fit*]: crate::alloc::Allocator#memory-fitting | |
| 54 | alloc::vec::Vec | from_raw_parts | function | This is highly unsafe, due to the number of invariants that aren't checked: * If `T` is not a zero-sized type and the capacity is nonzero, `ptr` must have been allocated using the global allocator, such as via the [`alloc::alloc`] function. If `T` is a zero-sized type or the capacity is zero, `ptr` need only be non-null and aligned. * `T` needs to have the same alignment as what `ptr` was allocated with, if the pointer is required to be allocated. (`T` having a less strict alignment is not sufficient, the alignment really needs to be equal to satisfy the [`dealloc`] requirement that memory must be allocated and deallocated with the same layout.) * The size of `T` times the `capacity` (i.e. the allocated size in bytes), if nonzero, needs to be the same size as the pointer was allocated with. (Because similar to alignment, [`dealloc`] must be called with the same layout `size`.) * `length` needs to be less than or equal to `capacity`. * The first `length` values must be properly initialized values of type `T`. * `capacity` needs to be the capacity that the pointer was allocated with, if the pointer is required to be allocated. * The allocated size in bytes must be no larger than `isize::MAX`. See the safety documentation of [`pointer::offset`]. These requirements are always upheld by any `ptr` that has been allocated via `Vec<T>`. Other allocation sources are allowed if the invariants are upheld. Violating these may cause problems like corrupting the allocator's internal data structures. For example it is normally **not** safe to build a `Vec<u8>` from a pointer to a C `char` array with length `size_t`, doing so is only safe if the array was initially allocated by a `Vec` or `String`. It's also not safe to build one from a `Vec<u16>` and its length, because the allocator cares about the alignment, and these two types have different alignments. The buffer was allocated with alignment 2 (for `u16`), but after turning it into a `Vec<u8>` it'll be deallocated with alignment 1. To avoid these issues, it is often preferable to do casting/transmuting using [`slice::from_raw_parts`] instead. The ownership of `ptr` is effectively transferred to the `Vec<T>` which may then deallocate, reallocate or change the contents of memory pointed to by the pointer at will. Ensure that nothing else uses the pointer after calling this function. [`String`]: crate::string::String [`alloc::alloc`]: crate::alloc::alloc [`dealloc`]: crate::alloc::GlobalAlloc::dealloc | |
| 55 | alloc::vec::Vec | from_raw_parts_in | function | This is highly unsafe, due to the number of invariants that aren't checked: * `ptr` must be [*currently allocated*] via the given allocator `alloc`. * `T` needs to have the same alignment as what `ptr` was allocated with. (`T` having a less strict alignment is not sufficient, the alignment really needs to be equal to satisfy the [`dealloc`] requirement that memory must be allocated and deallocated with the same layout.) * The size of `T` times the `capacity` (i.e. the allocated size in bytes) needs to be the same size as the pointer was allocated with. (Because similar to alignment, [`dealloc`] must be called with the same layout `size`.) * `length` needs to be less than or equal to `capacity`. * The first `length` values must be properly initialized values of type `T`. * `capacity` needs to [*fit*] the layout size that the pointer was allocated with. * The allocated size in bytes must be no larger than `isize::MAX`. See the safety documentation of [`pointer::offset`]. These requirements are always upheld by any `ptr` that has been allocated via `Vec<T, A>`. Other allocation sources are allowed if the invariants are upheld. Violating these may cause problems like corrupting the allocator's internal data structures. For example it is **not** safe to build a `Vec<u8>` from a pointer to a C `char` array with length `size_t`. It's also not safe to build one from a `Vec<u16>` and its length, because the allocator cares about the alignment, and these two types have different alignments. The buffer was allocated with alignment 2 (for `u16`), but after turning it into a `Vec<u8>` it'll be deallocated with alignment 1. The ownership of `ptr` is effectively transferred to the `Vec<T>` which may then deallocate, reallocate or change the contents of memory pointed to by the pointer at will. Ensure that nothing else uses the pointer after calling this function. [`String`]: crate::string::String [`dealloc`]: crate::alloc::GlobalAlloc::dealloc [*currently allocated*]: crate::alloc::Allocator#currently-allocated-memory [*fit*]: crate::alloc::Allocator#memory-fitting | |
| 56 | alloc::vec::Vec | set_len | function | - `new_len` must be less than or equal to [`capacity()`]. - The elements at `old_len..new_len` must be initialized. [`capacity()`]: Vec::capacity | |
| 57 | core::alloc | Allocator | trait | Memory blocks that are [*currently allocated*] by an allocator, must point to valid memory, and retain their validity until either: - the memory block is deallocated, or - the allocator is dropped. Copying, cloning, or moving the allocator must not invalidate memory blocks returned from it. A copied or cloned allocator must behave like the original allocator. A memory block which is [*currently allocated*] may be passed to any method of the allocator that accepts such an argument. Additionally, any memory block returned by the allocator must satisfy the allocation invariants described in `core::ptr`. In particular, if a block has base address `p` and size `n`, then `p as usize + n <= usize::MAX` must hold. This ensures that pointer arithmetic within the allocation (for example, `ptr.add(len)`) cannot overflow the address space. [*currently allocated*]: #currently-allocated-memory | |
| 58 | core::alloc | GlobalAlloc | trait | The `GlobalAlloc` trait is an `unsafe` trait for a number of reasons, and implementors must ensure that they adhere to these contracts: * It's undefined behavior if global allocators unwind. This restriction may be lifted in the future, but currently a panic from any of these functions may lead to memory unsafety. * `Layout` queries and calculations in general must be correct. Callers of this trait are allowed to rely on the contracts defined on each method, and implementors must ensure such contracts remain true. * You must not rely on allocations actually happening, even if there are explicit heap allocations in the source. The optimizer may detect unused allocations that it can either eliminate entirely or move to the stack and thus never invoke the allocator. The optimizer may further assume that allocation is infallible, so code that used to fail due to allocator failures may now suddenly work because the optimizer worked around the need for an allocation. More concretely, the following code example is unsound, irrespective of whether your custom allocator allows counting how many allocations have happened. ```rust,ignore (unsound and has placeholders) drop(Box::new(42)); let number_of_heap_allocs = /* call private allocator API */; unsafe { std::hint::assert_unchecked(number_of_heap_allocs > 0); } ``` Note that the optimizations mentioned above are not the only optimization that can be applied. You may generally not rely on heap allocations happening if they can be removed without changing program behavior. Whether allocations happen or not is not part of the program behavior, even if it could be detected via an allocator that tracks allocations by printing or otherwise having side effects. | |
| 59 | core::alloc::layout::Layout | for_value_raw | function | This function is only safe to call if the following conditions hold: - If `T` is `Sized`, this function is always safe to call. - If the unsized tail of `T` is: - a [slice], then the length of the slice tail must be an initialized integer, and the size of the *entire value* (dynamic tail length + statically sized prefix) must fit in `isize`. For the special case where the dynamic tail length is 0, this function is safe to call. - a [trait object], then the vtable part of the pointer must point to a valid vtable for the type `T` acquired by an unsizing coercion, and the size of the *entire value* (dynamic tail length + statically sized prefix) must fit in `isize`. - an (unstable) [extern type], then this function is always safe to call, but may panic or otherwise return the wrong value, as the extern type's layout is not known. This is the same behavior as [`Layout::for_value`] on a reference to an extern type tail. - otherwise, it is conservatively not allowed to call this function. [trait object]: ../../book/ch17-02-trait-objects.html [extern type]: ../../unstable-book/language-features/extern-types.html | |
| 60 | core::alloc::layout::Layout | from_size_align_unchecked | function | This function is unsafe as it does not verify the preconditions from [`Layout::from_size_align`]. | |
| 61 | core::alloc::layout::Layout | from_size_alignment_unchecked | function | This function is unsafe as it does not verify the preconditions from [`Layout::from_size_alignment`]. | |
| 62 | core::array | as_ascii_unchecked | function | Every byte in the array must be in `0..=127`, or else this is UB. | |
| 63 | core::array::iter::IntoIter | new_unchecked | function | - The `buffer[initialized]` elements must all be initialized. - The range must be canonical, with `initialized.start <= initialized.end`. - The range must be in-bounds for the buffer, with `initialized.end <= N`. (Like how indexing `[0][100..100]` fails despite the range being empty.) It's sound to have more elements initialized than mentioned, though that will most likely result in them being leaked. | |
| 64 | core::ascii::ascii_char::AsciiChar | digit_unchecked | function | This is immediate UB if called with `d > 64`. If `d >= 10` and `d <= 64`, this is allowed to return any value or panic. Notably, it should not be expected to return hex digits, or any other reasonable extension of the decimal digits. (This loose safety condition is intended to simplify soundness proofs when writing code using this method, since the implementation doesn't need something really specific, not to make those other arguments do something useful. It might be tightened before stabilization.) | |
| 65 | core::ascii::ascii_char::AsciiChar | from_u8_unchecked | function | `b` must be in `0..=127`, or else this is UB. | |
| 66 | core::cell | CloneFromCell | trait | Implementing this trait for a type is sound if and only if the following code is sound for T = that type. ``` #![feature(cell_get_cloned)] | |
| 67 | core::cell::RefCell | try_borrow_unguarded | function | Unlike `RefCell::borrow`, this method is unsafe because it does not return a `Ref`, thus leaving the borrow flag untouched. Mutably borrowing the `RefCell` while the reference returned by this method is alive is undefined behavior. | |
| 68 | core::cell::UnsafeCell | as_mut_unchecked | function | - It is Undefined Behavior to call this while any other reference(s) to the wrapped value are alive. - Mutating the wrapped value through other means while the returned reference is alive is Undefined Behavior. | |
| 69 | core::cell::UnsafeCell | as_ref_unchecked | function | - It is Undefined Behavior to call this while any mutable reference to the wrapped value is alive. - Mutating the wrapped value while the returned reference is alive is Undefined Behavior. | |
| 70 | core::cell::UnsafeCell | replace | function | The caller must take care to avoid aliasing and data races. - It is Undefined Behavior to allow calls to race with any other access to the wrapped value. - It is Undefined Behavior to call this while any other reference(s) to the wrapped value are alive. | |
| 71 | core::char | as_ascii_unchecked | function | This char must be within the ASCII range, or else this is UB. | |
| 72 | core::char | from_u32_unchecked | function | This function is unsafe, as it may construct invalid `char` values. For a safe version of this function, see the [`from_u32`] function. [`from_u32`]: #method.from_u32 | |
| 73 | core::clone | CloneToUninit | trait | Implementations must ensure that when `.clone_to_uninit(dest)` returns normally rather than panicking, it always leaves `*dest` initialized as a valid value of type `Self`. | |
| 74 | core::clone | TrivialClone | trait | `Clone::clone` must be equivalent to copying the value, otherwise calling functions such as `slice::clone_from_slice` can have undefined behaviour. | |
| 75 | core::core_arch::aarch64::mte | __arm_mte_create_random_tag | function | ||
| 76 | core::core_arch::aarch64::mte | __arm_mte_exclude_tag | function | ||
| 77 | core::core_arch::aarch64::mte | __arm_mte_get_tag | function | ||
| 78 | core::core_arch::aarch64::mte | __arm_mte_increment_tag | function | ||
| 79 | core::core_arch::aarch64::mte | __arm_mte_ptrdiff | function | ||
| 80 | core::core_arch::aarch64::mte | __arm_mte_set_tag | function | ||
| 81 | core::core_arch::aarch64::neon | vld1_dup_f64 | function | ||
| 82 | core::core_arch::aarch64::neon | vld1_lane_f64 | function | ||
| 83 | core::core_arch::aarch64::neon | vld1q_dup_f64 | function | ||
| 84 | core::core_arch::aarch64::neon | vld1q_lane_f64 | function | ||
| 85 | core::core_arch::aarch64::neon::generated | vld1_f16 | function | * Neon intrinsic unsafe | |
| 86 | core::core_arch::aarch64::neon::generated | vld1_f32 | function | * Neon intrinsic unsafe | |
| 87 | core::core_arch::aarch64::neon::generated | vld1_f64 | function | * Neon intrinsic unsafe | |
| 88 | core::core_arch::aarch64::neon::generated | vld1_f64_x2 | function | * Neon intrinsic unsafe | |
| 89 | core::core_arch::aarch64::neon::generated | vld1_f64_x3 | function | * Neon intrinsic unsafe | |
| 90 | core::core_arch::aarch64::neon::generated | vld1_f64_x4 | function | * Neon intrinsic unsafe | |
| 91 | core::core_arch::aarch64::neon::generated | vld1_p16 | function | * Neon intrinsic unsafe | |
| 92 | core::core_arch::aarch64::neon::generated | vld1_p64 | function | * Neon intrinsic unsafe | |
| 93 | core::core_arch::aarch64::neon::generated | vld1_p8 | function | * Neon intrinsic unsafe | |
| 94 | core::core_arch::aarch64::neon::generated | vld1_s16 | function | * Neon intrinsic unsafe | |
| 95 | core::core_arch::aarch64::neon::generated | vld1_s32 | function | * Neon intrinsic unsafe | |
| 96 | core::core_arch::aarch64::neon::generated | vld1_s64 | function | * Neon intrinsic unsafe | |
| 97 | core::core_arch::aarch64::neon::generated | vld1_s8 | function | * Neon intrinsic unsafe | |
| 98 | core::core_arch::aarch64::neon::generated | vld1_u16 | function | * Neon intrinsic unsafe | |
| 99 | core::core_arch::aarch64::neon::generated | vld1_u32 | function | * Neon intrinsic unsafe | |
| 100 | core::core_arch::aarch64::neon::generated | vld1_u64 | function | * Neon intrinsic unsafe | |
| 101 | core::core_arch::aarch64::neon::generated | vld1_u8 | function | * Neon intrinsic unsafe | |
| 102 | core::core_arch::aarch64::neon::generated | vld1q_f16 | function | * Neon intrinsic unsafe | |
| 103 | core::core_arch::aarch64::neon::generated | vld1q_f32 | function | * Neon intrinsic unsafe | |
| 104 | core::core_arch::aarch64::neon::generated | vld1q_f64 | function | * Neon intrinsic unsafe | |
| 105 | core::core_arch::aarch64::neon::generated | vld1q_f64_x2 | function | * Neon intrinsic unsafe | |
| 106 | core::core_arch::aarch64::neon::generated | vld1q_f64_x3 | function | * Neon intrinsic unsafe | |
| 107 | core::core_arch::aarch64::neon::generated | vld1q_f64_x4 | function | * Neon intrinsic unsafe | |
| 108 | core::core_arch::aarch64::neon::generated | vld1q_p16 | function | * Neon intrinsic unsafe | |
| 109 | core::core_arch::aarch64::neon::generated | vld1q_p64 | function | * Neon intrinsic unsafe | |
| 110 | core::core_arch::aarch64::neon::generated | vld1q_p8 | function | * Neon intrinsic unsafe | |
| 111 | core::core_arch::aarch64::neon::generated | vld1q_s16 | function | * Neon intrinsic unsafe | |
| 112 | core::core_arch::aarch64::neon::generated | vld1q_s32 | function | * Neon intrinsic unsafe | |
| 113 | core::core_arch::aarch64::neon::generated | vld1q_s64 | function | * Neon intrinsic unsafe | |
| 114 | core::core_arch::aarch64::neon::generated | vld1q_s8 | function | * Neon intrinsic unsafe | |
| 115 | core::core_arch::aarch64::neon::generated | vld1q_u16 | function | * Neon intrinsic unsafe | |
| 116 | core::core_arch::aarch64::neon::generated | vld1q_u32 | function | * Neon intrinsic unsafe | |
| 117 | core::core_arch::aarch64::neon::generated | vld1q_u64 | function | * Neon intrinsic unsafe | |
| 118 | core::core_arch::aarch64::neon::generated | vld1q_u8 | function | * Neon intrinsic unsafe | |
| 119 | core::core_arch::aarch64::neon::generated | vld2_dup_f64 | function | * Neon intrinsic unsafe | |
| 120 | core::core_arch::aarch64::neon::generated | vld2_f64 | function | * Neon intrinsic unsafe | |
| 121 | core::core_arch::aarch64::neon::generated | vld2_lane_f64 | function | * Neon intrinsic unsafe | |
| 122 | core::core_arch::aarch64::neon::generated | vld2_lane_p64 | function | * Neon intrinsic unsafe | |
| 123 | core::core_arch::aarch64::neon::generated | vld2_lane_s64 | function | * Neon intrinsic unsafe | |
| 124 | core::core_arch::aarch64::neon::generated | vld2_lane_u64 | function | * Neon intrinsic unsafe | |
| 125 | core::core_arch::aarch64::neon::generated | vld2q_dup_f64 | function | * Neon intrinsic unsafe | |
| 126 | core::core_arch::aarch64::neon::generated | vld2q_dup_p64 | function | * Neon intrinsic unsafe | |
| 127 | core::core_arch::aarch64::neon::generated | vld2q_dup_s64 | function | * Neon intrinsic unsafe | |
| 128 | core::core_arch::aarch64::neon::generated | vld2q_dup_u64 | function | * Neon intrinsic unsafe | |
| 129 | core::core_arch::aarch64::neon::generated | vld2q_f64 | function | * Neon intrinsic unsafe | |
| 130 | core::core_arch::aarch64::neon::generated | vld2q_lane_f64 | function | * Neon intrinsic unsafe | |
| 131 | core::core_arch::aarch64::neon::generated | vld2q_lane_p64 | function | * Neon intrinsic unsafe | |
| 132 | core::core_arch::aarch64::neon::generated | vld2q_lane_p8 | function | * Neon intrinsic unsafe | |
| 133 | core::core_arch::aarch64::neon::generated | vld2q_lane_s64 | function | * Neon intrinsic unsafe | |
| 134 | core::core_arch::aarch64::neon::generated | vld2q_lane_s8 | function | * Neon intrinsic unsafe | |
| 135 | core::core_arch::aarch64::neon::generated | vld2q_lane_u64 | function | * Neon intrinsic unsafe | |
| 136 | core::core_arch::aarch64::neon::generated | vld2q_lane_u8 | function | * Neon intrinsic unsafe | |
| 137 | core::core_arch::aarch64::neon::generated | vld2q_p64 | function | * Neon intrinsic unsafe | |
| 138 | core::core_arch::aarch64::neon::generated | vld2q_s64 | function | * Neon intrinsic unsafe | |
| 139 | core::core_arch::aarch64::neon::generated | vld2q_u64 | function | * Neon intrinsic unsafe | |
| 140 | core::core_arch::aarch64::neon::generated | vld3_dup_f64 | function | * Neon intrinsic unsafe | |
| 141 | core::core_arch::aarch64::neon::generated | vld3_f64 | function | * Neon intrinsic unsafe | |
| 142 | core::core_arch::aarch64::neon::generated | vld3_lane_f64 | function | * Neon intrinsic unsafe | |
| 143 | core::core_arch::aarch64::neon::generated | vld3_lane_p64 | function | * Neon intrinsic unsafe | |
| 144 | core::core_arch::aarch64::neon::generated | vld3_lane_s64 | function | * Neon intrinsic unsafe | |
| 145 | core::core_arch::aarch64::neon::generated | vld3_lane_u64 | function | * Neon intrinsic unsafe | |
| 146 | core::core_arch::aarch64::neon::generated | vld3q_dup_f64 | function | * Neon intrinsic unsafe | |
| 147 | core::core_arch::aarch64::neon::generated | vld3q_dup_p64 | function | * Neon intrinsic unsafe | |
| 148 | core::core_arch::aarch64::neon::generated | vld3q_dup_s64 | function | * Neon intrinsic unsafe | |
| 149 | core::core_arch::aarch64::neon::generated | vld3q_dup_u64 | function | * Neon intrinsic unsafe | |
| 150 | core::core_arch::aarch64::neon::generated | vld3q_f64 | function | * Neon intrinsic unsafe | |
| 151 | core::core_arch::aarch64::neon::generated | vld3q_lane_f64 | function | * Neon intrinsic unsafe | |
| 152 | core::core_arch::aarch64::neon::generated | vld3q_lane_p64 | function | * Neon intrinsic unsafe | |
| 153 | core::core_arch::aarch64::neon::generated | vld3q_lane_p8 | function | * Neon intrinsic unsafe | |
| 154 | core::core_arch::aarch64::neon::generated | vld3q_lane_s64 | function | * Neon intrinsic unsafe | |
| 155 | core::core_arch::aarch64::neon::generated | vld3q_lane_s8 | function | * Neon intrinsic unsafe | |
| 156 | core::core_arch::aarch64::neon::generated | vld3q_lane_u64 | function | * Neon intrinsic unsafe | |
| 157 | core::core_arch::aarch64::neon::generated | vld3q_lane_u8 | function | * Neon intrinsic unsafe | |
| 158 | core::core_arch::aarch64::neon::generated | vld3q_p64 | function | * Neon intrinsic unsafe | |
| 159 | core::core_arch::aarch64::neon::generated | vld3q_s64 | function | * Neon intrinsic unsafe | |
| 160 | core::core_arch::aarch64::neon::generated | vld3q_u64 | function | * Neon intrinsic unsafe | |
| 161 | core::core_arch::aarch64::neon::generated | vld4_dup_f64 | function | * Neon intrinsic unsafe | |
| 162 | core::core_arch::aarch64::neon::generated | vld4_f64 | function | * Neon intrinsic unsafe | |
| 163 | core::core_arch::aarch64::neon::generated | vld4_lane_f64 | function | * Neon intrinsic unsafe | |
| 164 | core::core_arch::aarch64::neon::generated | vld4_lane_p64 | function | * Neon intrinsic unsafe | |
| 165 | core::core_arch::aarch64::neon::generated | vld4_lane_s64 | function | * Neon intrinsic unsafe | |
| 166 | core::core_arch::aarch64::neon::generated | vld4_lane_u64 | function | * Neon intrinsic unsafe | |
| 167 | core::core_arch::aarch64::neon::generated | vld4q_dup_f64 | function | * Neon intrinsic unsafe | |
| 168 | core::core_arch::aarch64::neon::generated | vld4q_dup_p64 | function | * Neon intrinsic unsafe | |
| 169 | core::core_arch::aarch64::neon::generated | vld4q_dup_s64 | function | * Neon intrinsic unsafe | |
| 170 | core::core_arch::aarch64::neon::generated | vld4q_dup_u64 | function | * Neon intrinsic unsafe | |
| 171 | core::core_arch::aarch64::neon::generated | vld4q_f64 | function | * Neon intrinsic unsafe | |
| 172 | core::core_arch::aarch64::neon::generated | vld4q_lane_f64 | function | * Neon intrinsic unsafe | |
| 173 | core::core_arch::aarch64::neon::generated | vld4q_lane_p64 | function | * Neon intrinsic unsafe | |
| 174 | core::core_arch::aarch64::neon::generated | vld4q_lane_p8 | function | * Neon intrinsic unsafe | |
| 175 | core::core_arch::aarch64::neon::generated | vld4q_lane_s64 | function | * Neon intrinsic unsafe | |
| 176 | core::core_arch::aarch64::neon::generated | vld4q_lane_s8 | function | * Neon intrinsic unsafe | |
| 177 | core::core_arch::aarch64::neon::generated | vld4q_lane_u64 | function | * Neon intrinsic unsafe | |
| 178 | core::core_arch::aarch64::neon::generated | vld4q_lane_u8 | function | * Neon intrinsic unsafe | |
| 179 | core::core_arch::aarch64::neon::generated | vld4q_p64 | function | * Neon intrinsic unsafe | |
| 180 | core::core_arch::aarch64::neon::generated | vld4q_s64 | function | * Neon intrinsic unsafe | |
| 181 | core::core_arch::aarch64::neon::generated | vld4q_u64 | function | * Neon intrinsic unsafe | |
| 182 | core::core_arch::aarch64::neon::generated | vldap1_lane_p64 | function | * Neon intrinsic unsafe | |
| 183 | core::core_arch::aarch64::neon::generated | vldap1_lane_s64 | function | * Neon intrinsic unsafe | |
| 184 | core::core_arch::aarch64::neon::generated | vldap1_lane_u64 | function | * Neon intrinsic unsafe | |
| 185 | core::core_arch::aarch64::neon::generated | vldap1q_lane_f64 | function | * Neon intrinsic unsafe | |
| 186 | core::core_arch::aarch64::neon::generated | vldap1q_lane_p64 | function | * Neon intrinsic unsafe | |
| 187 | core::core_arch::aarch64::neon::generated | vldap1q_lane_s64 | function | * Neon intrinsic unsafe | |
| 188 | core::core_arch::aarch64::neon::generated | vldap1q_lane_u64 | function | * Neon intrinsic unsafe | |
| 189 | core::core_arch::aarch64::neon::generated | vluti2_lane_f16 | function | * Neon intrinsic unsafe | |
| 190 | core::core_arch::aarch64::neon::generated | vluti2_lane_p16 | function | * Neon intrinsic unsafe | |
| 191 | core::core_arch::aarch64::neon::generated | vluti2_lane_p8 | function | * Neon intrinsic unsafe | |
| 192 | core::core_arch::aarch64::neon::generated | vluti2_lane_s16 | function | * Neon intrinsic unsafe | |
| 193 | core::core_arch::aarch64::neon::generated | vluti2_lane_s8 | function | * Neon intrinsic unsafe | |
| 194 | core::core_arch::aarch64::neon::generated | vluti2_lane_u16 | function | * Neon intrinsic unsafe | |
| 195 | core::core_arch::aarch64::neon::generated | vluti2_lane_u8 | function | * Neon intrinsic unsafe | |
| 196 | core::core_arch::aarch64::neon::generated | vluti2_laneq_f16 | function | * Neon intrinsic unsafe | |
| 197 | core::core_arch::aarch64::neon::generated | vluti2_laneq_p16 | function | * Neon intrinsic unsafe | |
| 198 | core::core_arch::aarch64::neon::generated | vluti2_laneq_p8 | function | * Neon intrinsic unsafe | |
| 199 | core::core_arch::aarch64::neon::generated | vluti2_laneq_s16 | function | * Neon intrinsic unsafe | |
| 200 | core::core_arch::aarch64::neon::generated | vluti2_laneq_s8 | function | * Neon intrinsic unsafe | |
| 201 | core::core_arch::aarch64::neon::generated | vluti2_laneq_u16 | function | * Neon intrinsic unsafe | |
| 202 | core::core_arch::aarch64::neon::generated | vluti2_laneq_u8 | function | * Neon intrinsic unsafe | |
| 203 | core::core_arch::aarch64::neon::generated | vluti2q_lane_f16 | function | * Neon intrinsic unsafe | |
| 204 | core::core_arch::aarch64::neon::generated | vluti2q_lane_p16 | function | * Neon intrinsic unsafe | |
| 205 | core::core_arch::aarch64::neon::generated | vluti2q_lane_p8 | function | * Neon intrinsic unsafe | |
| 206 | core::core_arch::aarch64::neon::generated | vluti2q_lane_s16 | function | * Neon intrinsic unsafe | |
| 207 | core::core_arch::aarch64::neon::generated | vluti2q_lane_s8 | function | * Neon intrinsic unsafe | |
| 208 | core::core_arch::aarch64::neon::generated | vluti2q_lane_u16 | function | * Neon intrinsic unsafe | |
| 209 | core::core_arch::aarch64::neon::generated | vluti2q_lane_u8 | function | * Neon intrinsic unsafe | |
| 210 | core::core_arch::aarch64::neon::generated | vluti2q_laneq_f16 | function | * Neon intrinsic unsafe | |
| 211 | core::core_arch::aarch64::neon::generated | vluti2q_laneq_p16 | function | * Neon intrinsic unsafe | |
| 212 | core::core_arch::aarch64::neon::generated | vluti2q_laneq_p8 | function | * Neon intrinsic unsafe | |
| 213 | core::core_arch::aarch64::neon::generated | vluti2q_laneq_s16 | function | * Neon intrinsic unsafe | |
| 214 | core::core_arch::aarch64::neon::generated | vluti2q_laneq_s8 | function | * Neon intrinsic unsafe | |
| 215 | core::core_arch::aarch64::neon::generated | vluti2q_laneq_u16 | function | * Neon intrinsic unsafe | |
| 216 | core::core_arch::aarch64::neon::generated | vluti2q_laneq_u8 | function | * Neon intrinsic unsafe | |
| 217 | core::core_arch::aarch64::neon::generated | vluti4q_lane_f16_x2 | function | * Neon intrinsic unsafe | |
| 218 | core::core_arch::aarch64::neon::generated | vluti4q_lane_p16_x2 | function | * Neon intrinsic unsafe | |
| 219 | core::core_arch::aarch64::neon::generated | vluti4q_lane_p8 | function | * Neon intrinsic unsafe | |
| 220 | core::core_arch::aarch64::neon::generated | vluti4q_lane_s16_x2 | function | * Neon intrinsic unsafe | |
| 221 | core::core_arch::aarch64::neon::generated | vluti4q_lane_s8 | function | * Neon intrinsic unsafe | |
| 222 | core::core_arch::aarch64::neon::generated | vluti4q_lane_u16_x2 | function | * Neon intrinsic unsafe | |
| 223 | core::core_arch::aarch64::neon::generated | vluti4q_lane_u8 | function | * Neon intrinsic unsafe | |
| 224 | core::core_arch::aarch64::neon::generated | vluti4q_laneq_f16_x2 | function | * Neon intrinsic unsafe | |
| 225 | core::core_arch::aarch64::neon::generated | vluti4q_laneq_p16_x2 | function | * Neon intrinsic unsafe | |
| 226 | core::core_arch::aarch64::neon::generated | vluti4q_laneq_p8 | function | * Neon intrinsic unsafe | |
| 227 | core::core_arch::aarch64::neon::generated | vluti4q_laneq_s16_x2 | function | * Neon intrinsic unsafe | |
| 228 | core::core_arch::aarch64::neon::generated | vluti4q_laneq_s8 | function | * Neon intrinsic unsafe | |
| 229 | core::core_arch::aarch64::neon::generated | vluti4q_laneq_u16_x2 | function | * Neon intrinsic unsafe | |
| 230 | core::core_arch::aarch64::neon::generated | vluti4q_laneq_u8 | function | * Neon intrinsic unsafe | |
| 231 | core::core_arch::aarch64::neon::generated | vst1_f16 | function | * Neon intrinsic unsafe | |
| 232 | core::core_arch::aarch64::neon::generated | vst1_f32 | function | * Neon intrinsic unsafe | |
| 233 | core::core_arch::aarch64::neon::generated | vst1_f64 | function | * Neon intrinsic unsafe | |
| 234 | core::core_arch::aarch64::neon::generated | vst1_f64_x2 | function | * Neon intrinsic unsafe | |
| 235 | core::core_arch::aarch64::neon::generated | vst1_f64_x3 | function | * Neon intrinsic unsafe | |
| 236 | core::core_arch::aarch64::neon::generated | vst1_f64_x4 | function | * Neon intrinsic unsafe | |
| 237 | core::core_arch::aarch64::neon::generated | vst1_lane_f64 | function | * Neon intrinsic unsafe | |
| 238 | core::core_arch::aarch64::neon::generated | vst1_p16 | function | * Neon intrinsic unsafe | |
| 239 | core::core_arch::aarch64::neon::generated | vst1_p64 | function | * Neon intrinsic unsafe | |
| 240 | core::core_arch::aarch64::neon::generated | vst1_p8 | function | * Neon intrinsic unsafe | |
| 241 | core::core_arch::aarch64::neon::generated | vst1_s16 | function | * Neon intrinsic unsafe | |
| 242 | core::core_arch::aarch64::neon::generated | vst1_s32 | function | * Neon intrinsic unsafe | |
| 243 | core::core_arch::aarch64::neon::generated | vst1_s64 | function | * Neon intrinsic unsafe | |
| 244 | core::core_arch::aarch64::neon::generated | vst1_s8 | function | * Neon intrinsic unsafe | |
| 245 | core::core_arch::aarch64::neon::generated | vst1_u16 | function | * Neon intrinsic unsafe | |
| 246 | core::core_arch::aarch64::neon::generated | vst1_u32 | function | * Neon intrinsic unsafe | |
| 247 | core::core_arch::aarch64::neon::generated | vst1_u64 | function | * Neon intrinsic unsafe | |
| 248 | core::core_arch::aarch64::neon::generated | vst1_u8 | function | * Neon intrinsic unsafe | |
| 249 | core::core_arch::aarch64::neon::generated | vst1q_f16 | function | * Neon intrinsic unsafe | |
| 250 | core::core_arch::aarch64::neon::generated | vst1q_f32 | function | * Neon intrinsic unsafe | |
| 251 | core::core_arch::aarch64::neon::generated | vst1q_f64 | function | * Neon intrinsic unsafe | |
| 252 | core::core_arch::aarch64::neon::generated | vst1q_f64_x2 | function | * Neon intrinsic unsafe | |
| 253 | core::core_arch::aarch64::neon::generated | vst1q_f64_x3 | function | * Neon intrinsic unsafe | |
| 254 | core::core_arch::aarch64::neon::generated | vst1q_f64_x4 | function | * Neon intrinsic unsafe | |
| 255 | core::core_arch::aarch64::neon::generated | vst1q_lane_f64 | function | * Neon intrinsic unsafe | |
| 256 | core::core_arch::aarch64::neon::generated | vst1q_p16 | function | * Neon intrinsic unsafe | |
| 257 | core::core_arch::aarch64::neon::generated | vst1q_p64 | function | * Neon intrinsic unsafe | |
| 258 | core::core_arch::aarch64::neon::generated | vst1q_p8 | function | * Neon intrinsic unsafe | |
| 259 | core::core_arch::aarch64::neon::generated | vst1q_s16 | function | * Neon intrinsic unsafe | |
| 260 | core::core_arch::aarch64::neon::generated | vst1q_s32 | function | * Neon intrinsic unsafe | |
| 261 | core::core_arch::aarch64::neon::generated | vst1q_s64 | function | * Neon intrinsic unsafe | |
| 262 | core::core_arch::aarch64::neon::generated | vst1q_s8 | function | * Neon intrinsic unsafe | |
| 263 | core::core_arch::aarch64::neon::generated | vst1q_u16 | function | * Neon intrinsic unsafe | |
| 264 | core::core_arch::aarch64::neon::generated | vst1q_u32 | function | * Neon intrinsic unsafe | |
| 265 | core::core_arch::aarch64::neon::generated | vst1q_u64 | function | * Neon intrinsic unsafe | |
| 266 | core::core_arch::aarch64::neon::generated | vst1q_u8 | function | * Neon intrinsic unsafe | |
| 267 | core::core_arch::aarch64::neon::generated | vst2_f64 | function | * Neon intrinsic unsafe | |
| 268 | core::core_arch::aarch64::neon::generated | vst2_lane_f64 | function | * Neon intrinsic unsafe | |
| 269 | core::core_arch::aarch64::neon::generated | vst2_lane_p64 | function | * Neon intrinsic unsafe | |
| 270 | core::core_arch::aarch64::neon::generated | vst2_lane_s64 | function | * Neon intrinsic unsafe | |
| 271 | core::core_arch::aarch64::neon::generated | vst2_lane_u64 | function | * Neon intrinsic unsafe | |
| 272 | core::core_arch::aarch64::neon::generated | vst2q_f64 | function | * Neon intrinsic unsafe | |
| 273 | core::core_arch::aarch64::neon::generated | vst2q_lane_f64 | function | * Neon intrinsic unsafe | |
| 274 | core::core_arch::aarch64::neon::generated | vst2q_lane_p64 | function | * Neon intrinsic unsafe | |
| 275 | core::core_arch::aarch64::neon::generated | vst2q_lane_p8 | function | * Neon intrinsic unsafe | |
| 276 | core::core_arch::aarch64::neon::generated | vst2q_lane_s64 | function | * Neon intrinsic unsafe | |
| 277 | core::core_arch::aarch64::neon::generated | vst2q_lane_s8 | function | * Neon intrinsic unsafe | |
| 278 | core::core_arch::aarch64::neon::generated | vst2q_lane_u64 | function | * Neon intrinsic unsafe | |
| 279 | core::core_arch::aarch64::neon::generated | vst2q_lane_u8 | function | * Neon intrinsic unsafe | |
| 280 | core::core_arch::aarch64::neon::generated | vst2q_p64 | function | * Neon intrinsic unsafe | |
| 281 | core::core_arch::aarch64::neon::generated | vst2q_s64 | function | * Neon intrinsic unsafe | |
| 282 | core::core_arch::aarch64::neon::generated | vst2q_u64 | function | * Neon intrinsic unsafe | |
| 283 | core::core_arch::aarch64::neon::generated | vst3_f64 | function | * Neon intrinsic unsafe | |
| 284 | core::core_arch::aarch64::neon::generated | vst3_lane_f64 | function | * Neon intrinsic unsafe | |
| 285 | core::core_arch::aarch64::neon::generated | vst3_lane_p64 | function | * Neon intrinsic unsafe | |
| 286 | core::core_arch::aarch64::neon::generated | vst3_lane_s64 | function | * Neon intrinsic unsafe | |
| 287 | core::core_arch::aarch64::neon::generated | vst3_lane_u64 | function | * Neon intrinsic unsafe | |
| 288 | core::core_arch::aarch64::neon::generated | vst3q_f64 | function | * Neon intrinsic unsafe | |
| 289 | core::core_arch::aarch64::neon::generated | vst3q_lane_f64 | function | * Neon intrinsic unsafe | |
| 290 | core::core_arch::aarch64::neon::generated | vst3q_lane_p64 | function | * Neon intrinsic unsafe | |
| 291 | core::core_arch::aarch64::neon::generated | vst3q_lane_p8 | function | * Neon intrinsic unsafe | |
| 292 | core::core_arch::aarch64::neon::generated | vst3q_lane_s64 | function | * Neon intrinsic unsafe | |
| 293 | core::core_arch::aarch64::neon::generated | vst3q_lane_s8 | function | * Neon intrinsic unsafe | |
| 294 | core::core_arch::aarch64::neon::generated | vst3q_lane_u64 | function | * Neon intrinsic unsafe | |
| 295 | core::core_arch::aarch64::neon::generated | vst3q_lane_u8 | function | * Neon intrinsic unsafe | |
| 296 | core::core_arch::aarch64::neon::generated | vst3q_p64 | function | * Neon intrinsic unsafe | |
| 297 | core::core_arch::aarch64::neon::generated | vst3q_s64 | function | * Neon intrinsic unsafe | |
| 298 | core::core_arch::aarch64::neon::generated | vst3q_u64 | function | * Neon intrinsic unsafe | |
| 299 | core::core_arch::aarch64::neon::generated | vst4_f64 | function | * Neon intrinsic unsafe | |
| 300 | core::core_arch::aarch64::neon::generated | vst4_lane_f64 | function | * Neon intrinsic unsafe | |
| 301 | core::core_arch::aarch64::neon::generated | vst4_lane_p64 | function | * Neon intrinsic unsafe | |
| 302 | core::core_arch::aarch64::neon::generated | vst4_lane_s64 | function | * Neon intrinsic unsafe | |
| 303 | core::core_arch::aarch64::neon::generated | vst4_lane_u64 | function | * Neon intrinsic unsafe | |
| 304 | core::core_arch::aarch64::neon::generated | vst4q_f64 | function | * Neon intrinsic unsafe | |
| 305 | core::core_arch::aarch64::neon::generated | vst4q_lane_f64 | function | * Neon intrinsic unsafe | |
| 306 | core::core_arch::aarch64::neon::generated | vst4q_lane_p64 | function | * Neon intrinsic unsafe | |
| 307 | core::core_arch::aarch64::neon::generated | vst4q_lane_p8 | function | * Neon intrinsic unsafe | |
| 308 | core::core_arch::aarch64::neon::generated | vst4q_lane_s64 | function | * Neon intrinsic unsafe | |
| 309 | core::core_arch::aarch64::neon::generated | vst4q_lane_s8 | function | * Neon intrinsic unsafe | |
| 310 | core::core_arch::aarch64::neon::generated | vst4q_lane_u64 | function | * Neon intrinsic unsafe | |
| 311 | core::core_arch::aarch64::neon::generated | vst4q_lane_u8 | function | * Neon intrinsic unsafe | |
| 312 | core::core_arch::aarch64::neon::generated | vst4q_p64 | function | * Neon intrinsic unsafe | |
| 313 | core::core_arch::aarch64::neon::generated | vst4q_s64 | function | * Neon intrinsic unsafe | |
| 314 | core::core_arch::aarch64::neon::generated | vst4q_u64 | function | * Neon intrinsic unsafe | |
| 315 | core::core_arch::aarch64::neon::generated | vstl1_lane_f64 | function | * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]. | |
| 316 | core::core_arch::aarch64::neon::generated | vstl1_lane_p64 | function | * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]. | |
| 317 | core::core_arch::aarch64::neon::generated | vstl1_lane_s64 | function | * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]. | |
| 318 | core::core_arch::aarch64::neon::generated | vstl1_lane_u64 | function | * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]. | |
| 319 | core::core_arch::aarch64::neon::generated | vstl1q_lane_f64 | function | * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]. | |
| 320 | core::core_arch::aarch64::neon::generated | vstl1q_lane_p64 | function | * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]. | |
| 321 | core::core_arch::aarch64::neon::generated | vstl1q_lane_s64 | function | * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]. | |
| 322 | core::core_arch::aarch64::neon::generated | vstl1q_lane_u64 | function | * The pointer in `ptr` must satisfy the requirements of [`core::ptr::write`]. | |
| 323 | core::core_arch::aarch64::prefetch | _prefetch | function | ||
| 324 | core::core_arch::aarch64::rand | __rndr | function | ||
| 325 | core::core_arch::aarch64::rand | __rndrrs | function | ||
| 326 | core::core_arch::aarch64::sve2::generated | svldnt1_gather_s64index_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 327 | core::core_arch::aarch64::sve2::generated | svldnt1_gather_s64index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 328 | core::core_arch::aarch64::sve2::generated | svldnt1_gather_s64index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 329 | core::core_arch::aarch64::sve2::generated | svldnt1_gather_s64offset_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 330 | core::core_arch::aarch64::sve2::generated | svldnt1_gather_s64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 331 | core::core_arch::aarch64::sve2::generated | svldnt1_gather_s64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 332 | core::core_arch::aarch64::sve2::generated | svldnt1_gather_u32base_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 333 | core::core_arch::aarch64::sve2::generated | svldnt1_gather_u32base_index_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 334 | core::core_arch::aarch64::sve2::generated | svldnt1_gather_u32base_index_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 335 | core::core_arch::aarch64::sve2::generated | svldnt1_gather_u32base_index_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 336 | core::core_arch::aarch64::sve2::generated | svldnt1_gather_u32base_offset_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 337 | core::core_arch::aarch64::sve2::generated | svldnt1_gather_u32base_offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 338 | core::core_arch::aarch64::sve2::generated | svldnt1_gather_u32base_offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 339 | core::core_arch::aarch64::sve2::generated | svldnt1_gather_u32base_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 340 | core::core_arch::aarch64::sve2::generated | svldnt1_gather_u32base_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 341 | core::core_arch::aarch64::sve2::generated | svldnt1_gather_u32offset_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 342 | core::core_arch::aarch64::sve2::generated | svldnt1_gather_u32offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 343 | core::core_arch::aarch64::sve2::generated | svldnt1_gather_u32offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 344 | core::core_arch::aarch64::sve2::generated | svldnt1_gather_u64base_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 345 | core::core_arch::aarch64::sve2::generated | svldnt1_gather_u64base_index_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 346 | core::core_arch::aarch64::sve2::generated | svldnt1_gather_u64base_index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 347 | core::core_arch::aarch64::sve2::generated | svldnt1_gather_u64base_index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 348 | core::core_arch::aarch64::sve2::generated | svldnt1_gather_u64base_offset_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 349 | core::core_arch::aarch64::sve2::generated | svldnt1_gather_u64base_offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 350 | core::core_arch::aarch64::sve2::generated | svldnt1_gather_u64base_offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 351 | core::core_arch::aarch64::sve2::generated | svldnt1_gather_u64base_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 352 | core::core_arch::aarch64::sve2::generated | svldnt1_gather_u64base_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 353 | core::core_arch::aarch64::sve2::generated | svldnt1_gather_u64index_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 354 | core::core_arch::aarch64::sve2::generated | svldnt1_gather_u64index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 355 | core::core_arch::aarch64::sve2::generated | svldnt1_gather_u64index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 356 | core::core_arch::aarch64::sve2::generated | svldnt1_gather_u64offset_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 357 | core::core_arch::aarch64::sve2::generated | svldnt1_gather_u64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 358 | core::core_arch::aarch64::sve2::generated | svldnt1_gather_u64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 359 | core::core_arch::aarch64::sve2::generated | svldnt1sb_gather_s64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 360 | core::core_arch::aarch64::sve2::generated | svldnt1sb_gather_s64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 361 | core::core_arch::aarch64::sve2::generated | svldnt1sb_gather_u32base_offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 362 | core::core_arch::aarch64::sve2::generated | svldnt1sb_gather_u32base_offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 363 | core::core_arch::aarch64::sve2::generated | svldnt1sb_gather_u32base_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 364 | core::core_arch::aarch64::sve2::generated | svldnt1sb_gather_u32base_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 365 | core::core_arch::aarch64::sve2::generated | svldnt1sb_gather_u32offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 366 | core::core_arch::aarch64::sve2::generated | svldnt1sb_gather_u32offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 367 | core::core_arch::aarch64::sve2::generated | svldnt1sb_gather_u64base_offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 368 | core::core_arch::aarch64::sve2::generated | svldnt1sb_gather_u64base_offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 369 | core::core_arch::aarch64::sve2::generated | svldnt1sb_gather_u64base_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 370 | core::core_arch::aarch64::sve2::generated | svldnt1sb_gather_u64base_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 371 | core::core_arch::aarch64::sve2::generated | svldnt1sb_gather_u64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 372 | core::core_arch::aarch64::sve2::generated | svldnt1sb_gather_u64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 373 | core::core_arch::aarch64::sve2::generated | svldnt1sh_gather_s64index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 374 | core::core_arch::aarch64::sve2::generated | svldnt1sh_gather_s64index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 375 | core::core_arch::aarch64::sve2::generated | svldnt1sh_gather_s64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 376 | core::core_arch::aarch64::sve2::generated | svldnt1sh_gather_s64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 377 | core::core_arch::aarch64::sve2::generated | svldnt1sh_gather_u32base_index_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 378 | core::core_arch::aarch64::sve2::generated | svldnt1sh_gather_u32base_index_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 379 | core::core_arch::aarch64::sve2::generated | svldnt1sh_gather_u32base_offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 380 | core::core_arch::aarch64::sve2::generated | svldnt1sh_gather_u32base_offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 381 | core::core_arch::aarch64::sve2::generated | svldnt1sh_gather_u32base_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 382 | core::core_arch::aarch64::sve2::generated | svldnt1sh_gather_u32base_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 383 | core::core_arch::aarch64::sve2::generated | svldnt1sh_gather_u32offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 384 | core::core_arch::aarch64::sve2::generated | svldnt1sh_gather_u32offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 385 | core::core_arch::aarch64::sve2::generated | svldnt1sh_gather_u64base_index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 386 | core::core_arch::aarch64::sve2::generated | svldnt1sh_gather_u64base_index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 387 | core::core_arch::aarch64::sve2::generated | svldnt1sh_gather_u64base_offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 388 | core::core_arch::aarch64::sve2::generated | svldnt1sh_gather_u64base_offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 389 | core::core_arch::aarch64::sve2::generated | svldnt1sh_gather_u64base_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 390 | core::core_arch::aarch64::sve2::generated | svldnt1sh_gather_u64base_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 391 | core::core_arch::aarch64::sve2::generated | svldnt1sh_gather_u64index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 392 | core::core_arch::aarch64::sve2::generated | svldnt1sh_gather_u64index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 393 | core::core_arch::aarch64::sve2::generated | svldnt1sh_gather_u64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 394 | core::core_arch::aarch64::sve2::generated | svldnt1sh_gather_u64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 395 | core::core_arch::aarch64::sve2::generated | svldnt1sw_gather_s64index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 396 | core::core_arch::aarch64::sve2::generated | svldnt1sw_gather_s64index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 397 | core::core_arch::aarch64::sve2::generated | svldnt1sw_gather_s64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 398 | core::core_arch::aarch64::sve2::generated | svldnt1sw_gather_s64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 399 | core::core_arch::aarch64::sve2::generated | svldnt1sw_gather_u64base_index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 400 | core::core_arch::aarch64::sve2::generated | svldnt1sw_gather_u64base_index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 401 | core::core_arch::aarch64::sve2::generated | svldnt1sw_gather_u64base_offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 402 | core::core_arch::aarch64::sve2::generated | svldnt1sw_gather_u64base_offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 403 | core::core_arch::aarch64::sve2::generated | svldnt1sw_gather_u64base_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 404 | core::core_arch::aarch64::sve2::generated | svldnt1sw_gather_u64base_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 405 | core::core_arch::aarch64::sve2::generated | svldnt1sw_gather_u64index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 406 | core::core_arch::aarch64::sve2::generated | svldnt1sw_gather_u64index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 407 | core::core_arch::aarch64::sve2::generated | svldnt1sw_gather_u64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 408 | core::core_arch::aarch64::sve2::generated | svldnt1sw_gather_u64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 409 | core::core_arch::aarch64::sve2::generated | svldnt1ub_gather_s64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 410 | core::core_arch::aarch64::sve2::generated | svldnt1ub_gather_s64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 411 | core::core_arch::aarch64::sve2::generated | svldnt1ub_gather_u32base_offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 412 | core::core_arch::aarch64::sve2::generated | svldnt1ub_gather_u32base_offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 413 | core::core_arch::aarch64::sve2::generated | svldnt1ub_gather_u32base_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 414 | core::core_arch::aarch64::sve2::generated | svldnt1ub_gather_u32base_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 415 | core::core_arch::aarch64::sve2::generated | svldnt1ub_gather_u32offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 416 | core::core_arch::aarch64::sve2::generated | svldnt1ub_gather_u32offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 417 | core::core_arch::aarch64::sve2::generated | svldnt1ub_gather_u64base_offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 418 | core::core_arch::aarch64::sve2::generated | svldnt1ub_gather_u64base_offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 419 | core::core_arch::aarch64::sve2::generated | svldnt1ub_gather_u64base_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 420 | core::core_arch::aarch64::sve2::generated | svldnt1ub_gather_u64base_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 421 | core::core_arch::aarch64::sve2::generated | svldnt1ub_gather_u64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 422 | core::core_arch::aarch64::sve2::generated | svldnt1ub_gather_u64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 423 | core::core_arch::aarch64::sve2::generated | svldnt1uh_gather_s64index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 424 | core::core_arch::aarch64::sve2::generated | svldnt1uh_gather_s64index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 425 | core::core_arch::aarch64::sve2::generated | svldnt1uh_gather_s64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 426 | core::core_arch::aarch64::sve2::generated | svldnt1uh_gather_s64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 427 | core::core_arch::aarch64::sve2::generated | svldnt1uh_gather_u32base_index_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 428 | core::core_arch::aarch64::sve2::generated | svldnt1uh_gather_u32base_index_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 429 | core::core_arch::aarch64::sve2::generated | svldnt1uh_gather_u32base_offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 430 | core::core_arch::aarch64::sve2::generated | svldnt1uh_gather_u32base_offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 431 | core::core_arch::aarch64::sve2::generated | svldnt1uh_gather_u32base_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 432 | core::core_arch::aarch64::sve2::generated | svldnt1uh_gather_u32base_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 433 | core::core_arch::aarch64::sve2::generated | svldnt1uh_gather_u32offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 434 | core::core_arch::aarch64::sve2::generated | svldnt1uh_gather_u32offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 435 | core::core_arch::aarch64::sve2::generated | svldnt1uh_gather_u64base_index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 436 | core::core_arch::aarch64::sve2::generated | svldnt1uh_gather_u64base_index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 437 | core::core_arch::aarch64::sve2::generated | svldnt1uh_gather_u64base_offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 438 | core::core_arch::aarch64::sve2::generated | svldnt1uh_gather_u64base_offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 439 | core::core_arch::aarch64::sve2::generated | svldnt1uh_gather_u64base_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 440 | core::core_arch::aarch64::sve2::generated | svldnt1uh_gather_u64base_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 441 | core::core_arch::aarch64::sve2::generated | svldnt1uh_gather_u64index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 442 | core::core_arch::aarch64::sve2::generated | svldnt1uh_gather_u64index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 443 | core::core_arch::aarch64::sve2::generated | svldnt1uh_gather_u64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 444 | core::core_arch::aarch64::sve2::generated | svldnt1uh_gather_u64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 445 | core::core_arch::aarch64::sve2::generated | svldnt1uw_gather_s64index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 446 | core::core_arch::aarch64::sve2::generated | svldnt1uw_gather_s64index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 447 | core::core_arch::aarch64::sve2::generated | svldnt1uw_gather_s64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 448 | core::core_arch::aarch64::sve2::generated | svldnt1uw_gather_s64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 449 | core::core_arch::aarch64::sve2::generated | svldnt1uw_gather_u64base_index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 450 | core::core_arch::aarch64::sve2::generated | svldnt1uw_gather_u64base_index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 451 | core::core_arch::aarch64::sve2::generated | svldnt1uw_gather_u64base_offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 452 | core::core_arch::aarch64::sve2::generated | svldnt1uw_gather_u64base_offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 453 | core::core_arch::aarch64::sve2::generated | svldnt1uw_gather_u64base_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 454 | core::core_arch::aarch64::sve2::generated | svldnt1uw_gather_u64base_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 455 | core::core_arch::aarch64::sve2::generated | svldnt1uw_gather_u64index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 456 | core::core_arch::aarch64::sve2::generated | svldnt1uw_gather_u64index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 457 | core::core_arch::aarch64::sve2::generated | svldnt1uw_gather_u64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 458 | core::core_arch::aarch64::sve2::generated | svldnt1uw_gather_u64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 459 | core::core_arch::aarch64::sve2::generated | svstnt1_scatter_s64index_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 460 | core::core_arch::aarch64::sve2::generated | svstnt1_scatter_s64index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 461 | core::core_arch::aarch64::sve2::generated | svstnt1_scatter_s64index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 462 | core::core_arch::aarch64::sve2::generated | svstnt1_scatter_s64offset_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 463 | core::core_arch::aarch64::sve2::generated | svstnt1_scatter_s64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 464 | core::core_arch::aarch64::sve2::generated | svstnt1_scatter_s64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 465 | core::core_arch::aarch64::sve2::generated | svstnt1_scatter_u32base_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 466 | core::core_arch::aarch64::sve2::generated | svstnt1_scatter_u32base_index_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 467 | core::core_arch::aarch64::sve2::generated | svstnt1_scatter_u32base_index_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 468 | core::core_arch::aarch64::sve2::generated | svstnt1_scatter_u32base_index_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 469 | core::core_arch::aarch64::sve2::generated | svstnt1_scatter_u32base_offset_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 470 | core::core_arch::aarch64::sve2::generated | svstnt1_scatter_u32base_offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 471 | core::core_arch::aarch64::sve2::generated | svstnt1_scatter_u32base_offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 472 | core::core_arch::aarch64::sve2::generated | svstnt1_scatter_u32base_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 473 | core::core_arch::aarch64::sve2::generated | svstnt1_scatter_u32base_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 474 | core::core_arch::aarch64::sve2::generated | svstnt1_scatter_u32offset_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 475 | core::core_arch::aarch64::sve2::generated | svstnt1_scatter_u32offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 476 | core::core_arch::aarch64::sve2::generated | svstnt1_scatter_u32offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 477 | core::core_arch::aarch64::sve2::generated | svstnt1_scatter_u64base_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 478 | core::core_arch::aarch64::sve2::generated | svstnt1_scatter_u64base_index_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 479 | core::core_arch::aarch64::sve2::generated | svstnt1_scatter_u64base_index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 480 | core::core_arch::aarch64::sve2::generated | svstnt1_scatter_u64base_index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 481 | core::core_arch::aarch64::sve2::generated | svstnt1_scatter_u64base_offset_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 482 | core::core_arch::aarch64::sve2::generated | svstnt1_scatter_u64base_offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 483 | core::core_arch::aarch64::sve2::generated | svstnt1_scatter_u64base_offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 484 | core::core_arch::aarch64::sve2::generated | svstnt1_scatter_u64base_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 485 | core::core_arch::aarch64::sve2::generated | svstnt1_scatter_u64base_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 486 | core::core_arch::aarch64::sve2::generated | svstnt1_scatter_u64index_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 487 | core::core_arch::aarch64::sve2::generated | svstnt1_scatter_u64index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 488 | core::core_arch::aarch64::sve2::generated | svstnt1_scatter_u64index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 489 | core::core_arch::aarch64::sve2::generated | svstnt1_scatter_u64offset_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 490 | core::core_arch::aarch64::sve2::generated | svstnt1_scatter_u64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 491 | core::core_arch::aarch64::sve2::generated | svstnt1_scatter_u64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 492 | core::core_arch::aarch64::sve2::generated | svstnt1b_scatter_s64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 493 | core::core_arch::aarch64::sve2::generated | svstnt1b_scatter_s64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 494 | core::core_arch::aarch64::sve2::generated | svstnt1b_scatter_u32base_offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 495 | core::core_arch::aarch64::sve2::generated | svstnt1b_scatter_u32base_offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 496 | core::core_arch::aarch64::sve2::generated | svstnt1b_scatter_u32base_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 497 | core::core_arch::aarch64::sve2::generated | svstnt1b_scatter_u32base_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 498 | core::core_arch::aarch64::sve2::generated | svstnt1b_scatter_u32offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 499 | core::core_arch::aarch64::sve2::generated | svstnt1b_scatter_u32offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 500 | core::core_arch::aarch64::sve2::generated | svstnt1b_scatter_u64base_offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 501 | core::core_arch::aarch64::sve2::generated | svstnt1b_scatter_u64base_offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 502 | core::core_arch::aarch64::sve2::generated | svstnt1b_scatter_u64base_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 503 | core::core_arch::aarch64::sve2::generated | svstnt1b_scatter_u64base_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 504 | core::core_arch::aarch64::sve2::generated | svstnt1b_scatter_u64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 505 | core::core_arch::aarch64::sve2::generated | svstnt1b_scatter_u64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 506 | core::core_arch::aarch64::sve2::generated | svstnt1h_scatter_s64index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 507 | core::core_arch::aarch64::sve2::generated | svstnt1h_scatter_s64index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 508 | core::core_arch::aarch64::sve2::generated | svstnt1h_scatter_s64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 509 | core::core_arch::aarch64::sve2::generated | svstnt1h_scatter_s64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 510 | core::core_arch::aarch64::sve2::generated | svstnt1h_scatter_u32base_index_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 511 | core::core_arch::aarch64::sve2::generated | svstnt1h_scatter_u32base_index_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 512 | core::core_arch::aarch64::sve2::generated | svstnt1h_scatter_u32base_offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 513 | core::core_arch::aarch64::sve2::generated | svstnt1h_scatter_u32base_offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 514 | core::core_arch::aarch64::sve2::generated | svstnt1h_scatter_u32base_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 515 | core::core_arch::aarch64::sve2::generated | svstnt1h_scatter_u32base_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 516 | core::core_arch::aarch64::sve2::generated | svstnt1h_scatter_u32offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 517 | core::core_arch::aarch64::sve2::generated | svstnt1h_scatter_u32offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 518 | core::core_arch::aarch64::sve2::generated | svstnt1h_scatter_u64base_index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 519 | core::core_arch::aarch64::sve2::generated | svstnt1h_scatter_u64base_index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 520 | core::core_arch::aarch64::sve2::generated | svstnt1h_scatter_u64base_offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 521 | core::core_arch::aarch64::sve2::generated | svstnt1h_scatter_u64base_offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 522 | core::core_arch::aarch64::sve2::generated | svstnt1h_scatter_u64base_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 523 | core::core_arch::aarch64::sve2::generated | svstnt1h_scatter_u64base_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 524 | core::core_arch::aarch64::sve2::generated | svstnt1h_scatter_u64index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 525 | core::core_arch::aarch64::sve2::generated | svstnt1h_scatter_u64index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 526 | core::core_arch::aarch64::sve2::generated | svstnt1h_scatter_u64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 527 | core::core_arch::aarch64::sve2::generated | svstnt1h_scatter_u64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 528 | core::core_arch::aarch64::sve2::generated | svstnt1w_scatter_s64index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 529 | core::core_arch::aarch64::sve2::generated | svstnt1w_scatter_s64index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 530 | core::core_arch::aarch64::sve2::generated | svstnt1w_scatter_s64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 531 | core::core_arch::aarch64::sve2::generated | svstnt1w_scatter_s64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 532 | core::core_arch::aarch64::sve2::generated | svstnt1w_scatter_u64base_index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 533 | core::core_arch::aarch64::sve2::generated | svstnt1w_scatter_u64base_index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 534 | core::core_arch::aarch64::sve2::generated | svstnt1w_scatter_u64base_offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 535 | core::core_arch::aarch64::sve2::generated | svstnt1w_scatter_u64base_offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 536 | core::core_arch::aarch64::sve2::generated | svstnt1w_scatter_u64base_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 537 | core::core_arch::aarch64::sve2::generated | svstnt1w_scatter_u64base_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 538 | core::core_arch::aarch64::sve2::generated | svstnt1w_scatter_u64index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 539 | core::core_arch::aarch64::sve2::generated | svstnt1w_scatter_u64index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 540 | core::core_arch::aarch64::sve2::generated | svstnt1w_scatter_u64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 541 | core::core_arch::aarch64::sve2::generated | svstnt1w_scatter_u64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 542 | core::core_arch::aarch64::sve2::generated | svwhilerw_f32 | function | * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`. | |
| 543 | core::core_arch::aarch64::sve2::generated | svwhilerw_f64 | function | * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`. | |
| 544 | core::core_arch::aarch64::sve2::generated | svwhilerw_s16 | function | * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`. | |
| 545 | core::core_arch::aarch64::sve2::generated | svwhilerw_s32 | function | * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`. | |
| 546 | core::core_arch::aarch64::sve2::generated | svwhilerw_s64 | function | * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`. | |
| 547 | core::core_arch::aarch64::sve2::generated | svwhilerw_s8 | function | * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`. | |
| 548 | core::core_arch::aarch64::sve2::generated | svwhilerw_u16 | function | * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`. | |
| 549 | core::core_arch::aarch64::sve2::generated | svwhilerw_u32 | function | * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`. | |
| 550 | core::core_arch::aarch64::sve2::generated | svwhilerw_u64 | function | * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`. | |
| 551 | core::core_arch::aarch64::sve2::generated | svwhilerw_u8 | function | * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`. | |
| 552 | core::core_arch::aarch64::sve2::generated | svwhilewr_f32 | function | * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`. | |
| 553 | core::core_arch::aarch64::sve2::generated | svwhilewr_f64 | function | * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`. | |
| 554 | core::core_arch::aarch64::sve2::generated | svwhilewr_s16 | function | * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`. | |
| 555 | core::core_arch::aarch64::sve2::generated | svwhilewr_s32 | function | * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`. | |
| 556 | core::core_arch::aarch64::sve2::generated | svwhilewr_s64 | function | * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`. | |
| 557 | core::core_arch::aarch64::sve2::generated | svwhilewr_s8 | function | * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`. | |
| 558 | core::core_arch::aarch64::sve2::generated | svwhilewr_u16 | function | * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`. | |
| 559 | core::core_arch::aarch64::sve2::generated | svwhilewr_u32 | function | * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`. | |
| 560 | core::core_arch::aarch64::sve2::generated | svwhilewr_u64 | function | * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`. | |
| 561 | core::core_arch::aarch64::sve2::generated | svwhilewr_u8 | function | * [`pointer::byte_offset_from`](pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, `op1` and `op2`. | |
| 562 | core::core_arch::aarch64::sve::generated | svld1_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 563 | core::core_arch::aarch64::sve::generated | svld1_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 564 | core::core_arch::aarch64::sve::generated | svld1_gather_s32index_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 565 | core::core_arch::aarch64::sve::generated | svld1_gather_s32index_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 566 | core::core_arch::aarch64::sve::generated | svld1_gather_s32index_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 567 | core::core_arch::aarch64::sve::generated | svld1_gather_s32offset_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 568 | core::core_arch::aarch64::sve::generated | svld1_gather_s32offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 569 | core::core_arch::aarch64::sve::generated | svld1_gather_s32offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 570 | core::core_arch::aarch64::sve::generated | svld1_gather_s64index_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 571 | core::core_arch::aarch64::sve::generated | svld1_gather_s64index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 572 | core::core_arch::aarch64::sve::generated | svld1_gather_s64index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 573 | core::core_arch::aarch64::sve::generated | svld1_gather_s64offset_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 574 | core::core_arch::aarch64::sve::generated | svld1_gather_s64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 575 | core::core_arch::aarch64::sve::generated | svld1_gather_s64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 576 | core::core_arch::aarch64::sve::generated | svld1_gather_u32base_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 577 | core::core_arch::aarch64::sve::generated | svld1_gather_u32base_index_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 578 | core::core_arch::aarch64::sve::generated | svld1_gather_u32base_index_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 579 | core::core_arch::aarch64::sve::generated | svld1_gather_u32base_index_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 580 | core::core_arch::aarch64::sve::generated | svld1_gather_u32base_offset_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 581 | core::core_arch::aarch64::sve::generated | svld1_gather_u32base_offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 582 | core::core_arch::aarch64::sve::generated | svld1_gather_u32base_offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 583 | core::core_arch::aarch64::sve::generated | svld1_gather_u32base_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 584 | core::core_arch::aarch64::sve::generated | svld1_gather_u32base_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 585 | core::core_arch::aarch64::sve::generated | svld1_gather_u32index_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 586 | core::core_arch::aarch64::sve::generated | svld1_gather_u32index_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 587 | core::core_arch::aarch64::sve::generated | svld1_gather_u32index_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 588 | core::core_arch::aarch64::sve::generated | svld1_gather_u32offset_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 589 | core::core_arch::aarch64::sve::generated | svld1_gather_u32offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 590 | core::core_arch::aarch64::sve::generated | svld1_gather_u32offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 591 | core::core_arch::aarch64::sve::generated | svld1_gather_u64base_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 592 | core::core_arch::aarch64::sve::generated | svld1_gather_u64base_index_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 593 | core::core_arch::aarch64::sve::generated | svld1_gather_u64base_index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 594 | core::core_arch::aarch64::sve::generated | svld1_gather_u64base_index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 595 | core::core_arch::aarch64::sve::generated | svld1_gather_u64base_offset_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 596 | core::core_arch::aarch64::sve::generated | svld1_gather_u64base_offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 597 | core::core_arch::aarch64::sve::generated | svld1_gather_u64base_offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 598 | core::core_arch::aarch64::sve::generated | svld1_gather_u64base_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 599 | core::core_arch::aarch64::sve::generated | svld1_gather_u64base_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 600 | core::core_arch::aarch64::sve::generated | svld1_gather_u64index_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 601 | core::core_arch::aarch64::sve::generated | svld1_gather_u64index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 602 | core::core_arch::aarch64::sve::generated | svld1_gather_u64index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 603 | core::core_arch::aarch64::sve::generated | svld1_gather_u64offset_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 604 | core::core_arch::aarch64::sve::generated | svld1_gather_u64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 605 | core::core_arch::aarch64::sve::generated | svld1_gather_u64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 606 | core::core_arch::aarch64::sve::generated | svld1_s16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 607 | core::core_arch::aarch64::sve::generated | svld1_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 608 | core::core_arch::aarch64::sve::generated | svld1_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 609 | core::core_arch::aarch64::sve::generated | svld1_s8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 610 | core::core_arch::aarch64::sve::generated | svld1_u16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 611 | core::core_arch::aarch64::sve::generated | svld1_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 612 | core::core_arch::aarch64::sve::generated | svld1_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 613 | core::core_arch::aarch64::sve::generated | svld1_u8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 614 | core::core_arch::aarch64::sve::generated | svld1_vnum_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 615 | core::core_arch::aarch64::sve::generated | svld1_vnum_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 616 | core::core_arch::aarch64::sve::generated | svld1_vnum_s16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 617 | core::core_arch::aarch64::sve::generated | svld1_vnum_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 618 | core::core_arch::aarch64::sve::generated | svld1_vnum_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 619 | core::core_arch::aarch64::sve::generated | svld1_vnum_s8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 620 | core::core_arch::aarch64::sve::generated | svld1_vnum_u16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 621 | core::core_arch::aarch64::sve::generated | svld1_vnum_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 622 | core::core_arch::aarch64::sve::generated | svld1_vnum_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 623 | core::core_arch::aarch64::sve::generated | svld1_vnum_u8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 624 | core::core_arch::aarch64::sve::generated | svld1ro_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 625 | core::core_arch::aarch64::sve::generated | svld1ro_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 626 | core::core_arch::aarch64::sve::generated | svld1ro_s16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 627 | core::core_arch::aarch64::sve::generated | svld1ro_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 628 | core::core_arch::aarch64::sve::generated | svld1ro_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 629 | core::core_arch::aarch64::sve::generated | svld1ro_s8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 630 | core::core_arch::aarch64::sve::generated | svld1ro_u16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 631 | core::core_arch::aarch64::sve::generated | svld1ro_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 632 | core::core_arch::aarch64::sve::generated | svld1ro_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 633 | core::core_arch::aarch64::sve::generated | svld1ro_u8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 634 | core::core_arch::aarch64::sve::generated | svld1rq_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 635 | core::core_arch::aarch64::sve::generated | svld1rq_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 636 | core::core_arch::aarch64::sve::generated | svld1rq_s16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 637 | core::core_arch::aarch64::sve::generated | svld1rq_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 638 | core::core_arch::aarch64::sve::generated | svld1rq_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 639 | core::core_arch::aarch64::sve::generated | svld1rq_s8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 640 | core::core_arch::aarch64::sve::generated | svld1rq_u16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 641 | core::core_arch::aarch64::sve::generated | svld1rq_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 642 | core::core_arch::aarch64::sve::generated | svld1rq_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 643 | core::core_arch::aarch64::sve::generated | svld1rq_u8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 644 | core::core_arch::aarch64::sve::generated | svld1sb_gather_s32offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 645 | core::core_arch::aarch64::sve::generated | svld1sb_gather_s32offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 646 | core::core_arch::aarch64::sve::generated | svld1sb_gather_s64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 647 | core::core_arch::aarch64::sve::generated | svld1sb_gather_s64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 648 | core::core_arch::aarch64::sve::generated | svld1sb_gather_u32base_offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 649 | core::core_arch::aarch64::sve::generated | svld1sb_gather_u32base_offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 650 | core::core_arch::aarch64::sve::generated | svld1sb_gather_u32base_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 651 | core::core_arch::aarch64::sve::generated | svld1sb_gather_u32base_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 652 | core::core_arch::aarch64::sve::generated | svld1sb_gather_u32offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 653 | core::core_arch::aarch64::sve::generated | svld1sb_gather_u32offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 654 | core::core_arch::aarch64::sve::generated | svld1sb_gather_u64base_offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 655 | core::core_arch::aarch64::sve::generated | svld1sb_gather_u64base_offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 656 | core::core_arch::aarch64::sve::generated | svld1sb_gather_u64base_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 657 | core::core_arch::aarch64::sve::generated | svld1sb_gather_u64base_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 658 | core::core_arch::aarch64::sve::generated | svld1sb_gather_u64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 659 | core::core_arch::aarch64::sve::generated | svld1sb_gather_u64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 660 | core::core_arch::aarch64::sve::generated | svld1sb_s16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 661 | core::core_arch::aarch64::sve::generated | svld1sb_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 662 | core::core_arch::aarch64::sve::generated | svld1sb_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 663 | core::core_arch::aarch64::sve::generated | svld1sb_u16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 664 | core::core_arch::aarch64::sve::generated | svld1sb_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 665 | core::core_arch::aarch64::sve::generated | svld1sb_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 666 | core::core_arch::aarch64::sve::generated | svld1sb_vnum_s16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 667 | core::core_arch::aarch64::sve::generated | svld1sb_vnum_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 668 | core::core_arch::aarch64::sve::generated | svld1sb_vnum_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 669 | core::core_arch::aarch64::sve::generated | svld1sb_vnum_u16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 670 | core::core_arch::aarch64::sve::generated | svld1sb_vnum_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 671 | core::core_arch::aarch64::sve::generated | svld1sb_vnum_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 672 | core::core_arch::aarch64::sve::generated | svld1sh_gather_s32index_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 673 | core::core_arch::aarch64::sve::generated | svld1sh_gather_s32index_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 674 | core::core_arch::aarch64::sve::generated | svld1sh_gather_s32offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 675 | core::core_arch::aarch64::sve::generated | svld1sh_gather_s32offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 676 | core::core_arch::aarch64::sve::generated | svld1sh_gather_s64index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 677 | core::core_arch::aarch64::sve::generated | svld1sh_gather_s64index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 678 | core::core_arch::aarch64::sve::generated | svld1sh_gather_s64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 679 | core::core_arch::aarch64::sve::generated | svld1sh_gather_s64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 680 | core::core_arch::aarch64::sve::generated | svld1sh_gather_u32base_index_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 681 | core::core_arch::aarch64::sve::generated | svld1sh_gather_u32base_index_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 682 | core::core_arch::aarch64::sve::generated | svld1sh_gather_u32base_offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 683 | core::core_arch::aarch64::sve::generated | svld1sh_gather_u32base_offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 684 | core::core_arch::aarch64::sve::generated | svld1sh_gather_u32base_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 685 | core::core_arch::aarch64::sve::generated | svld1sh_gather_u32base_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 686 | core::core_arch::aarch64::sve::generated | svld1sh_gather_u32index_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 687 | core::core_arch::aarch64::sve::generated | svld1sh_gather_u32index_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 688 | core::core_arch::aarch64::sve::generated | svld1sh_gather_u32offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 689 | core::core_arch::aarch64::sve::generated | svld1sh_gather_u32offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 690 | core::core_arch::aarch64::sve::generated | svld1sh_gather_u64base_index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 691 | core::core_arch::aarch64::sve::generated | svld1sh_gather_u64base_index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 692 | core::core_arch::aarch64::sve::generated | svld1sh_gather_u64base_offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 693 | core::core_arch::aarch64::sve::generated | svld1sh_gather_u64base_offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 694 | core::core_arch::aarch64::sve::generated | svld1sh_gather_u64base_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 695 | core::core_arch::aarch64::sve::generated | svld1sh_gather_u64base_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 696 | core::core_arch::aarch64::sve::generated | svld1sh_gather_u64index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 697 | core::core_arch::aarch64::sve::generated | svld1sh_gather_u64index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 698 | core::core_arch::aarch64::sve::generated | svld1sh_gather_u64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 699 | core::core_arch::aarch64::sve::generated | svld1sh_gather_u64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 700 | core::core_arch::aarch64::sve::generated | svld1sh_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 701 | core::core_arch::aarch64::sve::generated | svld1sh_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 702 | core::core_arch::aarch64::sve::generated | svld1sh_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 703 | core::core_arch::aarch64::sve::generated | svld1sh_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 704 | core::core_arch::aarch64::sve::generated | svld1sh_vnum_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 705 | core::core_arch::aarch64::sve::generated | svld1sh_vnum_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 706 | core::core_arch::aarch64::sve::generated | svld1sh_vnum_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 707 | core::core_arch::aarch64::sve::generated | svld1sh_vnum_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 708 | core::core_arch::aarch64::sve::generated | svld1sw_gather_s64index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 709 | core::core_arch::aarch64::sve::generated | svld1sw_gather_s64index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 710 | core::core_arch::aarch64::sve::generated | svld1sw_gather_s64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 711 | core::core_arch::aarch64::sve::generated | svld1sw_gather_s64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 712 | core::core_arch::aarch64::sve::generated | svld1sw_gather_u64base_index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 713 | core::core_arch::aarch64::sve::generated | svld1sw_gather_u64base_index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 714 | core::core_arch::aarch64::sve::generated | svld1sw_gather_u64base_offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 715 | core::core_arch::aarch64::sve::generated | svld1sw_gather_u64base_offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 716 | core::core_arch::aarch64::sve::generated | svld1sw_gather_u64base_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 717 | core::core_arch::aarch64::sve::generated | svld1sw_gather_u64base_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 718 | core::core_arch::aarch64::sve::generated | svld1sw_gather_u64index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 719 | core::core_arch::aarch64::sve::generated | svld1sw_gather_u64index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 720 | core::core_arch::aarch64::sve::generated | svld1sw_gather_u64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 721 | core::core_arch::aarch64::sve::generated | svld1sw_gather_u64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 722 | core::core_arch::aarch64::sve::generated | svld1sw_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 723 | core::core_arch::aarch64::sve::generated | svld1sw_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 724 | core::core_arch::aarch64::sve::generated | svld1sw_vnum_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 725 | core::core_arch::aarch64::sve::generated | svld1sw_vnum_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 726 | core::core_arch::aarch64::sve::generated | svld1ub_gather_s32offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 727 | core::core_arch::aarch64::sve::generated | svld1ub_gather_s32offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 728 | core::core_arch::aarch64::sve::generated | svld1ub_gather_s64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 729 | core::core_arch::aarch64::sve::generated | svld1ub_gather_s64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 730 | core::core_arch::aarch64::sve::generated | svld1ub_gather_u32base_offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 731 | core::core_arch::aarch64::sve::generated | svld1ub_gather_u32base_offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 732 | core::core_arch::aarch64::sve::generated | svld1ub_gather_u32base_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 733 | core::core_arch::aarch64::sve::generated | svld1ub_gather_u32base_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 734 | core::core_arch::aarch64::sve::generated | svld1ub_gather_u32offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 735 | core::core_arch::aarch64::sve::generated | svld1ub_gather_u32offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 736 | core::core_arch::aarch64::sve::generated | svld1ub_gather_u64base_offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 737 | core::core_arch::aarch64::sve::generated | svld1ub_gather_u64base_offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 738 | core::core_arch::aarch64::sve::generated | svld1ub_gather_u64base_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 739 | core::core_arch::aarch64::sve::generated | svld1ub_gather_u64base_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 740 | core::core_arch::aarch64::sve::generated | svld1ub_gather_u64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 741 | core::core_arch::aarch64::sve::generated | svld1ub_gather_u64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 742 | core::core_arch::aarch64::sve::generated | svld1ub_s16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 743 | core::core_arch::aarch64::sve::generated | svld1ub_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 744 | core::core_arch::aarch64::sve::generated | svld1ub_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 745 | core::core_arch::aarch64::sve::generated | svld1ub_u16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 746 | core::core_arch::aarch64::sve::generated | svld1ub_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 747 | core::core_arch::aarch64::sve::generated | svld1ub_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 748 | core::core_arch::aarch64::sve::generated | svld1ub_vnum_s16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 749 | core::core_arch::aarch64::sve::generated | svld1ub_vnum_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 750 | core::core_arch::aarch64::sve::generated | svld1ub_vnum_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 751 | core::core_arch::aarch64::sve::generated | svld1ub_vnum_u16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 752 | core::core_arch::aarch64::sve::generated | svld1ub_vnum_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 753 | core::core_arch::aarch64::sve::generated | svld1ub_vnum_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 754 | core::core_arch::aarch64::sve::generated | svld1uh_gather_s32index_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 755 | core::core_arch::aarch64::sve::generated | svld1uh_gather_s32index_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 756 | core::core_arch::aarch64::sve::generated | svld1uh_gather_s32offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 757 | core::core_arch::aarch64::sve::generated | svld1uh_gather_s32offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 758 | core::core_arch::aarch64::sve::generated | svld1uh_gather_s64index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 759 | core::core_arch::aarch64::sve::generated | svld1uh_gather_s64index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 760 | core::core_arch::aarch64::sve::generated | svld1uh_gather_s64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 761 | core::core_arch::aarch64::sve::generated | svld1uh_gather_s64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 762 | core::core_arch::aarch64::sve::generated | svld1uh_gather_u32base_index_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 763 | core::core_arch::aarch64::sve::generated | svld1uh_gather_u32base_index_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 764 | core::core_arch::aarch64::sve::generated | svld1uh_gather_u32base_offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 765 | core::core_arch::aarch64::sve::generated | svld1uh_gather_u32base_offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 766 | core::core_arch::aarch64::sve::generated | svld1uh_gather_u32base_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 767 | core::core_arch::aarch64::sve::generated | svld1uh_gather_u32base_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 768 | core::core_arch::aarch64::sve::generated | svld1uh_gather_u32index_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 769 | core::core_arch::aarch64::sve::generated | svld1uh_gather_u32index_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 770 | core::core_arch::aarch64::sve::generated | svld1uh_gather_u32offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 771 | core::core_arch::aarch64::sve::generated | svld1uh_gather_u32offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 772 | core::core_arch::aarch64::sve::generated | svld1uh_gather_u64base_index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 773 | core::core_arch::aarch64::sve::generated | svld1uh_gather_u64base_index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 774 | core::core_arch::aarch64::sve::generated | svld1uh_gather_u64base_offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 775 | core::core_arch::aarch64::sve::generated | svld1uh_gather_u64base_offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 776 | core::core_arch::aarch64::sve::generated | svld1uh_gather_u64base_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 777 | core::core_arch::aarch64::sve::generated | svld1uh_gather_u64base_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 778 | core::core_arch::aarch64::sve::generated | svld1uh_gather_u64index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 779 | core::core_arch::aarch64::sve::generated | svld1uh_gather_u64index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 780 | core::core_arch::aarch64::sve::generated | svld1uh_gather_u64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 781 | core::core_arch::aarch64::sve::generated | svld1uh_gather_u64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 782 | core::core_arch::aarch64::sve::generated | svld1uh_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 783 | core::core_arch::aarch64::sve::generated | svld1uh_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 784 | core::core_arch::aarch64::sve::generated | svld1uh_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 785 | core::core_arch::aarch64::sve::generated | svld1uh_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 786 | core::core_arch::aarch64::sve::generated | svld1uh_vnum_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 787 | core::core_arch::aarch64::sve::generated | svld1uh_vnum_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 788 | core::core_arch::aarch64::sve::generated | svld1uh_vnum_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 789 | core::core_arch::aarch64::sve::generated | svld1uh_vnum_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 790 | core::core_arch::aarch64::sve::generated | svld1uw_gather_s64index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 791 | core::core_arch::aarch64::sve::generated | svld1uw_gather_s64index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 792 | core::core_arch::aarch64::sve::generated | svld1uw_gather_s64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 793 | core::core_arch::aarch64::sve::generated | svld1uw_gather_s64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 794 | core::core_arch::aarch64::sve::generated | svld1uw_gather_u64base_index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 795 | core::core_arch::aarch64::sve::generated | svld1uw_gather_u64base_index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 796 | core::core_arch::aarch64::sve::generated | svld1uw_gather_u64base_offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 797 | core::core_arch::aarch64::sve::generated | svld1uw_gather_u64base_offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 798 | core::core_arch::aarch64::sve::generated | svld1uw_gather_u64base_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 799 | core::core_arch::aarch64::sve::generated | svld1uw_gather_u64base_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 800 | core::core_arch::aarch64::sve::generated | svld1uw_gather_u64index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 801 | core::core_arch::aarch64::sve::generated | svld1uw_gather_u64index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 802 | core::core_arch::aarch64::sve::generated | svld1uw_gather_u64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 803 | core::core_arch::aarch64::sve::generated | svld1uw_gather_u64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 804 | core::core_arch::aarch64::sve::generated | svld1uw_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 805 | core::core_arch::aarch64::sve::generated | svld1uw_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 806 | core::core_arch::aarch64::sve::generated | svld1uw_vnum_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 807 | core::core_arch::aarch64::sve::generated | svld1uw_vnum_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 808 | core::core_arch::aarch64::sve::generated | svld2_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 809 | core::core_arch::aarch64::sve::generated | svld2_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 810 | core::core_arch::aarch64::sve::generated | svld2_s16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 811 | core::core_arch::aarch64::sve::generated | svld2_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 812 | core::core_arch::aarch64::sve::generated | svld2_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 813 | core::core_arch::aarch64::sve::generated | svld2_s8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 814 | core::core_arch::aarch64::sve::generated | svld2_u16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 815 | core::core_arch::aarch64::sve::generated | svld2_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 816 | core::core_arch::aarch64::sve::generated | svld2_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 817 | core::core_arch::aarch64::sve::generated | svld2_u8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 818 | core::core_arch::aarch64::sve::generated | svld2_vnum_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 819 | core::core_arch::aarch64::sve::generated | svld2_vnum_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 820 | core::core_arch::aarch64::sve::generated | svld2_vnum_s16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 821 | core::core_arch::aarch64::sve::generated | svld2_vnum_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 822 | core::core_arch::aarch64::sve::generated | svld2_vnum_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 823 | core::core_arch::aarch64::sve::generated | svld2_vnum_s8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 824 | core::core_arch::aarch64::sve::generated | svld2_vnum_u16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 825 | core::core_arch::aarch64::sve::generated | svld2_vnum_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 826 | core::core_arch::aarch64::sve::generated | svld2_vnum_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 827 | core::core_arch::aarch64::sve::generated | svld2_vnum_u8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 828 | core::core_arch::aarch64::sve::generated | svld3_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 829 | core::core_arch::aarch64::sve::generated | svld3_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 830 | core::core_arch::aarch64::sve::generated | svld3_s16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 831 | core::core_arch::aarch64::sve::generated | svld3_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 832 | core::core_arch::aarch64::sve::generated | svld3_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 833 | core::core_arch::aarch64::sve::generated | svld3_s8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 834 | core::core_arch::aarch64::sve::generated | svld3_u16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 835 | core::core_arch::aarch64::sve::generated | svld3_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 836 | core::core_arch::aarch64::sve::generated | svld3_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 837 | core::core_arch::aarch64::sve::generated | svld3_u8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 838 | core::core_arch::aarch64::sve::generated | svld3_vnum_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 839 | core::core_arch::aarch64::sve::generated | svld3_vnum_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 840 | core::core_arch::aarch64::sve::generated | svld3_vnum_s16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 841 | core::core_arch::aarch64::sve::generated | svld3_vnum_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 842 | core::core_arch::aarch64::sve::generated | svld3_vnum_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 843 | core::core_arch::aarch64::sve::generated | svld3_vnum_s8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 844 | core::core_arch::aarch64::sve::generated | svld3_vnum_u16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 845 | core::core_arch::aarch64::sve::generated | svld3_vnum_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 846 | core::core_arch::aarch64::sve::generated | svld3_vnum_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 847 | core::core_arch::aarch64::sve::generated | svld3_vnum_u8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 848 | core::core_arch::aarch64::sve::generated | svld4_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 849 | core::core_arch::aarch64::sve::generated | svld4_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 850 | core::core_arch::aarch64::sve::generated | svld4_s16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 851 | core::core_arch::aarch64::sve::generated | svld4_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 852 | core::core_arch::aarch64::sve::generated | svld4_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 853 | core::core_arch::aarch64::sve::generated | svld4_s8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 854 | core::core_arch::aarch64::sve::generated | svld4_u16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 855 | core::core_arch::aarch64::sve::generated | svld4_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 856 | core::core_arch::aarch64::sve::generated | svld4_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 857 | core::core_arch::aarch64::sve::generated | svld4_u8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 858 | core::core_arch::aarch64::sve::generated | svld4_vnum_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 859 | core::core_arch::aarch64::sve::generated | svld4_vnum_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 860 | core::core_arch::aarch64::sve::generated | svld4_vnum_s16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 861 | core::core_arch::aarch64::sve::generated | svld4_vnum_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 862 | core::core_arch::aarch64::sve::generated | svld4_vnum_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 863 | core::core_arch::aarch64::sve::generated | svld4_vnum_s8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 864 | core::core_arch::aarch64::sve::generated | svld4_vnum_u16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 865 | core::core_arch::aarch64::sve::generated | svld4_vnum_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 866 | core::core_arch::aarch64::sve::generated | svld4_vnum_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 867 | core::core_arch::aarch64::sve::generated | svld4_vnum_u8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 868 | core::core_arch::aarch64::sve::generated | svldff1_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 869 | core::core_arch::aarch64::sve::generated | svldff1_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 870 | core::core_arch::aarch64::sve::generated | svldff1_gather_s32index_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 871 | core::core_arch::aarch64::sve::generated | svldff1_gather_s32index_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 872 | core::core_arch::aarch64::sve::generated | svldff1_gather_s32index_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 873 | core::core_arch::aarch64::sve::generated | svldff1_gather_s32offset_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 874 | core::core_arch::aarch64::sve::generated | svldff1_gather_s32offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 875 | core::core_arch::aarch64::sve::generated | svldff1_gather_s32offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 876 | core::core_arch::aarch64::sve::generated | svldff1_gather_s64index_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 877 | core::core_arch::aarch64::sve::generated | svldff1_gather_s64index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 878 | core::core_arch::aarch64::sve::generated | svldff1_gather_s64index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 879 | core::core_arch::aarch64::sve::generated | svldff1_gather_s64offset_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 880 | core::core_arch::aarch64::sve::generated | svldff1_gather_s64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 881 | core::core_arch::aarch64::sve::generated | svldff1_gather_s64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 882 | core::core_arch::aarch64::sve::generated | svldff1_gather_u32base_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 883 | core::core_arch::aarch64::sve::generated | svldff1_gather_u32base_index_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 884 | core::core_arch::aarch64::sve::generated | svldff1_gather_u32base_index_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 885 | core::core_arch::aarch64::sve::generated | svldff1_gather_u32base_index_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 886 | core::core_arch::aarch64::sve::generated | svldff1_gather_u32base_offset_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 887 | core::core_arch::aarch64::sve::generated | svldff1_gather_u32base_offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 888 | core::core_arch::aarch64::sve::generated | svldff1_gather_u32base_offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 889 | core::core_arch::aarch64::sve::generated | svldff1_gather_u32base_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 890 | core::core_arch::aarch64::sve::generated | svldff1_gather_u32base_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 891 | core::core_arch::aarch64::sve::generated | svldff1_gather_u32index_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 892 | core::core_arch::aarch64::sve::generated | svldff1_gather_u32index_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 893 | core::core_arch::aarch64::sve::generated | svldff1_gather_u32index_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 894 | core::core_arch::aarch64::sve::generated | svldff1_gather_u32offset_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 895 | core::core_arch::aarch64::sve::generated | svldff1_gather_u32offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 896 | core::core_arch::aarch64::sve::generated | svldff1_gather_u32offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 897 | core::core_arch::aarch64::sve::generated | svldff1_gather_u64base_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 898 | core::core_arch::aarch64::sve::generated | svldff1_gather_u64base_index_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 899 | core::core_arch::aarch64::sve::generated | svldff1_gather_u64base_index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 900 | core::core_arch::aarch64::sve::generated | svldff1_gather_u64base_index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 901 | core::core_arch::aarch64::sve::generated | svldff1_gather_u64base_offset_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 902 | core::core_arch::aarch64::sve::generated | svldff1_gather_u64base_offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 903 | core::core_arch::aarch64::sve::generated | svldff1_gather_u64base_offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 904 | core::core_arch::aarch64::sve::generated | svldff1_gather_u64base_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 905 | core::core_arch::aarch64::sve::generated | svldff1_gather_u64base_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 906 | core::core_arch::aarch64::sve::generated | svldff1_gather_u64index_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 907 | core::core_arch::aarch64::sve::generated | svldff1_gather_u64index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 908 | core::core_arch::aarch64::sve::generated | svldff1_gather_u64index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 909 | core::core_arch::aarch64::sve::generated | svldff1_gather_u64offset_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 910 | core::core_arch::aarch64::sve::generated | svldff1_gather_u64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 911 | core::core_arch::aarch64::sve::generated | svldff1_gather_u64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 912 | core::core_arch::aarch64::sve::generated | svldff1_s16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 913 | core::core_arch::aarch64::sve::generated | svldff1_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 914 | core::core_arch::aarch64::sve::generated | svldff1_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 915 | core::core_arch::aarch64::sve::generated | svldff1_s8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 916 | core::core_arch::aarch64::sve::generated | svldff1_u16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 917 | core::core_arch::aarch64::sve::generated | svldff1_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 918 | core::core_arch::aarch64::sve::generated | svldff1_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 919 | core::core_arch::aarch64::sve::generated | svldff1_u8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 920 | core::core_arch::aarch64::sve::generated | svldff1_vnum_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 921 | core::core_arch::aarch64::sve::generated | svldff1_vnum_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 922 | core::core_arch::aarch64::sve::generated | svldff1_vnum_s16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 923 | core::core_arch::aarch64::sve::generated | svldff1_vnum_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 924 | core::core_arch::aarch64::sve::generated | svldff1_vnum_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 925 | core::core_arch::aarch64::sve::generated | svldff1_vnum_s8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 926 | core::core_arch::aarch64::sve::generated | svldff1_vnum_u16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 927 | core::core_arch::aarch64::sve::generated | svldff1_vnum_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 928 | core::core_arch::aarch64::sve::generated | svldff1_vnum_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 929 | core::core_arch::aarch64::sve::generated | svldff1_vnum_u8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 930 | core::core_arch::aarch64::sve::generated | svldff1sb_gather_s32offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 931 | core::core_arch::aarch64::sve::generated | svldff1sb_gather_s32offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 932 | core::core_arch::aarch64::sve::generated | svldff1sb_gather_s64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 933 | core::core_arch::aarch64::sve::generated | svldff1sb_gather_s64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 934 | core::core_arch::aarch64::sve::generated | svldff1sb_gather_u32base_offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 935 | core::core_arch::aarch64::sve::generated | svldff1sb_gather_u32base_offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 936 | core::core_arch::aarch64::sve::generated | svldff1sb_gather_u32base_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 937 | core::core_arch::aarch64::sve::generated | svldff1sb_gather_u32base_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 938 | core::core_arch::aarch64::sve::generated | svldff1sb_gather_u32offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 939 | core::core_arch::aarch64::sve::generated | svldff1sb_gather_u32offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 940 | core::core_arch::aarch64::sve::generated | svldff1sb_gather_u64base_offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 941 | core::core_arch::aarch64::sve::generated | svldff1sb_gather_u64base_offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 942 | core::core_arch::aarch64::sve::generated | svldff1sb_gather_u64base_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 943 | core::core_arch::aarch64::sve::generated | svldff1sb_gather_u64base_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 944 | core::core_arch::aarch64::sve::generated | svldff1sb_gather_u64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 945 | core::core_arch::aarch64::sve::generated | svldff1sb_gather_u64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 946 | core::core_arch::aarch64::sve::generated | svldff1sb_s16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 947 | core::core_arch::aarch64::sve::generated | svldff1sb_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 948 | core::core_arch::aarch64::sve::generated | svldff1sb_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 949 | core::core_arch::aarch64::sve::generated | svldff1sb_u16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 950 | core::core_arch::aarch64::sve::generated | svldff1sb_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 951 | core::core_arch::aarch64::sve::generated | svldff1sb_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 952 | core::core_arch::aarch64::sve::generated | svldff1sb_vnum_s16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 953 | core::core_arch::aarch64::sve::generated | svldff1sb_vnum_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 954 | core::core_arch::aarch64::sve::generated | svldff1sb_vnum_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 955 | core::core_arch::aarch64::sve::generated | svldff1sb_vnum_u16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 956 | core::core_arch::aarch64::sve::generated | svldff1sb_vnum_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 957 | core::core_arch::aarch64::sve::generated | svldff1sb_vnum_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 958 | core::core_arch::aarch64::sve::generated | svldff1sh_gather_s32index_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 959 | core::core_arch::aarch64::sve::generated | svldff1sh_gather_s32index_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 960 | core::core_arch::aarch64::sve::generated | svldff1sh_gather_s32offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 961 | core::core_arch::aarch64::sve::generated | svldff1sh_gather_s32offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 962 | core::core_arch::aarch64::sve::generated | svldff1sh_gather_s64index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 963 | core::core_arch::aarch64::sve::generated | svldff1sh_gather_s64index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 964 | core::core_arch::aarch64::sve::generated | svldff1sh_gather_s64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 965 | core::core_arch::aarch64::sve::generated | svldff1sh_gather_s64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 966 | core::core_arch::aarch64::sve::generated | svldff1sh_gather_u32base_index_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 967 | core::core_arch::aarch64::sve::generated | svldff1sh_gather_u32base_index_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 968 | core::core_arch::aarch64::sve::generated | svldff1sh_gather_u32base_offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 969 | core::core_arch::aarch64::sve::generated | svldff1sh_gather_u32base_offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 970 | core::core_arch::aarch64::sve::generated | svldff1sh_gather_u32base_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 971 | core::core_arch::aarch64::sve::generated | svldff1sh_gather_u32base_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 972 | core::core_arch::aarch64::sve::generated | svldff1sh_gather_u32index_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 973 | core::core_arch::aarch64::sve::generated | svldff1sh_gather_u32index_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 974 | core::core_arch::aarch64::sve::generated | svldff1sh_gather_u32offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 975 | core::core_arch::aarch64::sve::generated | svldff1sh_gather_u32offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 976 | core::core_arch::aarch64::sve::generated | svldff1sh_gather_u64base_index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 977 | core::core_arch::aarch64::sve::generated | svldff1sh_gather_u64base_index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 978 | core::core_arch::aarch64::sve::generated | svldff1sh_gather_u64base_offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 979 | core::core_arch::aarch64::sve::generated | svldff1sh_gather_u64base_offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 980 | core::core_arch::aarch64::sve::generated | svldff1sh_gather_u64base_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 981 | core::core_arch::aarch64::sve::generated | svldff1sh_gather_u64base_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 982 | core::core_arch::aarch64::sve::generated | svldff1sh_gather_u64index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 983 | core::core_arch::aarch64::sve::generated | svldff1sh_gather_u64index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 984 | core::core_arch::aarch64::sve::generated | svldff1sh_gather_u64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 985 | core::core_arch::aarch64::sve::generated | svldff1sh_gather_u64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 986 | core::core_arch::aarch64::sve::generated | svldff1sh_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 987 | core::core_arch::aarch64::sve::generated | svldff1sh_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 988 | core::core_arch::aarch64::sve::generated | svldff1sh_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 989 | core::core_arch::aarch64::sve::generated | svldff1sh_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 990 | core::core_arch::aarch64::sve::generated | svldff1sh_vnum_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 991 | core::core_arch::aarch64::sve::generated | svldff1sh_vnum_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 992 | core::core_arch::aarch64::sve::generated | svldff1sh_vnum_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 993 | core::core_arch::aarch64::sve::generated | svldff1sh_vnum_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 994 | core::core_arch::aarch64::sve::generated | svldff1sw_gather_s64index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 995 | core::core_arch::aarch64::sve::generated | svldff1sw_gather_s64index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 996 | core::core_arch::aarch64::sve::generated | svldff1sw_gather_s64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 997 | core::core_arch::aarch64::sve::generated | svldff1sw_gather_s64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 998 | core::core_arch::aarch64::sve::generated | svldff1sw_gather_u64base_index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 999 | core::core_arch::aarch64::sve::generated | svldff1sw_gather_u64base_index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1000 | core::core_arch::aarch64::sve::generated | svldff1sw_gather_u64base_offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1001 | core::core_arch::aarch64::sve::generated | svldff1sw_gather_u64base_offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1002 | core::core_arch::aarch64::sve::generated | svldff1sw_gather_u64base_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1003 | core::core_arch::aarch64::sve::generated | svldff1sw_gather_u64base_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1004 | core::core_arch::aarch64::sve::generated | svldff1sw_gather_u64index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1005 | core::core_arch::aarch64::sve::generated | svldff1sw_gather_u64index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1006 | core::core_arch::aarch64::sve::generated | svldff1sw_gather_u64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1007 | core::core_arch::aarch64::sve::generated | svldff1sw_gather_u64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1008 | core::core_arch::aarch64::sve::generated | svldff1sw_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1009 | core::core_arch::aarch64::sve::generated | svldff1sw_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1010 | core::core_arch::aarch64::sve::generated | svldff1sw_vnum_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1011 | core::core_arch::aarch64::sve::generated | svldff1sw_vnum_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1012 | core::core_arch::aarch64::sve::generated | svldff1ub_gather_s32offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1013 | core::core_arch::aarch64::sve::generated | svldff1ub_gather_s32offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1014 | core::core_arch::aarch64::sve::generated | svldff1ub_gather_s64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1015 | core::core_arch::aarch64::sve::generated | svldff1ub_gather_s64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1016 | core::core_arch::aarch64::sve::generated | svldff1ub_gather_u32base_offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1017 | core::core_arch::aarch64::sve::generated | svldff1ub_gather_u32base_offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1018 | core::core_arch::aarch64::sve::generated | svldff1ub_gather_u32base_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1019 | core::core_arch::aarch64::sve::generated | svldff1ub_gather_u32base_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1020 | core::core_arch::aarch64::sve::generated | svldff1ub_gather_u32offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1021 | core::core_arch::aarch64::sve::generated | svldff1ub_gather_u32offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1022 | core::core_arch::aarch64::sve::generated | svldff1ub_gather_u64base_offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1023 | core::core_arch::aarch64::sve::generated | svldff1ub_gather_u64base_offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1024 | core::core_arch::aarch64::sve::generated | svldff1ub_gather_u64base_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1025 | core::core_arch::aarch64::sve::generated | svldff1ub_gather_u64base_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1026 | core::core_arch::aarch64::sve::generated | svldff1ub_gather_u64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1027 | core::core_arch::aarch64::sve::generated | svldff1ub_gather_u64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1028 | core::core_arch::aarch64::sve::generated | svldff1ub_s16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1029 | core::core_arch::aarch64::sve::generated | svldff1ub_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1030 | core::core_arch::aarch64::sve::generated | svldff1ub_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1031 | core::core_arch::aarch64::sve::generated | svldff1ub_u16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1032 | core::core_arch::aarch64::sve::generated | svldff1ub_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1033 | core::core_arch::aarch64::sve::generated | svldff1ub_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1034 | core::core_arch::aarch64::sve::generated | svldff1ub_vnum_s16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1035 | core::core_arch::aarch64::sve::generated | svldff1ub_vnum_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1036 | core::core_arch::aarch64::sve::generated | svldff1ub_vnum_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1037 | core::core_arch::aarch64::sve::generated | svldff1ub_vnum_u16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1038 | core::core_arch::aarch64::sve::generated | svldff1ub_vnum_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1039 | core::core_arch::aarch64::sve::generated | svldff1ub_vnum_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1040 | core::core_arch::aarch64::sve::generated | svldff1uh_gather_s32index_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1041 | core::core_arch::aarch64::sve::generated | svldff1uh_gather_s32index_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1042 | core::core_arch::aarch64::sve::generated | svldff1uh_gather_s32offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1043 | core::core_arch::aarch64::sve::generated | svldff1uh_gather_s32offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1044 | core::core_arch::aarch64::sve::generated | svldff1uh_gather_s64index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1045 | core::core_arch::aarch64::sve::generated | svldff1uh_gather_s64index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1046 | core::core_arch::aarch64::sve::generated | svldff1uh_gather_s64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1047 | core::core_arch::aarch64::sve::generated | svldff1uh_gather_s64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1048 | core::core_arch::aarch64::sve::generated | svldff1uh_gather_u32base_index_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1049 | core::core_arch::aarch64::sve::generated | svldff1uh_gather_u32base_index_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1050 | core::core_arch::aarch64::sve::generated | svldff1uh_gather_u32base_offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1051 | core::core_arch::aarch64::sve::generated | svldff1uh_gather_u32base_offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1052 | core::core_arch::aarch64::sve::generated | svldff1uh_gather_u32base_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1053 | core::core_arch::aarch64::sve::generated | svldff1uh_gather_u32base_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1054 | core::core_arch::aarch64::sve::generated | svldff1uh_gather_u32index_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1055 | core::core_arch::aarch64::sve::generated | svldff1uh_gather_u32index_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1056 | core::core_arch::aarch64::sve::generated | svldff1uh_gather_u32offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1057 | core::core_arch::aarch64::sve::generated | svldff1uh_gather_u32offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1058 | core::core_arch::aarch64::sve::generated | svldff1uh_gather_u64base_index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1059 | core::core_arch::aarch64::sve::generated | svldff1uh_gather_u64base_index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1060 | core::core_arch::aarch64::sve::generated | svldff1uh_gather_u64base_offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1061 | core::core_arch::aarch64::sve::generated | svldff1uh_gather_u64base_offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1062 | core::core_arch::aarch64::sve::generated | svldff1uh_gather_u64base_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1063 | core::core_arch::aarch64::sve::generated | svldff1uh_gather_u64base_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1064 | core::core_arch::aarch64::sve::generated | svldff1uh_gather_u64index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1065 | core::core_arch::aarch64::sve::generated | svldff1uh_gather_u64index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1066 | core::core_arch::aarch64::sve::generated | svldff1uh_gather_u64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1067 | core::core_arch::aarch64::sve::generated | svldff1uh_gather_u64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1068 | core::core_arch::aarch64::sve::generated | svldff1uh_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1069 | core::core_arch::aarch64::sve::generated | svldff1uh_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1070 | core::core_arch::aarch64::sve::generated | svldff1uh_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1071 | core::core_arch::aarch64::sve::generated | svldff1uh_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1072 | core::core_arch::aarch64::sve::generated | svldff1uh_vnum_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1073 | core::core_arch::aarch64::sve::generated | svldff1uh_vnum_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1074 | core::core_arch::aarch64::sve::generated | svldff1uh_vnum_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1075 | core::core_arch::aarch64::sve::generated | svldff1uh_vnum_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1076 | core::core_arch::aarch64::sve::generated | svldff1uw_gather_s64index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1077 | core::core_arch::aarch64::sve::generated | svldff1uw_gather_s64index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1078 | core::core_arch::aarch64::sve::generated | svldff1uw_gather_s64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1079 | core::core_arch::aarch64::sve::generated | svldff1uw_gather_s64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1080 | core::core_arch::aarch64::sve::generated | svldff1uw_gather_u64base_index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1081 | core::core_arch::aarch64::sve::generated | svldff1uw_gather_u64base_index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1082 | core::core_arch::aarch64::sve::generated | svldff1uw_gather_u64base_offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1083 | core::core_arch::aarch64::sve::generated | svldff1uw_gather_u64base_offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1084 | core::core_arch::aarch64::sve::generated | svldff1uw_gather_u64base_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1085 | core::core_arch::aarch64::sve::generated | svldff1uw_gather_u64base_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1086 | core::core_arch::aarch64::sve::generated | svldff1uw_gather_u64index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1087 | core::core_arch::aarch64::sve::generated | svldff1uw_gather_u64index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1088 | core::core_arch::aarch64::sve::generated | svldff1uw_gather_u64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1089 | core::core_arch::aarch64::sve::generated | svldff1uw_gather_u64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1090 | core::core_arch::aarch64::sve::generated | svldff1uw_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1091 | core::core_arch::aarch64::sve::generated | svldff1uw_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1092 | core::core_arch::aarch64::sve::generated | svldff1uw_vnum_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1093 | core::core_arch::aarch64::sve::generated | svldff1uw_vnum_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and first-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1094 | core::core_arch::aarch64::sve::generated | svldnf1_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1095 | core::core_arch::aarch64::sve::generated | svldnf1_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1096 | core::core_arch::aarch64::sve::generated | svldnf1_s16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1097 | core::core_arch::aarch64::sve::generated | svldnf1_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1098 | core::core_arch::aarch64::sve::generated | svldnf1_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1099 | core::core_arch::aarch64::sve::generated | svldnf1_s8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1100 | core::core_arch::aarch64::sve::generated | svldnf1_u16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1101 | core::core_arch::aarch64::sve::generated | svldnf1_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1102 | core::core_arch::aarch64::sve::generated | svldnf1_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1103 | core::core_arch::aarch64::sve::generated | svldnf1_u8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1104 | core::core_arch::aarch64::sve::generated | svldnf1_vnum_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1105 | core::core_arch::aarch64::sve::generated | svldnf1_vnum_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1106 | core::core_arch::aarch64::sve::generated | svldnf1_vnum_s16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1107 | core::core_arch::aarch64::sve::generated | svldnf1_vnum_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1108 | core::core_arch::aarch64::sve::generated | svldnf1_vnum_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1109 | core::core_arch::aarch64::sve::generated | svldnf1_vnum_s8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1110 | core::core_arch::aarch64::sve::generated | svldnf1_vnum_u16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1111 | core::core_arch::aarch64::sve::generated | svldnf1_vnum_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1112 | core::core_arch::aarch64::sve::generated | svldnf1_vnum_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1113 | core::core_arch::aarch64::sve::generated | svldnf1_vnum_u8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1114 | core::core_arch::aarch64::sve::generated | svldnf1sb_s16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1115 | core::core_arch::aarch64::sve::generated | svldnf1sb_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1116 | core::core_arch::aarch64::sve::generated | svldnf1sb_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1117 | core::core_arch::aarch64::sve::generated | svldnf1sb_u16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1118 | core::core_arch::aarch64::sve::generated | svldnf1sb_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1119 | core::core_arch::aarch64::sve::generated | svldnf1sb_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1120 | core::core_arch::aarch64::sve::generated | svldnf1sb_vnum_s16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1121 | core::core_arch::aarch64::sve::generated | svldnf1sb_vnum_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1122 | core::core_arch::aarch64::sve::generated | svldnf1sb_vnum_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1123 | core::core_arch::aarch64::sve::generated | svldnf1sb_vnum_u16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1124 | core::core_arch::aarch64::sve::generated | svldnf1sb_vnum_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1125 | core::core_arch::aarch64::sve::generated | svldnf1sb_vnum_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1126 | core::core_arch::aarch64::sve::generated | svldnf1sh_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1127 | core::core_arch::aarch64::sve::generated | svldnf1sh_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1128 | core::core_arch::aarch64::sve::generated | svldnf1sh_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1129 | core::core_arch::aarch64::sve::generated | svldnf1sh_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1130 | core::core_arch::aarch64::sve::generated | svldnf1sh_vnum_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1131 | core::core_arch::aarch64::sve::generated | svldnf1sh_vnum_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1132 | core::core_arch::aarch64::sve::generated | svldnf1sh_vnum_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1133 | core::core_arch::aarch64::sve::generated | svldnf1sh_vnum_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1134 | core::core_arch::aarch64::sve::generated | svldnf1sw_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1135 | core::core_arch::aarch64::sve::generated | svldnf1sw_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1136 | core::core_arch::aarch64::sve::generated | svldnf1sw_vnum_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1137 | core::core_arch::aarch64::sve::generated | svldnf1sw_vnum_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1138 | core::core_arch::aarch64::sve::generated | svldnf1ub_s16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1139 | core::core_arch::aarch64::sve::generated | svldnf1ub_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1140 | core::core_arch::aarch64::sve::generated | svldnf1ub_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1141 | core::core_arch::aarch64::sve::generated | svldnf1ub_u16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1142 | core::core_arch::aarch64::sve::generated | svldnf1ub_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1143 | core::core_arch::aarch64::sve::generated | svldnf1ub_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1144 | core::core_arch::aarch64::sve::generated | svldnf1ub_vnum_s16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1145 | core::core_arch::aarch64::sve::generated | svldnf1ub_vnum_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1146 | core::core_arch::aarch64::sve::generated | svldnf1ub_vnum_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1147 | core::core_arch::aarch64::sve::generated | svldnf1ub_vnum_u16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1148 | core::core_arch::aarch64::sve::generated | svldnf1ub_vnum_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1149 | core::core_arch::aarch64::sve::generated | svldnf1ub_vnum_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1150 | core::core_arch::aarch64::sve::generated | svldnf1uh_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1151 | core::core_arch::aarch64::sve::generated | svldnf1uh_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1152 | core::core_arch::aarch64::sve::generated | svldnf1uh_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1153 | core::core_arch::aarch64::sve::generated | svldnf1uh_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1154 | core::core_arch::aarch64::sve::generated | svldnf1uh_vnum_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1155 | core::core_arch::aarch64::sve::generated | svldnf1uh_vnum_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1156 | core::core_arch::aarch64::sve::generated | svldnf1uh_vnum_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1157 | core::core_arch::aarch64::sve::generated | svldnf1uh_vnum_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1158 | core::core_arch::aarch64::sve::generated | svldnf1uw_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1159 | core::core_arch::aarch64::sve::generated | svldnf1uw_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1160 | core::core_arch::aarch64::sve::generated | svldnf1uw_vnum_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1161 | core::core_arch::aarch64::sve::generated | svldnf1uw_vnum_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`, the first-fault register (`FFR`) and non-faulting behaviour). * Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details. | |
| 1162 | core::core_arch::aarch64::sve::generated | svldnt1_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 1163 | core::core_arch::aarch64::sve::generated | svldnt1_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 1164 | core::core_arch::aarch64::sve::generated | svldnt1_s16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 1165 | core::core_arch::aarch64::sve::generated | svldnt1_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 1166 | core::core_arch::aarch64::sve::generated | svldnt1_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 1167 | core::core_arch::aarch64::sve::generated | svldnt1_s8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 1168 | core::core_arch::aarch64::sve::generated | svldnt1_u16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 1169 | core::core_arch::aarch64::sve::generated | svldnt1_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 1170 | core::core_arch::aarch64::sve::generated | svldnt1_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 1171 | core::core_arch::aarch64::sve::generated | svldnt1_u8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 1172 | core::core_arch::aarch64::sve::generated | svldnt1_vnum_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 1173 | core::core_arch::aarch64::sve::generated | svldnt1_vnum_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 1174 | core::core_arch::aarch64::sve::generated | svldnt1_vnum_s16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 1175 | core::core_arch::aarch64::sve::generated | svldnt1_vnum_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 1176 | core::core_arch::aarch64::sve::generated | svldnt1_vnum_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 1177 | core::core_arch::aarch64::sve::generated | svldnt1_vnum_s8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 1178 | core::core_arch::aarch64::sve::generated | svldnt1_vnum_u16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 1179 | core::core_arch::aarch64::sve::generated | svldnt1_vnum_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 1180 | core::core_arch::aarch64::sve::generated | svldnt1_vnum_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 1181 | core::core_arch::aarch64::sve::generated | svldnt1_vnum_u8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 1182 | core::core_arch::aarch64::sve::generated | svprfb | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). | |
| 1183 | core::core_arch::aarch64::sve::generated | svprfb_gather_s32offset | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). | |
| 1184 | core::core_arch::aarch64::sve::generated | svprfb_gather_s64offset | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). | |
| 1185 | core::core_arch::aarch64::sve::generated | svprfb_gather_u32base | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1186 | core::core_arch::aarch64::sve::generated | svprfb_gather_u32base_offset | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1187 | core::core_arch::aarch64::sve::generated | svprfb_gather_u32offset | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). | |
| 1188 | core::core_arch::aarch64::sve::generated | svprfb_gather_u64base | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1189 | core::core_arch::aarch64::sve::generated | svprfb_gather_u64base_offset | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1190 | core::core_arch::aarch64::sve::generated | svprfb_gather_u64offset | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). | |
| 1191 | core::core_arch::aarch64::sve::generated | svprfb_vnum | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. | |
| 1192 | core::core_arch::aarch64::sve::generated | svprfd | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). | |
| 1193 | core::core_arch::aarch64::sve::generated | svprfd_gather_s32index | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). | |
| 1194 | core::core_arch::aarch64::sve::generated | svprfd_gather_s64index | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). | |
| 1195 | core::core_arch::aarch64::sve::generated | svprfd_gather_u32base | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1196 | core::core_arch::aarch64::sve::generated | svprfd_gather_u32base_index | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1197 | core::core_arch::aarch64::sve::generated | svprfd_gather_u32index | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). | |
| 1198 | core::core_arch::aarch64::sve::generated | svprfd_gather_u64base | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1199 | core::core_arch::aarch64::sve::generated | svprfd_gather_u64base_index | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1200 | core::core_arch::aarch64::sve::generated | svprfd_gather_u64index | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). | |
| 1201 | core::core_arch::aarch64::sve::generated | svprfd_vnum | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. | |
| 1202 | core::core_arch::aarch64::sve::generated | svprfh | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). | |
| 1203 | core::core_arch::aarch64::sve::generated | svprfh_gather_s32index | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). | |
| 1204 | core::core_arch::aarch64::sve::generated | svprfh_gather_s64index | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). | |
| 1205 | core::core_arch::aarch64::sve::generated | svprfh_gather_u32base | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1206 | core::core_arch::aarch64::sve::generated | svprfh_gather_u32base_index | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1207 | core::core_arch::aarch64::sve::generated | svprfh_gather_u32index | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). | |
| 1208 | core::core_arch::aarch64::sve::generated | svprfh_gather_u64base | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1209 | core::core_arch::aarch64::sve::generated | svprfh_gather_u64base_index | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1210 | core::core_arch::aarch64::sve::generated | svprfh_gather_u64index | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). | |
| 1211 | core::core_arch::aarch64::sve::generated | svprfh_vnum | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. | |
| 1212 | core::core_arch::aarch64::sve::generated | svprfw | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). | |
| 1213 | core::core_arch::aarch64::sve::generated | svprfw_gather_s32index | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). | |
| 1214 | core::core_arch::aarch64::sve::generated | svprfw_gather_s64index | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). | |
| 1215 | core::core_arch::aarch64::sve::generated | svprfw_gather_u32base | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1216 | core::core_arch::aarch64::sve::generated | svprfw_gather_u32base_index | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1217 | core::core_arch::aarch64::sve::generated | svprfw_gather_u32index | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). | |
| 1218 | core::core_arch::aarch64::sve::generated | svprfw_gather_u64base | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1219 | core::core_arch::aarch64::sve::generated | svprfw_gather_u64base_index | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1220 | core::core_arch::aarch64::sve::generated | svprfw_gather_u64index | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). | |
| 1221 | core::core_arch::aarch64::sve::generated | svprfw_vnum | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. | |
| 1222 | core::core_arch::aarch64::sve::generated | svst1_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1223 | core::core_arch::aarch64::sve::generated | svst1_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1224 | core::core_arch::aarch64::sve::generated | svst1_s16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1225 | core::core_arch::aarch64::sve::generated | svst1_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1226 | core::core_arch::aarch64::sve::generated | svst1_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1227 | core::core_arch::aarch64::sve::generated | svst1_s8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1228 | core::core_arch::aarch64::sve::generated | svst1_scatter_s32index_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1229 | core::core_arch::aarch64::sve::generated | svst1_scatter_s32index_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1230 | core::core_arch::aarch64::sve::generated | svst1_scatter_s32index_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1231 | core::core_arch::aarch64::sve::generated | svst1_scatter_s32offset_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1232 | core::core_arch::aarch64::sve::generated | svst1_scatter_s32offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1233 | core::core_arch::aarch64::sve::generated | svst1_scatter_s32offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1234 | core::core_arch::aarch64::sve::generated | svst1_scatter_s64index_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1235 | core::core_arch::aarch64::sve::generated | svst1_scatter_s64index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1236 | core::core_arch::aarch64::sve::generated | svst1_scatter_s64index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1237 | core::core_arch::aarch64::sve::generated | svst1_scatter_s64offset_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1238 | core::core_arch::aarch64::sve::generated | svst1_scatter_s64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1239 | core::core_arch::aarch64::sve::generated | svst1_scatter_s64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1240 | core::core_arch::aarch64::sve::generated | svst1_scatter_u32base_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1241 | core::core_arch::aarch64::sve::generated | svst1_scatter_u32base_index_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1242 | core::core_arch::aarch64::sve::generated | svst1_scatter_u32base_index_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1243 | core::core_arch::aarch64::sve::generated | svst1_scatter_u32base_index_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1244 | core::core_arch::aarch64::sve::generated | svst1_scatter_u32base_offset_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1245 | core::core_arch::aarch64::sve::generated | svst1_scatter_u32base_offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1246 | core::core_arch::aarch64::sve::generated | svst1_scatter_u32base_offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1247 | core::core_arch::aarch64::sve::generated | svst1_scatter_u32base_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1248 | core::core_arch::aarch64::sve::generated | svst1_scatter_u32base_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1249 | core::core_arch::aarch64::sve::generated | svst1_scatter_u32index_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1250 | core::core_arch::aarch64::sve::generated | svst1_scatter_u32index_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1251 | core::core_arch::aarch64::sve::generated | svst1_scatter_u32index_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1252 | core::core_arch::aarch64::sve::generated | svst1_scatter_u32offset_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1253 | core::core_arch::aarch64::sve::generated | svst1_scatter_u32offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1254 | core::core_arch::aarch64::sve::generated | svst1_scatter_u32offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1255 | core::core_arch::aarch64::sve::generated | svst1_scatter_u64base_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1256 | core::core_arch::aarch64::sve::generated | svst1_scatter_u64base_index_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1257 | core::core_arch::aarch64::sve::generated | svst1_scatter_u64base_index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1258 | core::core_arch::aarch64::sve::generated | svst1_scatter_u64base_index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1259 | core::core_arch::aarch64::sve::generated | svst1_scatter_u64base_offset_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1260 | core::core_arch::aarch64::sve::generated | svst1_scatter_u64base_offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1261 | core::core_arch::aarch64::sve::generated | svst1_scatter_u64base_offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1262 | core::core_arch::aarch64::sve::generated | svst1_scatter_u64base_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1263 | core::core_arch::aarch64::sve::generated | svst1_scatter_u64base_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1264 | core::core_arch::aarch64::sve::generated | svst1_scatter_u64index_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1265 | core::core_arch::aarch64::sve::generated | svst1_scatter_u64index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1266 | core::core_arch::aarch64::sve::generated | svst1_scatter_u64index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1267 | core::core_arch::aarch64::sve::generated | svst1_scatter_u64offset_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1268 | core::core_arch::aarch64::sve::generated | svst1_scatter_u64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1269 | core::core_arch::aarch64::sve::generated | svst1_scatter_u64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1270 | core::core_arch::aarch64::sve::generated | svst1_u16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1271 | core::core_arch::aarch64::sve::generated | svst1_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1272 | core::core_arch::aarch64::sve::generated | svst1_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1273 | core::core_arch::aarch64::sve::generated | svst1_u8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1274 | core::core_arch::aarch64::sve::generated | svst1_vnum_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1275 | core::core_arch::aarch64::sve::generated | svst1_vnum_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1276 | core::core_arch::aarch64::sve::generated | svst1_vnum_s16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1277 | core::core_arch::aarch64::sve::generated | svst1_vnum_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1278 | core::core_arch::aarch64::sve::generated | svst1_vnum_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1279 | core::core_arch::aarch64::sve::generated | svst1_vnum_s8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1280 | core::core_arch::aarch64::sve::generated | svst1_vnum_u16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1281 | core::core_arch::aarch64::sve::generated | svst1_vnum_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1282 | core::core_arch::aarch64::sve::generated | svst1_vnum_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1283 | core::core_arch::aarch64::sve::generated | svst1_vnum_u8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1284 | core::core_arch::aarch64::sve::generated | svst1b_s16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1285 | core::core_arch::aarch64::sve::generated | svst1b_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1286 | core::core_arch::aarch64::sve::generated | svst1b_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1287 | core::core_arch::aarch64::sve::generated | svst1b_scatter_s32offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1288 | core::core_arch::aarch64::sve::generated | svst1b_scatter_s32offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1289 | core::core_arch::aarch64::sve::generated | svst1b_scatter_s64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1290 | core::core_arch::aarch64::sve::generated | svst1b_scatter_s64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1291 | core::core_arch::aarch64::sve::generated | svst1b_scatter_u32base_offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1292 | core::core_arch::aarch64::sve::generated | svst1b_scatter_u32base_offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1293 | core::core_arch::aarch64::sve::generated | svst1b_scatter_u32base_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1294 | core::core_arch::aarch64::sve::generated | svst1b_scatter_u32base_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1295 | core::core_arch::aarch64::sve::generated | svst1b_scatter_u32offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1296 | core::core_arch::aarch64::sve::generated | svst1b_scatter_u32offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1297 | core::core_arch::aarch64::sve::generated | svst1b_scatter_u64base_offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1298 | core::core_arch::aarch64::sve::generated | svst1b_scatter_u64base_offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1299 | core::core_arch::aarch64::sve::generated | svst1b_scatter_u64base_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1300 | core::core_arch::aarch64::sve::generated | svst1b_scatter_u64base_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1301 | core::core_arch::aarch64::sve::generated | svst1b_scatter_u64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1302 | core::core_arch::aarch64::sve::generated | svst1b_scatter_u64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1303 | core::core_arch::aarch64::sve::generated | svst1b_u16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1304 | core::core_arch::aarch64::sve::generated | svst1b_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1305 | core::core_arch::aarch64::sve::generated | svst1b_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1306 | core::core_arch::aarch64::sve::generated | svst1b_vnum_s16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1307 | core::core_arch::aarch64::sve::generated | svst1b_vnum_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1308 | core::core_arch::aarch64::sve::generated | svst1b_vnum_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1309 | core::core_arch::aarch64::sve::generated | svst1b_vnum_u16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1310 | core::core_arch::aarch64::sve::generated | svst1b_vnum_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1311 | core::core_arch::aarch64::sve::generated | svst1b_vnum_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1312 | core::core_arch::aarch64::sve::generated | svst1h_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1313 | core::core_arch::aarch64::sve::generated | svst1h_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1314 | core::core_arch::aarch64::sve::generated | svst1h_scatter_s32index_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1315 | core::core_arch::aarch64::sve::generated | svst1h_scatter_s32index_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1316 | core::core_arch::aarch64::sve::generated | svst1h_scatter_s32offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1317 | core::core_arch::aarch64::sve::generated | svst1h_scatter_s32offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1318 | core::core_arch::aarch64::sve::generated | svst1h_scatter_s64index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1319 | core::core_arch::aarch64::sve::generated | svst1h_scatter_s64index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1320 | core::core_arch::aarch64::sve::generated | svst1h_scatter_s64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1321 | core::core_arch::aarch64::sve::generated | svst1h_scatter_s64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1322 | core::core_arch::aarch64::sve::generated | svst1h_scatter_u32base_index_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1323 | core::core_arch::aarch64::sve::generated | svst1h_scatter_u32base_index_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1324 | core::core_arch::aarch64::sve::generated | svst1h_scatter_u32base_offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1325 | core::core_arch::aarch64::sve::generated | svst1h_scatter_u32base_offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1326 | core::core_arch::aarch64::sve::generated | svst1h_scatter_u32base_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1327 | core::core_arch::aarch64::sve::generated | svst1h_scatter_u32base_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1328 | core::core_arch::aarch64::sve::generated | svst1h_scatter_u32index_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1329 | core::core_arch::aarch64::sve::generated | svst1h_scatter_u32index_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1330 | core::core_arch::aarch64::sve::generated | svst1h_scatter_u32offset_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1331 | core::core_arch::aarch64::sve::generated | svst1h_scatter_u32offset_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1332 | core::core_arch::aarch64::sve::generated | svst1h_scatter_u64base_index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1333 | core::core_arch::aarch64::sve::generated | svst1h_scatter_u64base_index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1334 | core::core_arch::aarch64::sve::generated | svst1h_scatter_u64base_offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1335 | core::core_arch::aarch64::sve::generated | svst1h_scatter_u64base_offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1336 | core::core_arch::aarch64::sve::generated | svst1h_scatter_u64base_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1337 | core::core_arch::aarch64::sve::generated | svst1h_scatter_u64base_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1338 | core::core_arch::aarch64::sve::generated | svst1h_scatter_u64index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1339 | core::core_arch::aarch64::sve::generated | svst1h_scatter_u64index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1340 | core::core_arch::aarch64::sve::generated | svst1h_scatter_u64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1341 | core::core_arch::aarch64::sve::generated | svst1h_scatter_u64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1342 | core::core_arch::aarch64::sve::generated | svst1h_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1343 | core::core_arch::aarch64::sve::generated | svst1h_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1344 | core::core_arch::aarch64::sve::generated | svst1h_vnum_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1345 | core::core_arch::aarch64::sve::generated | svst1h_vnum_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1346 | core::core_arch::aarch64::sve::generated | svst1h_vnum_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1347 | core::core_arch::aarch64::sve::generated | svst1h_vnum_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1348 | core::core_arch::aarch64::sve::generated | svst1w_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1349 | core::core_arch::aarch64::sve::generated | svst1w_scatter_s64index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1350 | core::core_arch::aarch64::sve::generated | svst1w_scatter_s64index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1351 | core::core_arch::aarch64::sve::generated | svst1w_scatter_s64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1352 | core::core_arch::aarch64::sve::generated | svst1w_scatter_s64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1353 | core::core_arch::aarch64::sve::generated | svst1w_scatter_u64base_index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1354 | core::core_arch::aarch64::sve::generated | svst1w_scatter_u64base_index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1355 | core::core_arch::aarch64::sve::generated | svst1w_scatter_u64base_offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1356 | core::core_arch::aarch64::sve::generated | svst1w_scatter_u64base_offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1357 | core::core_arch::aarch64::sve::generated | svst1w_scatter_u64base_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1358 | core::core_arch::aarch64::sve::generated | svst1w_scatter_u64base_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Addresses passed in `bases` lack provenance, so this is similar to using a `usize as ptr` cast (or [`core::ptr::with_exposed_provenance`]) on each lane before using it. | |
| 1359 | core::core_arch::aarch64::sve::generated | svst1w_scatter_u64index_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1360 | core::core_arch::aarch64::sve::generated | svst1w_scatter_u64index_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1361 | core::core_arch::aarch64::sve::generated | svst1w_scatter_u64offset_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1362 | core::core_arch::aarch64::sve::generated | svst1w_scatter_u64offset_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1363 | core::core_arch::aarch64::sve::generated | svst1w_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1364 | core::core_arch::aarch64::sve::generated | svst1w_vnum_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1365 | core::core_arch::aarch64::sve::generated | svst1w_vnum_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1366 | core::core_arch::aarch64::sve::generated | svst2_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1367 | core::core_arch::aarch64::sve::generated | svst2_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1368 | core::core_arch::aarch64::sve::generated | svst2_s16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1369 | core::core_arch::aarch64::sve::generated | svst2_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1370 | core::core_arch::aarch64::sve::generated | svst2_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1371 | core::core_arch::aarch64::sve::generated | svst2_s8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1372 | core::core_arch::aarch64::sve::generated | svst2_u16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1373 | core::core_arch::aarch64::sve::generated | svst2_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1374 | core::core_arch::aarch64::sve::generated | svst2_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1375 | core::core_arch::aarch64::sve::generated | svst2_u8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1376 | core::core_arch::aarch64::sve::generated | svst2_vnum_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1377 | core::core_arch::aarch64::sve::generated | svst2_vnum_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1378 | core::core_arch::aarch64::sve::generated | svst2_vnum_s16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1379 | core::core_arch::aarch64::sve::generated | svst2_vnum_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1380 | core::core_arch::aarch64::sve::generated | svst2_vnum_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1381 | core::core_arch::aarch64::sve::generated | svst2_vnum_s8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1382 | core::core_arch::aarch64::sve::generated | svst2_vnum_u16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1383 | core::core_arch::aarch64::sve::generated | svst2_vnum_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1384 | core::core_arch::aarch64::sve::generated | svst2_vnum_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1385 | core::core_arch::aarch64::sve::generated | svst2_vnum_u8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1386 | core::core_arch::aarch64::sve::generated | svst3_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1387 | core::core_arch::aarch64::sve::generated | svst3_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1388 | core::core_arch::aarch64::sve::generated | svst3_s16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1389 | core::core_arch::aarch64::sve::generated | svst3_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1390 | core::core_arch::aarch64::sve::generated | svst3_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1391 | core::core_arch::aarch64::sve::generated | svst3_s8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1392 | core::core_arch::aarch64::sve::generated | svst3_u16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1393 | core::core_arch::aarch64::sve::generated | svst3_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1394 | core::core_arch::aarch64::sve::generated | svst3_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1395 | core::core_arch::aarch64::sve::generated | svst3_u8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1396 | core::core_arch::aarch64::sve::generated | svst3_vnum_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1397 | core::core_arch::aarch64::sve::generated | svst3_vnum_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1398 | core::core_arch::aarch64::sve::generated | svst3_vnum_s16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1399 | core::core_arch::aarch64::sve::generated | svst3_vnum_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1400 | core::core_arch::aarch64::sve::generated | svst3_vnum_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1401 | core::core_arch::aarch64::sve::generated | svst3_vnum_s8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1402 | core::core_arch::aarch64::sve::generated | svst3_vnum_u16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1403 | core::core_arch::aarch64::sve::generated | svst3_vnum_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1404 | core::core_arch::aarch64::sve::generated | svst3_vnum_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1405 | core::core_arch::aarch64::sve::generated | svst3_vnum_u8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1406 | core::core_arch::aarch64::sve::generated | svst4_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1407 | core::core_arch::aarch64::sve::generated | svst4_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1408 | core::core_arch::aarch64::sve::generated | svst4_s16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1409 | core::core_arch::aarch64::sve::generated | svst4_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1410 | core::core_arch::aarch64::sve::generated | svst4_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1411 | core::core_arch::aarch64::sve::generated | svst4_s8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1412 | core::core_arch::aarch64::sve::generated | svst4_u16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1413 | core::core_arch::aarch64::sve::generated | svst4_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1414 | core::core_arch::aarch64::sve::generated | svst4_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1415 | core::core_arch::aarch64::sve::generated | svst4_u8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1416 | core::core_arch::aarch64::sve::generated | svst4_vnum_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1417 | core::core_arch::aarch64::sve::generated | svst4_vnum_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1418 | core::core_arch::aarch64::sve::generated | svst4_vnum_s16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1419 | core::core_arch::aarch64::sve::generated | svst4_vnum_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1420 | core::core_arch::aarch64::sve::generated | svst4_vnum_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1421 | core::core_arch::aarch64::sve::generated | svst4_vnum_s8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1422 | core::core_arch::aarch64::sve::generated | svst4_vnum_u16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1423 | core::core_arch::aarch64::sve::generated | svst4_vnum_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1424 | core::core_arch::aarch64::sve::generated | svst4_vnum_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1425 | core::core_arch::aarch64::sve::generated | svst4_vnum_u8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). In particular, note that `vnum` is scaled by the vector length, `VL`, which is not known at compile time. * This dereferences and accesses the calculated address for each active element (governed by `pg`). | |
| 1426 | core::core_arch::aarch64::sve::generated | svstnt1_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 1427 | core::core_arch::aarch64::sve::generated | svstnt1_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 1428 | core::core_arch::aarch64::sve::generated | svstnt1_s16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 1429 | core::core_arch::aarch64::sve::generated | svstnt1_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 1430 | core::core_arch::aarch64::sve::generated | svstnt1_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 1431 | core::core_arch::aarch64::sve::generated | svstnt1_s8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 1432 | core::core_arch::aarch64::sve::generated | svstnt1_u16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 1433 | core::core_arch::aarch64::sve::generated | svstnt1_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 1434 | core::core_arch::aarch64::sve::generated | svstnt1_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 1435 | core::core_arch::aarch64::sve::generated | svstnt1_u8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 1436 | core::core_arch::aarch64::sve::generated | svstnt1_vnum_f32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 1437 | core::core_arch::aarch64::sve::generated | svstnt1_vnum_f64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 1438 | core::core_arch::aarch64::sve::generated | svstnt1_vnum_s16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 1439 | core::core_arch::aarch64::sve::generated | svstnt1_vnum_s32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 1440 | core::core_arch::aarch64::sve::generated | svstnt1_vnum_s64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 1441 | core::core_arch::aarch64::sve::generated | svstnt1_vnum_s8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 1442 | core::core_arch::aarch64::sve::generated | svstnt1_vnum_u16 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 1443 | core::core_arch::aarch64::sve::generated | svstnt1_vnum_u32 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 1444 | core::core_arch::aarch64::sve::generated | svstnt1_vnum_u64 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 1445 | core::core_arch::aarch64::sve::generated | svstnt1_vnum_u8 | function | * [`pointer::offset`](pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by `pg`). * This dereferences and accesses the calculated address for each active element (governed by `pg`). * Non-temporal accesses have special memory ordering rules, and [explicit barriers may be required for some applications](https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en). | |
| 1446 | core::core_arch::aarch64::sve::generated | svundef2_f32 | function | * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`]). | |
| 1447 | core::core_arch::aarch64::sve::generated | svundef2_f64 | function | * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`]). | |
| 1448 | core::core_arch::aarch64::sve::generated | svundef2_s16 | function | * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`]). | |
| 1449 | core::core_arch::aarch64::sve::generated | svundef2_s32 | function | * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`]). | |
| 1450 | core::core_arch::aarch64::sve::generated | svundef2_s64 | function | * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`]). | |
| 1451 | core::core_arch::aarch64::sve::generated | svundef2_s8 | function | * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`]). | |
| 1452 | core::core_arch::aarch64::sve::generated | svundef2_u16 | function | * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`]). | |
| 1453 | core::core_arch::aarch64::sve::generated | svundef2_u32 | function | * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`]). | |
| 1454 | core::core_arch::aarch64::sve::generated | svundef2_u64 | function | * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`]). | |
| 1455 | core::core_arch::aarch64::sve::generated | svundef2_u8 | function | * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`]). | |
| 1456 | core::core_arch::aarch64::sve::generated | svundef3_f32 | function | * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`]). | |
| 1457 | core::core_arch::aarch64::sve::generated | svundef3_f64 | function | * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`]). | |
| 1458 | core::core_arch::aarch64::sve::generated | svundef3_s16 | function | * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`]). | |
| 1459 | core::core_arch::aarch64::sve::generated | svundef3_s32 | function | * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`]). | |
| 1460 | core::core_arch::aarch64::sve::generated | svundef3_s64 | function | * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`]). | |
| 1461 | core::core_arch::aarch64::sve::generated | svundef3_s8 | function | * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`]). | |
| 1462 | core::core_arch::aarch64::sve::generated | svundef3_u16 | function | * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`]). | |
| 1463 | core::core_arch::aarch64::sve::generated | svundef3_u32 | function | * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`]). | |
| 1464 | core::core_arch::aarch64::sve::generated | svundef3_u64 | function | * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`]). | |
| 1465 | core::core_arch::aarch64::sve::generated | svundef3_u8 | function | * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`]). | |
| 1466 | core::core_arch::aarch64::sve::generated | svundef4_f32 | function | * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`]). | |
| 1467 | core::core_arch::aarch64::sve::generated | svundef4_f64 | function | * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`]). | |
| 1468 | core::core_arch::aarch64::sve::generated | svundef4_s16 | function | * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`]). | |
| 1469 | core::core_arch::aarch64::sve::generated | svundef4_s32 | function | * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`]). | |
| 1470 | core::core_arch::aarch64::sve::generated | svundef4_s64 | function | * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`]). | |
| 1471 | core::core_arch::aarch64::sve::generated | svundef4_s8 | function | * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`]). | |
| 1472 | core::core_arch::aarch64::sve::generated | svundef4_u16 | function | * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`]). | |
| 1473 | core::core_arch::aarch64::sve::generated | svundef4_u32 | function | * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`]). | |
| 1474 | core::core_arch::aarch64::sve::generated | svundef4_u64 | function | * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`]). | |
| 1475 | core::core_arch::aarch64::sve::generated | svundef4_u8 | function | * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`]). | |
| 1476 | core::core_arch::aarch64::sve::generated | svundef_f32 | function | * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`]). | |
| 1477 | core::core_arch::aarch64::sve::generated | svundef_f64 | function | * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`]). | |
| 1478 | core::core_arch::aarch64::sve::generated | svundef_s16 | function | * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`]). | |
| 1479 | core::core_arch::aarch64::sve::generated | svundef_s32 | function | * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`]). | |
| 1480 | core::core_arch::aarch64::sve::generated | svundef_s64 | function | * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`]). | |
| 1481 | core::core_arch::aarch64::sve::generated | svundef_s8 | function | * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`]). | |
| 1482 | core::core_arch::aarch64::sve::generated | svundef_u16 | function | * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`]). | |
| 1483 | core::core_arch::aarch64::sve::generated | svundef_u32 | function | * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`]). | |
| 1484 | core::core_arch::aarch64::sve::generated | svundef_u64 | function | * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`]). | |
| 1485 | core::core_arch::aarch64::sve::generated | svundef_u8 | function | * This creates an uninitialized value, and may be unsound (like [`core::mem::uninitialized`]). | |
| 1486 | core::core_arch::amdgpu | ds_bpermute | function | ||
| 1487 | core::core_arch::amdgpu | ds_permute | function | ||
| 1488 | core::core_arch::amdgpu | perm | function | ||
| 1489 | core::core_arch::amdgpu | permlane16_swap | function | ||
| 1490 | core::core_arch::amdgpu | permlane16_u32 | function | ||
| 1491 | core::core_arch::amdgpu | permlane16_var | function | ||
| 1492 | core::core_arch::amdgpu | permlane32_swap | function | ||
| 1493 | core::core_arch::amdgpu | permlane64_u32 | function | ||
| 1494 | core::core_arch::amdgpu | permlanex16_u32 | function | ||
| 1495 | core::core_arch::amdgpu | permlanex16_var | function | ||
| 1496 | core::core_arch::amdgpu | readlane_u32 | function | ||
| 1497 | core::core_arch::amdgpu | readlane_u64 | function | ||
| 1498 | core::core_arch::amdgpu | s_barrier_signal | function | ||
| 1499 | core::core_arch::amdgpu | s_barrier_signal_isfirst | function | ||
| 1500 | core::core_arch::amdgpu | s_barrier_wait | function | ||
| 1501 | core::core_arch::amdgpu | s_get_barrier_state | function | ||
| 1502 | core::core_arch::amdgpu | sched_barrier | function | ||
| 1503 | core::core_arch::amdgpu | sched_group_barrier | function | ||
| 1504 | core::core_arch::amdgpu | update_dpp | function | ||
| 1505 | core::core_arch::amdgpu | writelane_u32 | function | ||
| 1506 | core::core_arch::amdgpu | writelane_u64 | function | ||
| 1507 | core::core_arch::arm::dsp | __qadd | function | ||
| 1508 | core::core_arch::arm::dsp | __qdbl | function | ||
| 1509 | core::core_arch::arm::dsp | __qsub | function | ||
| 1510 | core::core_arch::arm::dsp | __smlabb | function | ||
| 1511 | core::core_arch::arm::dsp | __smlabt | function | ||
| 1512 | core::core_arch::arm::dsp | __smlatb | function | ||
| 1513 | core::core_arch::arm::dsp | __smlatt | function | ||
| 1514 | core::core_arch::arm::dsp | __smlawb | function | ||
| 1515 | core::core_arch::arm::dsp | __smlawt | function | ||
| 1516 | core::core_arch::arm::dsp | __smulbb | function | ||
| 1517 | core::core_arch::arm::dsp | __smulbt | function | ||
| 1518 | core::core_arch::arm::dsp | __smultb | function | ||
| 1519 | core::core_arch::arm::dsp | __smultt | function | ||
| 1520 | core::core_arch::arm::dsp | __smulwb | function | ||
| 1521 | core::core_arch::arm::dsp | __smulwt | function | ||
| 1522 | core::core_arch::arm::sat | __ssat | function | ||
| 1523 | core::core_arch::arm::sat | __usat | function | ||
| 1524 | core::core_arch::arm::simd32 | __qadd16 | function | ||
| 1525 | core::core_arch::arm::simd32 | __qadd8 | function | ||
| 1526 | core::core_arch::arm::simd32 | __qasx | function | ||
| 1527 | core::core_arch::arm::simd32 | __qsax | function | ||
| 1528 | core::core_arch::arm::simd32 | __qsub16 | function | ||
| 1529 | core::core_arch::arm::simd32 | __qsub8 | function | ||
| 1530 | core::core_arch::arm::simd32 | __sadd16 | function | ||
| 1531 | core::core_arch::arm::simd32 | __sadd8 | function | ||
| 1532 | core::core_arch::arm::simd32 | __sasx | function | ||
| 1533 | core::core_arch::arm::simd32 | __sel | function | ||
| 1534 | core::core_arch::arm::simd32 | __shadd16 | function | ||
| 1535 | core::core_arch::arm::simd32 | __shadd8 | function | ||
| 1536 | core::core_arch::arm::simd32 | __shsub16 | function | ||
| 1537 | core::core_arch::arm::simd32 | __shsub8 | function | ||
| 1538 | core::core_arch::arm::simd32 | __smlad | function | ||
| 1539 | core::core_arch::arm::simd32 | __smlsd | function | ||
| 1540 | core::core_arch::arm::simd32 | __smuad | function | ||
| 1541 | core::core_arch::arm::simd32 | __smuadx | function | ||
| 1542 | core::core_arch::arm::simd32 | __smusd | function | ||
| 1543 | core::core_arch::arm::simd32 | __smusdx | function | ||
| 1544 | core::core_arch::arm::simd32 | __ssub8 | function | ||
| 1545 | core::core_arch::arm::simd32 | __usad8 | function | ||
| 1546 | core::core_arch::arm::simd32 | __usada8 | function | ||
| 1547 | core::core_arch::arm::simd32 | __usub8 | function | ||
| 1548 | core::core_arch::arm_shared::barrier | __dmb | function | ||
| 1549 | core::core_arch::arm_shared::barrier | __dsb | function | ||
| 1550 | core::core_arch::arm_shared::barrier | __isb | function | ||
| 1551 | core::core_arch::arm_shared::hints | __nop | function | ||
| 1552 | core::core_arch::arm_shared::hints | __sev | function | ||
| 1553 | core::core_arch::arm_shared::hints | __sevl | function | ||
| 1554 | core::core_arch::arm_shared::hints | __wfe | function | ||
| 1555 | core::core_arch::arm_shared::hints | __wfi | function | ||
| 1556 | core::core_arch::arm_shared::hints | __yield | function | ||
| 1557 | core::core_arch::arm_shared::neon::generated | vext_s64 | function | * Neon intrinsic unsafe | |
| 1558 | core::core_arch::arm_shared::neon::generated | vext_u64 | function | * Neon intrinsic unsafe | |
| 1559 | core::core_arch::arm_shared::neon::generated | vld1_dup_f16 | function | * Neon intrinsic unsafe | |
| 1560 | core::core_arch::arm_shared::neon::generated | vld1_dup_f32 | function | * Neon intrinsic unsafe | |
| 1561 | core::core_arch::arm_shared::neon::generated | vld1_dup_p16 | function | * Neon intrinsic unsafe | |
| 1562 | core::core_arch::arm_shared::neon::generated | vld1_dup_p64 | function | * Neon intrinsic unsafe | |
| 1563 | core::core_arch::arm_shared::neon::generated | vld1_dup_p8 | function | * Neon intrinsic unsafe | |
| 1564 | core::core_arch::arm_shared::neon::generated | vld1_dup_s16 | function | * Neon intrinsic unsafe | |
| 1565 | core::core_arch::arm_shared::neon::generated | vld1_dup_s32 | function | * Neon intrinsic unsafe | |
| 1566 | core::core_arch::arm_shared::neon::generated | vld1_dup_s64 | function | * Neon intrinsic unsafe | |
| 1567 | core::core_arch::arm_shared::neon::generated | vld1_dup_s8 | function | * Neon intrinsic unsafe | |
| 1568 | core::core_arch::arm_shared::neon::generated | vld1_dup_u16 | function | * Neon intrinsic unsafe | |
| 1569 | core::core_arch::arm_shared::neon::generated | vld1_dup_u32 | function | * Neon intrinsic unsafe | |
| 1570 | core::core_arch::arm_shared::neon::generated | vld1_dup_u64 | function | * Neon intrinsic unsafe | |
| 1571 | core::core_arch::arm_shared::neon::generated | vld1_dup_u8 | function | * Neon intrinsic unsafe | |
| 1572 | core::core_arch::arm_shared::neon::generated | vld1_f16_x2 | function | * Neon intrinsic unsafe | |
| 1573 | core::core_arch::arm_shared::neon::generated | vld1_f16_x3 | function | * Neon intrinsic unsafe | |
| 1574 | core::core_arch::arm_shared::neon::generated | vld1_f16_x4 | function | * Neon intrinsic unsafe | |
| 1575 | core::core_arch::arm_shared::neon::generated | vld1_f32_x2 | function | * Neon intrinsic unsafe | |
| 1576 | core::core_arch::arm_shared::neon::generated | vld1_f32_x3 | function | * Neon intrinsic unsafe | |
| 1577 | core::core_arch::arm_shared::neon::generated | vld1_f32_x4 | function | * Neon intrinsic unsafe | |
| 1578 | core::core_arch::arm_shared::neon::generated | vld1_lane_f16 | function | * Neon intrinsic unsafe | |
| 1579 | core::core_arch::arm_shared::neon::generated | vld1_lane_f32 | function | * Neon intrinsic unsafe | |
| 1580 | core::core_arch::arm_shared::neon::generated | vld1_lane_p16 | function | * Neon intrinsic unsafe | |
| 1581 | core::core_arch::arm_shared::neon::generated | vld1_lane_p64 | function | * Neon intrinsic unsafe | |
| 1582 | core::core_arch::arm_shared::neon::generated | vld1_lane_p8 | function | * Neon intrinsic unsafe | |
| 1583 | core::core_arch::arm_shared::neon::generated | vld1_lane_s16 | function | * Neon intrinsic unsafe | |
| 1584 | core::core_arch::arm_shared::neon::generated | vld1_lane_s32 | function | * Neon intrinsic unsafe | |
| 1585 | core::core_arch::arm_shared::neon::generated | vld1_lane_s64 | function | * Neon intrinsic unsafe | |
| 1586 | core::core_arch::arm_shared::neon::generated | vld1_lane_s8 | function | * Neon intrinsic unsafe | |
| 1587 | core::core_arch::arm_shared::neon::generated | vld1_lane_u16 | function | * Neon intrinsic unsafe | |
| 1588 | core::core_arch::arm_shared::neon::generated | vld1_lane_u32 | function | * Neon intrinsic unsafe | |
| 1589 | core::core_arch::arm_shared::neon::generated | vld1_lane_u64 | function | * Neon intrinsic unsafe | |
| 1590 | core::core_arch::arm_shared::neon::generated | vld1_lane_u8 | function | * Neon intrinsic unsafe | |
| 1591 | core::core_arch::arm_shared::neon::generated | vld1_p16_x2 | function | * Neon intrinsic unsafe | |
| 1592 | core::core_arch::arm_shared::neon::generated | vld1_p16_x3 | function | * Neon intrinsic unsafe | |
| 1593 | core::core_arch::arm_shared::neon::generated | vld1_p16_x4 | function | * Neon intrinsic unsafe | |
| 1594 | core::core_arch::arm_shared::neon::generated | vld1_p64_x2 | function | * Neon intrinsic unsafe | |
| 1595 | core::core_arch::arm_shared::neon::generated | vld1_p64_x3 | function | * Neon intrinsic unsafe | |
| 1596 | core::core_arch::arm_shared::neon::generated | vld1_p64_x4 | function | * Neon intrinsic unsafe | |
| 1597 | core::core_arch::arm_shared::neon::generated | vld1_p8_x2 | function | * Neon intrinsic unsafe | |
| 1598 | core::core_arch::arm_shared::neon::generated | vld1_p8_x3 | function | * Neon intrinsic unsafe | |
| 1599 | core::core_arch::arm_shared::neon::generated | vld1_p8_x4 | function | * Neon intrinsic unsafe | |
| 1600 | core::core_arch::arm_shared::neon::generated | vld1_s16_x2 | function | * Neon intrinsic unsafe | |
| 1601 | core::core_arch::arm_shared::neon::generated | vld1_s16_x3 | function | * Neon intrinsic unsafe | |
| 1602 | core::core_arch::arm_shared::neon::generated | vld1_s16_x4 | function | * Neon intrinsic unsafe | |
| 1603 | core::core_arch::arm_shared::neon::generated | vld1_s32_x2 | function | * Neon intrinsic unsafe | |
| 1604 | core::core_arch::arm_shared::neon::generated | vld1_s32_x3 | function | * Neon intrinsic unsafe | |
| 1605 | core::core_arch::arm_shared::neon::generated | vld1_s32_x4 | function | * Neon intrinsic unsafe | |
| 1606 | core::core_arch::arm_shared::neon::generated | vld1_s64_x2 | function | * Neon intrinsic unsafe | |
| 1607 | core::core_arch::arm_shared::neon::generated | vld1_s64_x3 | function | * Neon intrinsic unsafe | |
| 1608 | core::core_arch::arm_shared::neon::generated | vld1_s64_x4 | function | * Neon intrinsic unsafe | |
| 1609 | core::core_arch::arm_shared::neon::generated | vld1_s8_x2 | function | * Neon intrinsic unsafe | |
| 1610 | core::core_arch::arm_shared::neon::generated | vld1_s8_x3 | function | * Neon intrinsic unsafe | |
| 1611 | core::core_arch::arm_shared::neon::generated | vld1_s8_x4 | function | * Neon intrinsic unsafe | |
| 1612 | core::core_arch::arm_shared::neon::generated | vld1_u16_x2 | function | * Neon intrinsic unsafe | |
| 1613 | core::core_arch::arm_shared::neon::generated | vld1_u16_x3 | function | * Neon intrinsic unsafe | |
| 1614 | core::core_arch::arm_shared::neon::generated | vld1_u16_x4 | function | * Neon intrinsic unsafe | |
| 1615 | core::core_arch::arm_shared::neon::generated | vld1_u32_x2 | function | * Neon intrinsic unsafe | |
| 1616 | core::core_arch::arm_shared::neon::generated | vld1_u32_x3 | function | * Neon intrinsic unsafe | |
| 1617 | core::core_arch::arm_shared::neon::generated | vld1_u32_x4 | function | * Neon intrinsic unsafe | |
| 1618 | core::core_arch::arm_shared::neon::generated | vld1_u64_x2 | function | * Neon intrinsic unsafe | |
| 1619 | core::core_arch::arm_shared::neon::generated | vld1_u64_x3 | function | * Neon intrinsic unsafe | |
| 1620 | core::core_arch::arm_shared::neon::generated | vld1_u64_x4 | function | * Neon intrinsic unsafe | |
| 1621 | core::core_arch::arm_shared::neon::generated | vld1_u8_x2 | function | * Neon intrinsic unsafe | |
| 1622 | core::core_arch::arm_shared::neon::generated | vld1_u8_x3 | function | * Neon intrinsic unsafe | |
| 1623 | core::core_arch::arm_shared::neon::generated | vld1_u8_x4 | function | * Neon intrinsic unsafe | |
| 1624 | core::core_arch::arm_shared::neon::generated | vld1q_dup_f16 | function | * Neon intrinsic unsafe | |
| 1625 | core::core_arch::arm_shared::neon::generated | vld1q_dup_f32 | function | * Neon intrinsic unsafe | |
| 1626 | core::core_arch::arm_shared::neon::generated | vld1q_dup_p16 | function | * Neon intrinsic unsafe | |
| 1627 | core::core_arch::arm_shared::neon::generated | vld1q_dup_p64 | function | * Neon intrinsic unsafe | |
| 1628 | core::core_arch::arm_shared::neon::generated | vld1q_dup_p8 | function | * Neon intrinsic unsafe | |
| 1629 | core::core_arch::arm_shared::neon::generated | vld1q_dup_s16 | function | * Neon intrinsic unsafe | |
| 1630 | core::core_arch::arm_shared::neon::generated | vld1q_dup_s32 | function | * Neon intrinsic unsafe | |
| 1631 | core::core_arch::arm_shared::neon::generated | vld1q_dup_s64 | function | * Neon intrinsic unsafe | |
| 1632 | core::core_arch::arm_shared::neon::generated | vld1q_dup_s8 | function | * Neon intrinsic unsafe | |
| 1633 | core::core_arch::arm_shared::neon::generated | vld1q_dup_u16 | function | * Neon intrinsic unsafe | |
| 1634 | core::core_arch::arm_shared::neon::generated | vld1q_dup_u32 | function | * Neon intrinsic unsafe | |
| 1635 | core::core_arch::arm_shared::neon::generated | vld1q_dup_u64 | function | * Neon intrinsic unsafe | |
| 1636 | core::core_arch::arm_shared::neon::generated | vld1q_dup_u8 | function | * Neon intrinsic unsafe | |
| 1637 | core::core_arch::arm_shared::neon::generated | vld1q_f16_x2 | function | * Neon intrinsic unsafe | |
| 1638 | core::core_arch::arm_shared::neon::generated | vld1q_f16_x3 | function | * Neon intrinsic unsafe | |
| 1639 | core::core_arch::arm_shared::neon::generated | vld1q_f16_x4 | function | * Neon intrinsic unsafe | |
| 1640 | core::core_arch::arm_shared::neon::generated | vld1q_f32_x2 | function | * Neon intrinsic unsafe | |
| 1641 | core::core_arch::arm_shared::neon::generated | vld1q_f32_x3 | function | * Neon intrinsic unsafe | |
| 1642 | core::core_arch::arm_shared::neon::generated | vld1q_f32_x4 | function | * Neon intrinsic unsafe | |
| 1643 | core::core_arch::arm_shared::neon::generated | vld1q_lane_f16 | function | * Neon intrinsic unsafe | |
| 1644 | core::core_arch::arm_shared::neon::generated | vld1q_lane_f32 | function | * Neon intrinsic unsafe | |
| 1645 | core::core_arch::arm_shared::neon::generated | vld1q_lane_p16 | function | * Neon intrinsic unsafe | |
| 1646 | core::core_arch::arm_shared::neon::generated | vld1q_lane_p64 | function | * Neon intrinsic unsafe | |
| 1647 | core::core_arch::arm_shared::neon::generated | vld1q_lane_p8 | function | * Neon intrinsic unsafe | |
| 1648 | core::core_arch::arm_shared::neon::generated | vld1q_lane_s16 | function | * Neon intrinsic unsafe | |
| 1649 | core::core_arch::arm_shared::neon::generated | vld1q_lane_s32 | function | * Neon intrinsic unsafe | |
| 1650 | core::core_arch::arm_shared::neon::generated | vld1q_lane_s64 | function | * Neon intrinsic unsafe | |
| 1651 | core::core_arch::arm_shared::neon::generated | vld1q_lane_s8 | function | * Neon intrinsic unsafe | |
| 1652 | core::core_arch::arm_shared::neon::generated | vld1q_lane_u16 | function | * Neon intrinsic unsafe | |
| 1653 | core::core_arch::arm_shared::neon::generated | vld1q_lane_u32 | function | * Neon intrinsic unsafe | |
| 1654 | core::core_arch::arm_shared::neon::generated | vld1q_lane_u64 | function | * Neon intrinsic unsafe | |
| 1655 | core::core_arch::arm_shared::neon::generated | vld1q_lane_u8 | function | * Neon intrinsic unsafe | |
| 1656 | core::core_arch::arm_shared::neon::generated | vld1q_p16_x2 | function | * Neon intrinsic unsafe | |
| 1657 | core::core_arch::arm_shared::neon::generated | vld1q_p16_x3 | function | * Neon intrinsic unsafe | |
| 1658 | core::core_arch::arm_shared::neon::generated | vld1q_p16_x4 | function | * Neon intrinsic unsafe | |
| 1659 | core::core_arch::arm_shared::neon::generated | vld1q_p64_x2 | function | * Neon intrinsic unsafe | |
| 1660 | core::core_arch::arm_shared::neon::generated | vld1q_p64_x3 | function | * Neon intrinsic unsafe | |
| 1661 | core::core_arch::arm_shared::neon::generated | vld1q_p64_x4 | function | * Neon intrinsic unsafe | |
| 1662 | core::core_arch::arm_shared::neon::generated | vld1q_p8_x2 | function | * Neon intrinsic unsafe | |
| 1663 | core::core_arch::arm_shared::neon::generated | vld1q_p8_x3 | function | * Neon intrinsic unsafe | |
| 1664 | core::core_arch::arm_shared::neon::generated | vld1q_p8_x4 | function | * Neon intrinsic unsafe | |
| 1665 | core::core_arch::arm_shared::neon::generated | vld1q_s16_x2 | function | * Neon intrinsic unsafe | |
| 1666 | core::core_arch::arm_shared::neon::generated | vld1q_s16_x3 | function | * Neon intrinsic unsafe | |
| 1667 | core::core_arch::arm_shared::neon::generated | vld1q_s16_x4 | function | * Neon intrinsic unsafe | |
| 1668 | core::core_arch::arm_shared::neon::generated | vld1q_s32_x2 | function | * Neon intrinsic unsafe | |
| 1669 | core::core_arch::arm_shared::neon::generated | vld1q_s32_x3 | function | * Neon intrinsic unsafe | |
| 1670 | core::core_arch::arm_shared::neon::generated | vld1q_s32_x4 | function | * Neon intrinsic unsafe | |
| 1671 | core::core_arch::arm_shared::neon::generated | vld1q_s64_x2 | function | * Neon intrinsic unsafe | |
| 1672 | core::core_arch::arm_shared::neon::generated | vld1q_s64_x3 | function | * Neon intrinsic unsafe | |
| 1673 | core::core_arch::arm_shared::neon::generated | vld1q_s64_x4 | function | * Neon intrinsic unsafe | |
| 1674 | core::core_arch::arm_shared::neon::generated | vld1q_s8_x2 | function | * Neon intrinsic unsafe | |
| 1675 | core::core_arch::arm_shared::neon::generated | vld1q_s8_x3 | function | * Neon intrinsic unsafe | |
| 1676 | core::core_arch::arm_shared::neon::generated | vld1q_s8_x4 | function | * Neon intrinsic unsafe | |
| 1677 | core::core_arch::arm_shared::neon::generated | vld1q_u16_x2 | function | * Neon intrinsic unsafe | |
| 1678 | core::core_arch::arm_shared::neon::generated | vld1q_u16_x3 | function | * Neon intrinsic unsafe | |
| 1679 | core::core_arch::arm_shared::neon::generated | vld1q_u16_x4 | function | * Neon intrinsic unsafe | |
| 1680 | core::core_arch::arm_shared::neon::generated | vld1q_u32_x2 | function | * Neon intrinsic unsafe | |
| 1681 | core::core_arch::arm_shared::neon::generated | vld1q_u32_x3 | function | * Neon intrinsic unsafe | |
| 1682 | core::core_arch::arm_shared::neon::generated | vld1q_u32_x4 | function | * Neon intrinsic unsafe | |
| 1683 | core::core_arch::arm_shared::neon::generated | vld1q_u64_x2 | function | * Neon intrinsic unsafe | |
| 1684 | core::core_arch::arm_shared::neon::generated | vld1q_u64_x3 | function | * Neon intrinsic unsafe | |
| 1685 | core::core_arch::arm_shared::neon::generated | vld1q_u64_x4 | function | * Neon intrinsic unsafe | |
| 1686 | core::core_arch::arm_shared::neon::generated | vld1q_u8_x2 | function | * Neon intrinsic unsafe | |
| 1687 | core::core_arch::arm_shared::neon::generated | vld1q_u8_x3 | function | * Neon intrinsic unsafe | |
| 1688 | core::core_arch::arm_shared::neon::generated | vld1q_u8_x4 | function | * Neon intrinsic unsafe | |
| 1689 | core::core_arch::arm_shared::neon::generated | vld2_dup_f16 | function | * Neon intrinsic unsafe | |
| 1690 | core::core_arch::arm_shared::neon::generated | vld2_dup_f32 | function | * Neon intrinsic unsafe | |
| 1691 | core::core_arch::arm_shared::neon::generated | vld2_dup_p16 | function | * Neon intrinsic unsafe | |
| 1692 | core::core_arch::arm_shared::neon::generated | vld2_dup_p64 | function | * Neon intrinsic unsafe | |
| 1693 | core::core_arch::arm_shared::neon::generated | vld2_dup_p8 | function | * Neon intrinsic unsafe | |
| 1694 | core::core_arch::arm_shared::neon::generated | vld2_dup_s16 | function | * Neon intrinsic unsafe | |
| 1695 | core::core_arch::arm_shared::neon::generated | vld2_dup_s32 | function | * Neon intrinsic unsafe | |
| 1696 | core::core_arch::arm_shared::neon::generated | vld2_dup_s64 | function | * Neon intrinsic unsafe | |
| 1697 | core::core_arch::arm_shared::neon::generated | vld2_dup_s8 | function | * Neon intrinsic unsafe | |
| 1698 | core::core_arch::arm_shared::neon::generated | vld2_dup_u16 | function | * Neon intrinsic unsafe | |
| 1699 | core::core_arch::arm_shared::neon::generated | vld2_dup_u32 | function | * Neon intrinsic unsafe | |
| 1700 | core::core_arch::arm_shared::neon::generated | vld2_dup_u64 | function | * Neon intrinsic unsafe | |
| 1701 | core::core_arch::arm_shared::neon::generated | vld2_dup_u8 | function | * Neon intrinsic unsafe | |
| 1702 | core::core_arch::arm_shared::neon::generated | vld2_f16 | function | * Neon intrinsic unsafe | |
| 1703 | core::core_arch::arm_shared::neon::generated | vld2_f32 | function | * Neon intrinsic unsafe | |
| 1704 | core::core_arch::arm_shared::neon::generated | vld2_lane_f16 | function | * Neon intrinsic unsafe | |
| 1705 | core::core_arch::arm_shared::neon::generated | vld2_lane_f32 | function | * Neon intrinsic unsafe | |
| 1706 | core::core_arch::arm_shared::neon::generated | vld2_lane_p16 | function | * Neon intrinsic unsafe | |
| 1707 | core::core_arch::arm_shared::neon::generated | vld2_lane_p8 | function | * Neon intrinsic unsafe | |
| 1708 | core::core_arch::arm_shared::neon::generated | vld2_lane_s16 | function | * Neon intrinsic unsafe | |
| 1709 | core::core_arch::arm_shared::neon::generated | vld2_lane_s32 | function | * Neon intrinsic unsafe | |
| 1710 | core::core_arch::arm_shared::neon::generated | vld2_lane_s8 | function | * Neon intrinsic unsafe | |
| 1711 | core::core_arch::arm_shared::neon::generated | vld2_lane_u16 | function | * Neon intrinsic unsafe | |
| 1712 | core::core_arch::arm_shared::neon::generated | vld2_lane_u32 | function | * Neon intrinsic unsafe | |
| 1713 | core::core_arch::arm_shared::neon::generated | vld2_lane_u8 | function | * Neon intrinsic unsafe | |
| 1714 | core::core_arch::arm_shared::neon::generated | vld2_p16 | function | * Neon intrinsic unsafe | |
| 1715 | core::core_arch::arm_shared::neon::generated | vld2_p64 | function | * Neon intrinsic unsafe | |
| 1716 | core::core_arch::arm_shared::neon::generated | vld2_p8 | function | * Neon intrinsic unsafe | |
| 1717 | core::core_arch::arm_shared::neon::generated | vld2_s16 | function | * Neon intrinsic unsafe | |
| 1718 | core::core_arch::arm_shared::neon::generated | vld2_s32 | function | * Neon intrinsic unsafe | |
| 1719 | core::core_arch::arm_shared::neon::generated | vld2_s64 | function | * Neon intrinsic unsafe | |
| 1720 | core::core_arch::arm_shared::neon::generated | vld2_s8 | function | * Neon intrinsic unsafe | |
| 1721 | core::core_arch::arm_shared::neon::generated | vld2_u16 | function | * Neon intrinsic unsafe | |
| 1722 | core::core_arch::arm_shared::neon::generated | vld2_u32 | function | * Neon intrinsic unsafe | |
| 1723 | core::core_arch::arm_shared::neon::generated | vld2_u64 | function | * Neon intrinsic unsafe | |
| 1724 | core::core_arch::arm_shared::neon::generated | vld2_u8 | function | * Neon intrinsic unsafe | |
| 1725 | core::core_arch::arm_shared::neon::generated | vld2q_dup_f16 | function | * Neon intrinsic unsafe | |
| 1726 | core::core_arch::arm_shared::neon::generated | vld2q_dup_f32 | function | * Neon intrinsic unsafe | |
| 1727 | core::core_arch::arm_shared::neon::generated | vld2q_dup_p16 | function | * Neon intrinsic unsafe | |
| 1728 | core::core_arch::arm_shared::neon::generated | vld2q_dup_p8 | function | * Neon intrinsic unsafe | |
| 1729 | core::core_arch::arm_shared::neon::generated | vld2q_dup_s16 | function | * Neon intrinsic unsafe | |
| 1730 | core::core_arch::arm_shared::neon::generated | vld2q_dup_s32 | function | * Neon intrinsic unsafe | |
| 1731 | core::core_arch::arm_shared::neon::generated | vld2q_dup_s8 | function | * Neon intrinsic unsafe | |
| 1732 | core::core_arch::arm_shared::neon::generated | vld2q_dup_u16 | function | * Neon intrinsic unsafe | |
| 1733 | core::core_arch::arm_shared::neon::generated | vld2q_dup_u32 | function | * Neon intrinsic unsafe | |
| 1734 | core::core_arch::arm_shared::neon::generated | vld2q_dup_u8 | function | * Neon intrinsic unsafe | |
| 1735 | core::core_arch::arm_shared::neon::generated | vld2q_f16 | function | * Neon intrinsic unsafe | |
| 1736 | core::core_arch::arm_shared::neon::generated | vld2q_f32 | function | * Neon intrinsic unsafe | |
| 1737 | core::core_arch::arm_shared::neon::generated | vld2q_lane_f16 | function | * Neon intrinsic unsafe | |
| 1738 | core::core_arch::arm_shared::neon::generated | vld2q_lane_f32 | function | * Neon intrinsic unsafe | |
| 1739 | core::core_arch::arm_shared::neon::generated | vld2q_lane_p16 | function | * Neon intrinsic unsafe | |
| 1740 | core::core_arch::arm_shared::neon::generated | vld2q_lane_s16 | function | * Neon intrinsic unsafe | |
| 1741 | core::core_arch::arm_shared::neon::generated | vld2q_lane_s32 | function | * Neon intrinsic unsafe | |
| 1742 | core::core_arch::arm_shared::neon::generated | vld2q_lane_u16 | function | * Neon intrinsic unsafe | |
| 1743 | core::core_arch::arm_shared::neon::generated | vld2q_lane_u32 | function | * Neon intrinsic unsafe | |
| 1744 | core::core_arch::arm_shared::neon::generated | vld2q_p16 | function | * Neon intrinsic unsafe | |
| 1745 | core::core_arch::arm_shared::neon::generated | vld2q_p8 | function | * Neon intrinsic unsafe | |
| 1746 | core::core_arch::arm_shared::neon::generated | vld2q_s16 | function | * Neon intrinsic unsafe | |
| 1747 | core::core_arch::arm_shared::neon::generated | vld2q_s32 | function | * Neon intrinsic unsafe | |
| 1748 | core::core_arch::arm_shared::neon::generated | vld2q_s8 | function | * Neon intrinsic unsafe | |
| 1749 | core::core_arch::arm_shared::neon::generated | vld2q_u16 | function | * Neon intrinsic unsafe | |
| 1750 | core::core_arch::arm_shared::neon::generated | vld2q_u32 | function | * Neon intrinsic unsafe | |
| 1751 | core::core_arch::arm_shared::neon::generated | vld2q_u8 | function | * Neon intrinsic unsafe | |
| 1752 | core::core_arch::arm_shared::neon::generated | vld3_dup_f16 | function | * Neon intrinsic unsafe | |
| 1753 | core::core_arch::arm_shared::neon::generated | vld3_dup_f32 | function | * Neon intrinsic unsafe | |
| 1754 | core::core_arch::arm_shared::neon::generated | vld3_dup_p16 | function | * Neon intrinsic unsafe | |
| 1755 | core::core_arch::arm_shared::neon::generated | vld3_dup_p64 | function | * Neon intrinsic unsafe | |
| 1756 | core::core_arch::arm_shared::neon::generated | vld3_dup_p8 | function | * Neon intrinsic unsafe | |
| 1757 | core::core_arch::arm_shared::neon::generated | vld3_dup_s16 | function | * Neon intrinsic unsafe | |
| 1758 | core::core_arch::arm_shared::neon::generated | vld3_dup_s32 | function | * Neon intrinsic unsafe | |
| 1759 | core::core_arch::arm_shared::neon::generated | vld3_dup_s64 | function | * Neon intrinsic unsafe | |
| 1760 | core::core_arch::arm_shared::neon::generated | vld3_dup_s8 | function | * Neon intrinsic unsafe | |
| 1761 | core::core_arch::arm_shared::neon::generated | vld3_dup_u16 | function | * Neon intrinsic unsafe | |
| 1762 | core::core_arch::arm_shared::neon::generated | vld3_dup_u32 | function | * Neon intrinsic unsafe | |
| 1763 | core::core_arch::arm_shared::neon::generated | vld3_dup_u64 | function | * Neon intrinsic unsafe | |
| 1764 | core::core_arch::arm_shared::neon::generated | vld3_dup_u8 | function | * Neon intrinsic unsafe | |
| 1765 | core::core_arch::arm_shared::neon::generated | vld3_f16 | function | * Neon intrinsic unsafe | |
| 1766 | core::core_arch::arm_shared::neon::generated | vld3_f32 | function | * Neon intrinsic unsafe | |
| 1767 | core::core_arch::arm_shared::neon::generated | vld3_lane_f16 | function | * Neon intrinsic unsafe | |
| 1768 | core::core_arch::arm_shared::neon::generated | vld3_lane_f32 | function | * Neon intrinsic unsafe | |
| 1769 | core::core_arch::arm_shared::neon::generated | vld3_lane_p16 | function | * Neon intrinsic unsafe | |
| 1770 | core::core_arch::arm_shared::neon::generated | vld3_lane_p8 | function | * Neon intrinsic unsafe | |
| 1771 | core::core_arch::arm_shared::neon::generated | vld3_lane_s16 | function | * Neon intrinsic unsafe | |
| 1772 | core::core_arch::arm_shared::neon::generated | vld3_lane_s32 | function | * Neon intrinsic unsafe | |
| 1773 | core::core_arch::arm_shared::neon::generated | vld3_lane_s8 | function | * Neon intrinsic unsafe | |
| 1774 | core::core_arch::arm_shared::neon::generated | vld3_lane_u16 | function | * Neon intrinsic unsafe | |
| 1775 | core::core_arch::arm_shared::neon::generated | vld3_lane_u32 | function | * Neon intrinsic unsafe | |
| 1776 | core::core_arch::arm_shared::neon::generated | vld3_lane_u8 | function | * Neon intrinsic unsafe | |
| 1777 | core::core_arch::arm_shared::neon::generated | vld3_p16 | function | * Neon intrinsic unsafe | |
| 1778 | core::core_arch::arm_shared::neon::generated | vld3_p64 | function | * Neon intrinsic unsafe | |
| 1779 | core::core_arch::arm_shared::neon::generated | vld3_p8 | function | * Neon intrinsic unsafe | |
| 1780 | core::core_arch::arm_shared::neon::generated | vld3_s16 | function | * Neon intrinsic unsafe | |
| 1781 | core::core_arch::arm_shared::neon::generated | vld3_s32 | function | * Neon intrinsic unsafe | |
| 1782 | core::core_arch::arm_shared::neon::generated | vld3_s64 | function | * Neon intrinsic unsafe | |
| 1783 | core::core_arch::arm_shared::neon::generated | vld3_s8 | function | * Neon intrinsic unsafe | |
| 1784 | core::core_arch::arm_shared::neon::generated | vld3_u16 | function | * Neon intrinsic unsafe | |
| 1785 | core::core_arch::arm_shared::neon::generated | vld3_u32 | function | * Neon intrinsic unsafe | |
| 1786 | core::core_arch::arm_shared::neon::generated | vld3_u64 | function | * Neon intrinsic unsafe | |
| 1787 | core::core_arch::arm_shared::neon::generated | vld3_u8 | function | * Neon intrinsic unsafe | |
| 1788 | core::core_arch::arm_shared::neon::generated | vld3q_dup_f16 | function | * Neon intrinsic unsafe | |
| 1789 | core::core_arch::arm_shared::neon::generated | vld3q_dup_f32 | function | * Neon intrinsic unsafe | |
| 1790 | core::core_arch::arm_shared::neon::generated | vld3q_dup_p16 | function | * Neon intrinsic unsafe | |
| 1791 | core::core_arch::arm_shared::neon::generated | vld3q_dup_p8 | function | * Neon intrinsic unsafe | |
| 1792 | core::core_arch::arm_shared::neon::generated | vld3q_dup_s16 | function | * Neon intrinsic unsafe | |
| 1793 | core::core_arch::arm_shared::neon::generated | vld3q_dup_s32 | function | * Neon intrinsic unsafe | |
| 1794 | core::core_arch::arm_shared::neon::generated | vld3q_dup_s8 | function | * Neon intrinsic unsafe | |
| 1795 | core::core_arch::arm_shared::neon::generated | vld3q_dup_u16 | function | * Neon intrinsic unsafe | |
| 1796 | core::core_arch::arm_shared::neon::generated | vld3q_dup_u32 | function | * Neon intrinsic unsafe | |
| 1797 | core::core_arch::arm_shared::neon::generated | vld3q_dup_u8 | function | * Neon intrinsic unsafe | |
| 1798 | core::core_arch::arm_shared::neon::generated | vld3q_f16 | function | * Neon intrinsic unsafe | |
| 1799 | core::core_arch::arm_shared::neon::generated | vld3q_f32 | function | * Neon intrinsic unsafe | |
| 1800 | core::core_arch::arm_shared::neon::generated | vld3q_lane_f16 | function | * Neon intrinsic unsafe | |
| 1801 | core::core_arch::arm_shared::neon::generated | vld3q_lane_f32 | function | * Neon intrinsic unsafe | |
| 1802 | core::core_arch::arm_shared::neon::generated | vld3q_lane_p16 | function | * Neon intrinsic unsafe | |
| 1803 | core::core_arch::arm_shared::neon::generated | vld3q_lane_s16 | function | * Neon intrinsic unsafe | |
| 1804 | core::core_arch::arm_shared::neon::generated | vld3q_lane_s32 | function | * Neon intrinsic unsafe | |
| 1805 | core::core_arch::arm_shared::neon::generated | vld3q_lane_u16 | function | * Neon intrinsic unsafe | |
| 1806 | core::core_arch::arm_shared::neon::generated | vld3q_lane_u32 | function | * Neon intrinsic unsafe | |
| 1807 | core::core_arch::arm_shared::neon::generated | vld3q_p16 | function | * Neon intrinsic unsafe | |
| 1808 | core::core_arch::arm_shared::neon::generated | vld3q_p8 | function | * Neon intrinsic unsafe | |
| 1809 | core::core_arch::arm_shared::neon::generated | vld3q_s16 | function | * Neon intrinsic unsafe | |
| 1810 | core::core_arch::arm_shared::neon::generated | vld3q_s32 | function | * Neon intrinsic unsafe | |
| 1811 | core::core_arch::arm_shared::neon::generated | vld3q_s8 | function | * Neon intrinsic unsafe | |
| 1812 | core::core_arch::arm_shared::neon::generated | vld3q_u16 | function | * Neon intrinsic unsafe | |
| 1813 | core::core_arch::arm_shared::neon::generated | vld3q_u32 | function | * Neon intrinsic unsafe | |
| 1814 | core::core_arch::arm_shared::neon::generated | vld3q_u8 | function | * Neon intrinsic unsafe | |
| 1815 | core::core_arch::arm_shared::neon::generated | vld4_dup_f16 | function | * Neon intrinsic unsafe | |
| 1816 | core::core_arch::arm_shared::neon::generated | vld4_dup_f32 | function | * Neon intrinsic unsafe | |
| 1817 | core::core_arch::arm_shared::neon::generated | vld4_dup_p16 | function | * Neon intrinsic unsafe | |
| 1818 | core::core_arch::arm_shared::neon::generated | vld4_dup_p64 | function | * Neon intrinsic unsafe | |
| 1819 | core::core_arch::arm_shared::neon::generated | vld4_dup_p8 | function | * Neon intrinsic unsafe | |
| 1820 | core::core_arch::arm_shared::neon::generated | vld4_dup_s16 | function | * Neon intrinsic unsafe | |
| 1821 | core::core_arch::arm_shared::neon::generated | vld4_dup_s32 | function | * Neon intrinsic unsafe | |
| 1822 | core::core_arch::arm_shared::neon::generated | vld4_dup_s64 | function | * Neon intrinsic unsafe | |
| 1823 | core::core_arch::arm_shared::neon::generated | vld4_dup_s8 | function | * Neon intrinsic unsafe | |
| 1824 | core::core_arch::arm_shared::neon::generated | vld4_dup_u16 | function | * Neon intrinsic unsafe | |
| 1825 | core::core_arch::arm_shared::neon::generated | vld4_dup_u32 | function | * Neon intrinsic unsafe | |
| 1826 | core::core_arch::arm_shared::neon::generated | vld4_dup_u64 | function | * Neon intrinsic unsafe | |
| 1827 | core::core_arch::arm_shared::neon::generated | vld4_dup_u8 | function | * Neon intrinsic unsafe | |
| 1828 | core::core_arch::arm_shared::neon::generated | vld4_f16 | function | * Neon intrinsic unsafe | |
| 1829 | core::core_arch::arm_shared::neon::generated | vld4_f32 | function | * Neon intrinsic unsafe | |
| 1830 | core::core_arch::arm_shared::neon::generated | vld4_lane_f16 | function | * Neon intrinsic unsafe | |
| 1831 | core::core_arch::arm_shared::neon::generated | vld4_lane_f32 | function | * Neon intrinsic unsafe | |
| 1832 | core::core_arch::arm_shared::neon::generated | vld4_lane_p16 | function | * Neon intrinsic unsafe | |
| 1833 | core::core_arch::arm_shared::neon::generated | vld4_lane_p8 | function | * Neon intrinsic unsafe | |
| 1834 | core::core_arch::arm_shared::neon::generated | vld4_lane_s16 | function | * Neon intrinsic unsafe | |
| 1835 | core::core_arch::arm_shared::neon::generated | vld4_lane_s32 | function | * Neon intrinsic unsafe | |
| 1836 | core::core_arch::arm_shared::neon::generated | vld4_lane_s8 | function | * Neon intrinsic unsafe | |
| 1837 | core::core_arch::arm_shared::neon::generated | vld4_lane_u16 | function | * Neon intrinsic unsafe | |
| 1838 | core::core_arch::arm_shared::neon::generated | vld4_lane_u32 | function | * Neon intrinsic unsafe | |
| 1839 | core::core_arch::arm_shared::neon::generated | vld4_lane_u8 | function | * Neon intrinsic unsafe | |
| 1840 | core::core_arch::arm_shared::neon::generated | vld4_p16 | function | * Neon intrinsic unsafe | |
| 1841 | core::core_arch::arm_shared::neon::generated | vld4_p64 | function | * Neon intrinsic unsafe | |
| 1842 | core::core_arch::arm_shared::neon::generated | vld4_p8 | function | * Neon intrinsic unsafe | |
| 1843 | core::core_arch::arm_shared::neon::generated | vld4_s16 | function | * Neon intrinsic unsafe | |
| 1844 | core::core_arch::arm_shared::neon::generated | vld4_s32 | function | * Neon intrinsic unsafe | |
| 1845 | core::core_arch::arm_shared::neon::generated | vld4_s64 | function | * Neon intrinsic unsafe | |
| 1846 | core::core_arch::arm_shared::neon::generated | vld4_s8 | function | * Neon intrinsic unsafe | |
| 1847 | core::core_arch::arm_shared::neon::generated | vld4_u16 | function | * Neon intrinsic unsafe | |
| 1848 | core::core_arch::arm_shared::neon::generated | vld4_u32 | function | * Neon intrinsic unsafe | |
| 1849 | core::core_arch::arm_shared::neon::generated | vld4_u64 | function | * Neon intrinsic unsafe | |
| 1850 | core::core_arch::arm_shared::neon::generated | vld4_u8 | function | * Neon intrinsic unsafe | |
| 1851 | core::core_arch::arm_shared::neon::generated | vld4q_dup_f16 | function | * Neon intrinsic unsafe | |
| 1852 | core::core_arch::arm_shared::neon::generated | vld4q_dup_f32 | function | * Neon intrinsic unsafe | |
| 1853 | core::core_arch::arm_shared::neon::generated | vld4q_dup_p16 | function | * Neon intrinsic unsafe | |
| 1854 | core::core_arch::arm_shared::neon::generated | vld4q_dup_p8 | function | * Neon intrinsic unsafe | |
| 1855 | core::core_arch::arm_shared::neon::generated | vld4q_dup_s16 | function | * Neon intrinsic unsafe | |
| 1856 | core::core_arch::arm_shared::neon::generated | vld4q_dup_s32 | function | * Neon intrinsic unsafe | |
| 1857 | core::core_arch::arm_shared::neon::generated | vld4q_dup_s8 | function | * Neon intrinsic unsafe | |
| 1858 | core::core_arch::arm_shared::neon::generated | vld4q_dup_u16 | function | * Neon intrinsic unsafe | |
| 1859 | core::core_arch::arm_shared::neon::generated | vld4q_dup_u32 | function | * Neon intrinsic unsafe | |
| 1860 | core::core_arch::arm_shared::neon::generated | vld4q_dup_u8 | function | * Neon intrinsic unsafe | |
| 1861 | core::core_arch::arm_shared::neon::generated | vld4q_f16 | function | * Neon intrinsic unsafe | |
| 1862 | core::core_arch::arm_shared::neon::generated | vld4q_f32 | function | * Neon intrinsic unsafe | |
| 1863 | core::core_arch::arm_shared::neon::generated | vld4q_lane_f16 | function | * Neon intrinsic unsafe | |
| 1864 | core::core_arch::arm_shared::neon::generated | vld4q_lane_f32 | function | * Neon intrinsic unsafe | |
| 1865 | core::core_arch::arm_shared::neon::generated | vld4q_lane_p16 | function | * Neon intrinsic unsafe | |
| 1866 | core::core_arch::arm_shared::neon::generated | vld4q_lane_s16 | function | * Neon intrinsic unsafe | |
| 1867 | core::core_arch::arm_shared::neon::generated | vld4q_lane_s32 | function | * Neon intrinsic unsafe | |
| 1868 | core::core_arch::arm_shared::neon::generated | vld4q_lane_u16 | function | * Neon intrinsic unsafe | |
| 1869 | core::core_arch::arm_shared::neon::generated | vld4q_lane_u32 | function | * Neon intrinsic unsafe | |
| 1870 | core::core_arch::arm_shared::neon::generated | vld4q_p16 | function | * Neon intrinsic unsafe | |
| 1871 | core::core_arch::arm_shared::neon::generated | vld4q_p8 | function | * Neon intrinsic unsafe | |
| 1872 | core::core_arch::arm_shared::neon::generated | vld4q_s16 | function | * Neon intrinsic unsafe | |
| 1873 | core::core_arch::arm_shared::neon::generated | vld4q_s32 | function | * Neon intrinsic unsafe | |
| 1874 | core::core_arch::arm_shared::neon::generated | vld4q_s8 | function | * Neon intrinsic unsafe | |
| 1875 | core::core_arch::arm_shared::neon::generated | vld4q_u16 | function | * Neon intrinsic unsafe | |
| 1876 | core::core_arch::arm_shared::neon::generated | vld4q_u32 | function | * Neon intrinsic unsafe | |
| 1877 | core::core_arch::arm_shared::neon::generated | vld4q_u8 | function | * Neon intrinsic unsafe | |
| 1878 | core::core_arch::arm_shared::neon::generated | vldrq_p128 | function | * Neon intrinsic unsafe | |
| 1879 | core::core_arch::arm_shared::neon::generated | vst1_f16_x2 | function | * Neon intrinsic unsafe | |
| 1880 | core::core_arch::arm_shared::neon::generated | vst1_f16_x3 | function | * Neon intrinsic unsafe | |
| 1881 | core::core_arch::arm_shared::neon::generated | vst1_f16_x4 | function | * Neon intrinsic unsafe | |
| 1882 | core::core_arch::arm_shared::neon::generated | vst1_f32_x2 | function | * Neon intrinsic unsafe | |
| 1883 | core::core_arch::arm_shared::neon::generated | vst1_f32_x3 | function | * Neon intrinsic unsafe | |
| 1884 | core::core_arch::arm_shared::neon::generated | vst1_f32_x4 | function | * Neon intrinsic unsafe | |
| 1885 | core::core_arch::arm_shared::neon::generated | vst1_lane_f16 | function | * Neon intrinsic unsafe | |
| 1886 | core::core_arch::arm_shared::neon::generated | vst1_lane_f32 | function | * Neon intrinsic unsafe | |
| 1887 | core::core_arch::arm_shared::neon::generated | vst1_lane_p16 | function | * Neon intrinsic unsafe | |
| 1888 | core::core_arch::arm_shared::neon::generated | vst1_lane_p64 | function | * Neon intrinsic unsafe | |
| 1889 | core::core_arch::arm_shared::neon::generated | vst1_lane_p8 | function | * Neon intrinsic unsafe | |
| 1890 | core::core_arch::arm_shared::neon::generated | vst1_lane_s16 | function | * Neon intrinsic unsafe | |
| 1891 | core::core_arch::arm_shared::neon::generated | vst1_lane_s32 | function | * Neon intrinsic unsafe | |
| 1892 | core::core_arch::arm_shared::neon::generated | vst1_lane_s64 | function | * Neon intrinsic unsafe | |
| 1893 | core::core_arch::arm_shared::neon::generated | vst1_lane_s8 | function | * Neon intrinsic unsafe | |
| 1894 | core::core_arch::arm_shared::neon::generated | vst1_lane_u16 | function | * Neon intrinsic unsafe | |
| 1895 | core::core_arch::arm_shared::neon::generated | vst1_lane_u32 | function | * Neon intrinsic unsafe | |
| 1896 | core::core_arch::arm_shared::neon::generated | vst1_lane_u64 | function | * Neon intrinsic unsafe | |
| 1897 | core::core_arch::arm_shared::neon::generated | vst1_lane_u8 | function | * Neon intrinsic unsafe | |
| 1898 | core::core_arch::arm_shared::neon::generated | vst1_p16_x2 | function | * Neon intrinsic unsafe | |
| 1899 | core::core_arch::arm_shared::neon::generated | vst1_p16_x3 | function | * Neon intrinsic unsafe | |
| 1900 | core::core_arch::arm_shared::neon::generated | vst1_p16_x4 | function | * Neon intrinsic unsafe | |
| 1901 | core::core_arch::arm_shared::neon::generated | vst1_p64_x2 | function | * Neon intrinsic unsafe | |
| 1902 | core::core_arch::arm_shared::neon::generated | vst1_p64_x3 | function | * Neon intrinsic unsafe | |
| 1903 | core::core_arch::arm_shared::neon::generated | vst1_p64_x4 | function | * Neon intrinsic unsafe | |
| 1904 | core::core_arch::arm_shared::neon::generated | vst1_p8_x2 | function | * Neon intrinsic unsafe | |
| 1905 | core::core_arch::arm_shared::neon::generated | vst1_p8_x3 | function | * Neon intrinsic unsafe | |
| 1906 | core::core_arch::arm_shared::neon::generated | vst1_p8_x4 | function | * Neon intrinsic unsafe | |
| 1907 | core::core_arch::arm_shared::neon::generated | vst1_s16_x2 | function | * Neon intrinsic unsafe | |
| 1908 | core::core_arch::arm_shared::neon::generated | vst1_s16_x3 | function | * Neon intrinsic unsafe | |
| 1909 | core::core_arch::arm_shared::neon::generated | vst1_s16_x4 | function | * Neon intrinsic unsafe | |
| 1910 | core::core_arch::arm_shared::neon::generated | vst1_s32_x2 | function | * Neon intrinsic unsafe | |
| 1911 | core::core_arch::arm_shared::neon::generated | vst1_s32_x3 | function | * Neon intrinsic unsafe | |
| 1912 | core::core_arch::arm_shared::neon::generated | vst1_s32_x4 | function | * Neon intrinsic unsafe | |
| 1913 | core::core_arch::arm_shared::neon::generated | vst1_s64_x2 | function | * Neon intrinsic unsafe | |
| 1914 | core::core_arch::arm_shared::neon::generated | vst1_s64_x3 | function | * Neon intrinsic unsafe | |
| 1915 | core::core_arch::arm_shared::neon::generated | vst1_s64_x4 | function | * Neon intrinsic unsafe | |
| 1916 | core::core_arch::arm_shared::neon::generated | vst1_s8_x2 | function | * Neon intrinsic unsafe | |
| 1917 | core::core_arch::arm_shared::neon::generated | vst1_s8_x3 | function | * Neon intrinsic unsafe | |
| 1918 | core::core_arch::arm_shared::neon::generated | vst1_s8_x4 | function | * Neon intrinsic unsafe | |
| 1919 | core::core_arch::arm_shared::neon::generated | vst1_u16_x2 | function | * Neon intrinsic unsafe | |
| 1920 | core::core_arch::arm_shared::neon::generated | vst1_u16_x3 | function | * Neon intrinsic unsafe | |
| 1921 | core::core_arch::arm_shared::neon::generated | vst1_u16_x4 | function | * Neon intrinsic unsafe | |
| 1922 | core::core_arch::arm_shared::neon::generated | vst1_u32_x2 | function | * Neon intrinsic unsafe | |
| 1923 | core::core_arch::arm_shared::neon::generated | vst1_u32_x3 | function | * Neon intrinsic unsafe | |
| 1924 | core::core_arch::arm_shared::neon::generated | vst1_u32_x4 | function | * Neon intrinsic unsafe | |
| 1925 | core::core_arch::arm_shared::neon::generated | vst1_u64_x2 | function | * Neon intrinsic unsafe | |
| 1926 | core::core_arch::arm_shared::neon::generated | vst1_u64_x3 | function | * Neon intrinsic unsafe | |
| 1927 | core::core_arch::arm_shared::neon::generated | vst1_u64_x4 | function | * Neon intrinsic unsafe | |
| 1928 | core::core_arch::arm_shared::neon::generated | vst1_u8_x2 | function | * Neon intrinsic unsafe | |
| 1929 | core::core_arch::arm_shared::neon::generated | vst1_u8_x3 | function | * Neon intrinsic unsafe | |
| 1930 | core::core_arch::arm_shared::neon::generated | vst1_u8_x4 | function | * Neon intrinsic unsafe | |
| 1931 | core::core_arch::arm_shared::neon::generated | vst1q_f16_x2 | function | * Neon intrinsic unsafe | |
| 1932 | core::core_arch::arm_shared::neon::generated | vst1q_f16_x3 | function | * Neon intrinsic unsafe | |
| 1933 | core::core_arch::arm_shared::neon::generated | vst1q_f16_x4 | function | * Neon intrinsic unsafe | |
| 1934 | core::core_arch::arm_shared::neon::generated | vst1q_f32_x2 | function | * Neon intrinsic unsafe | |
| 1935 | core::core_arch::arm_shared::neon::generated | vst1q_f32_x3 | function | * Neon intrinsic unsafe | |
| 1936 | core::core_arch::arm_shared::neon::generated | vst1q_f32_x4 | function | * Neon intrinsic unsafe | |
| 1937 | core::core_arch::arm_shared::neon::generated | vst1q_lane_f16 | function | * Neon intrinsic unsafe | |
| 1938 | core::core_arch::arm_shared::neon::generated | vst1q_lane_f32 | function | * Neon intrinsic unsafe | |
| 1939 | core::core_arch::arm_shared::neon::generated | vst1q_lane_p16 | function | * Neon intrinsic unsafe | |
| 1940 | core::core_arch::arm_shared::neon::generated | vst1q_lane_p64 | function | * Neon intrinsic unsafe | |
| 1941 | core::core_arch::arm_shared::neon::generated | vst1q_lane_p8 | function | * Neon intrinsic unsafe | |
| 1942 | core::core_arch::arm_shared::neon::generated | vst1q_lane_s16 | function | * Neon intrinsic unsafe | |
| 1943 | core::core_arch::arm_shared::neon::generated | vst1q_lane_s32 | function | * Neon intrinsic unsafe | |
| 1944 | core::core_arch::arm_shared::neon::generated | vst1q_lane_s64 | function | * Neon intrinsic unsafe | |
| 1945 | core::core_arch::arm_shared::neon::generated | vst1q_lane_s8 | function | * Neon intrinsic unsafe | |
| 1946 | core::core_arch::arm_shared::neon::generated | vst1q_lane_u16 | function | * Neon intrinsic unsafe | |
| 1947 | core::core_arch::arm_shared::neon::generated | vst1q_lane_u32 | function | * Neon intrinsic unsafe | |
| 1948 | core::core_arch::arm_shared::neon::generated | vst1q_lane_u64 | function | * Neon intrinsic unsafe | |
| 1949 | core::core_arch::arm_shared::neon::generated | vst1q_lane_u8 | function | * Neon intrinsic unsafe | |
| 1950 | core::core_arch::arm_shared::neon::generated | vst1q_p16_x2 | function | * Neon intrinsic unsafe | |
| 1951 | core::core_arch::arm_shared::neon::generated | vst1q_p16_x3 | function | * Neon intrinsic unsafe | |
| 1952 | core::core_arch::arm_shared::neon::generated | vst1q_p16_x4 | function | * Neon intrinsic unsafe | |
| 1953 | core::core_arch::arm_shared::neon::generated | vst1q_p64_x2 | function | * Neon intrinsic unsafe | |
| 1954 | core::core_arch::arm_shared::neon::generated | vst1q_p64_x3 | function | * Neon intrinsic unsafe | |
| 1955 | core::core_arch::arm_shared::neon::generated | vst1q_p64_x4 | function | * Neon intrinsic unsafe | |
| 1956 | core::core_arch::arm_shared::neon::generated | vst1q_p8_x2 | function | * Neon intrinsic unsafe | |
| 1957 | core::core_arch::arm_shared::neon::generated | vst1q_p8_x3 | function | * Neon intrinsic unsafe | |
| 1958 | core::core_arch::arm_shared::neon::generated | vst1q_p8_x4 | function | * Neon intrinsic unsafe | |
| 1959 | core::core_arch::arm_shared::neon::generated | vst1q_s16_x2 | function | * Neon intrinsic unsafe | |
| 1960 | core::core_arch::arm_shared::neon::generated | vst1q_s16_x3 | function | * Neon intrinsic unsafe | |
| 1961 | core::core_arch::arm_shared::neon::generated | vst1q_s16_x4 | function | * Neon intrinsic unsafe | |
| 1962 | core::core_arch::arm_shared::neon::generated | vst1q_s32_x2 | function | * Neon intrinsic unsafe | |
| 1963 | core::core_arch::arm_shared::neon::generated | vst1q_s32_x3 | function | * Neon intrinsic unsafe | |
| 1964 | core::core_arch::arm_shared::neon::generated | vst1q_s32_x4 | function | * Neon intrinsic unsafe | |
| 1965 | core::core_arch::arm_shared::neon::generated | vst1q_s64_x2 | function | * Neon intrinsic unsafe | |
| 1966 | core::core_arch::arm_shared::neon::generated | vst1q_s64_x3 | function | * Neon intrinsic unsafe | |
| 1967 | core::core_arch::arm_shared::neon::generated | vst1q_s64_x4 | function | * Neon intrinsic unsafe | |
| 1968 | core::core_arch::arm_shared::neon::generated | vst1q_s8_x2 | function | * Neon intrinsic unsafe | |
| 1969 | core::core_arch::arm_shared::neon::generated | vst1q_s8_x3 | function | * Neon intrinsic unsafe | |
| 1970 | core::core_arch::arm_shared::neon::generated | vst1q_s8_x4 | function | * Neon intrinsic unsafe | |
| 1971 | core::core_arch::arm_shared::neon::generated | vst1q_u16_x2 | function | * Neon intrinsic unsafe | |
| 1972 | core::core_arch::arm_shared::neon::generated | vst1q_u16_x3 | function | * Neon intrinsic unsafe | |
| 1973 | core::core_arch::arm_shared::neon::generated | vst1q_u16_x4 | function | * Neon intrinsic unsafe | |
| 1974 | core::core_arch::arm_shared::neon::generated | vst1q_u32_x2 | function | * Neon intrinsic unsafe | |
| 1975 | core::core_arch::arm_shared::neon::generated | vst1q_u32_x3 | function | * Neon intrinsic unsafe | |
| 1976 | core::core_arch::arm_shared::neon::generated | vst1q_u32_x4 | function | * Neon intrinsic unsafe | |
| 1977 | core::core_arch::arm_shared::neon::generated | vst1q_u64_x2 | function | * Neon intrinsic unsafe | |
| 1978 | core::core_arch::arm_shared::neon::generated | vst1q_u64_x3 | function | * Neon intrinsic unsafe | |
| 1979 | core::core_arch::arm_shared::neon::generated | vst1q_u64_x4 | function | * Neon intrinsic unsafe | |
| 1980 | core::core_arch::arm_shared::neon::generated | vst1q_u8_x2 | function | * Neon intrinsic unsafe | |
| 1981 | core::core_arch::arm_shared::neon::generated | vst1q_u8_x3 | function | * Neon intrinsic unsafe | |
| 1982 | core::core_arch::arm_shared::neon::generated | vst1q_u8_x4 | function | * Neon intrinsic unsafe | |
| 1983 | core::core_arch::arm_shared::neon::generated | vst2_f16 | function | * Neon intrinsic unsafe | |
| 1984 | core::core_arch::arm_shared::neon::generated | vst2_f32 | function | * Neon intrinsic unsafe | |
| 1985 | core::core_arch::arm_shared::neon::generated | vst2_lane_f16 | function | * Neon intrinsic unsafe | |
| 1986 | core::core_arch::arm_shared::neon::generated | vst2_lane_f32 | function | * Neon intrinsic unsafe | |
| 1987 | core::core_arch::arm_shared::neon::generated | vst2_lane_p16 | function | * Neon intrinsic unsafe | |
| 1988 | core::core_arch::arm_shared::neon::generated | vst2_lane_p8 | function | * Neon intrinsic unsafe | |
| 1989 | core::core_arch::arm_shared::neon::generated | vst2_lane_s16 | function | * Neon intrinsic unsafe | |
| 1990 | core::core_arch::arm_shared::neon::generated | vst2_lane_s32 | function | * Neon intrinsic unsafe | |
| 1991 | core::core_arch::arm_shared::neon::generated | vst2_lane_s8 | function | * Neon intrinsic unsafe | |
| 1992 | core::core_arch::arm_shared::neon::generated | vst2_lane_u16 | function | * Neon intrinsic unsafe | |
| 1993 | core::core_arch::arm_shared::neon::generated | vst2_lane_u32 | function | * Neon intrinsic unsafe | |
| 1994 | core::core_arch::arm_shared::neon::generated | vst2_lane_u8 | function | * Neon intrinsic unsafe | |
| 1995 | core::core_arch::arm_shared::neon::generated | vst2_p16 | function | * Neon intrinsic unsafe | |
| 1996 | core::core_arch::arm_shared::neon::generated | vst2_p64 | function | * Neon intrinsic unsafe | |
| 1997 | core::core_arch::arm_shared::neon::generated | vst2_p8 | function | * Neon intrinsic unsafe | |
| 1998 | core::core_arch::arm_shared::neon::generated | vst2_s16 | function | * Neon intrinsic unsafe | |
| 1999 | core::core_arch::arm_shared::neon::generated | vst2_s32 | function | * Neon intrinsic unsafe | |
| 2000 | core::core_arch::arm_shared::neon::generated | vst2_s64 | function | * Neon intrinsic unsafe | |
| 2001 | core::core_arch::arm_shared::neon::generated | vst2_s8 | function | * Neon intrinsic unsafe | |
| 2002 | core::core_arch::arm_shared::neon::generated | vst2_u16 | function | * Neon intrinsic unsafe | |
| 2003 | core::core_arch::arm_shared::neon::generated | vst2_u32 | function | * Neon intrinsic unsafe | |
| 2004 | core::core_arch::arm_shared::neon::generated | vst2_u64 | function | * Neon intrinsic unsafe | |
| 2005 | core::core_arch::arm_shared::neon::generated | vst2_u8 | function | * Neon intrinsic unsafe | |
| 2006 | core::core_arch::arm_shared::neon::generated | vst2q_f16 | function | * Neon intrinsic unsafe | |
| 2007 | core::core_arch::arm_shared::neon::generated | vst2q_f32 | function | * Neon intrinsic unsafe | |
| 2008 | core::core_arch::arm_shared::neon::generated | vst2q_lane_f16 | function | * Neon intrinsic unsafe | |
| 2009 | core::core_arch::arm_shared::neon::generated | vst2q_lane_f32 | function | * Neon intrinsic unsafe | |
| 2010 | core::core_arch::arm_shared::neon::generated | vst2q_lane_p16 | function | * Neon intrinsic unsafe | |
| 2011 | core::core_arch::arm_shared::neon::generated | vst2q_lane_s16 | function | * Neon intrinsic unsafe | |
| 2012 | core::core_arch::arm_shared::neon::generated | vst2q_lane_s32 | function | * Neon intrinsic unsafe | |
| 2013 | core::core_arch::arm_shared::neon::generated | vst2q_lane_u16 | function | * Neon intrinsic unsafe | |
| 2014 | core::core_arch::arm_shared::neon::generated | vst2q_lane_u32 | function | * Neon intrinsic unsafe | |
| 2015 | core::core_arch::arm_shared::neon::generated | vst2q_p16 | function | * Neon intrinsic unsafe | |
| 2016 | core::core_arch::arm_shared::neon::generated | vst2q_p8 | function | * Neon intrinsic unsafe | |
| 2017 | core::core_arch::arm_shared::neon::generated | vst2q_s16 | function | * Neon intrinsic unsafe | |
| 2018 | core::core_arch::arm_shared::neon::generated | vst2q_s32 | function | * Neon intrinsic unsafe | |
| 2019 | core::core_arch::arm_shared::neon::generated | vst2q_s8 | function | * Neon intrinsic unsafe | |
| 2020 | core::core_arch::arm_shared::neon::generated | vst2q_u16 | function | * Neon intrinsic unsafe | |
| 2021 | core::core_arch::arm_shared::neon::generated | vst2q_u32 | function | * Neon intrinsic unsafe | |
| 2022 | core::core_arch::arm_shared::neon::generated | vst2q_u8 | function | * Neon intrinsic unsafe | |
| 2023 | core::core_arch::arm_shared::neon::generated | vst3_f16 | function | * Neon intrinsic unsafe | |
| 2024 | core::core_arch::arm_shared::neon::generated | vst3_f32 | function | * Neon intrinsic unsafe | |
| 2025 | core::core_arch::arm_shared::neon::generated | vst3_lane_f16 | function | * Neon intrinsic unsafe | |
| 2026 | core::core_arch::arm_shared::neon::generated | vst3_lane_f32 | function | * Neon intrinsic unsafe | |
| 2027 | core::core_arch::arm_shared::neon::generated | vst3_lane_p16 | function | * Neon intrinsic unsafe | |
| 2028 | core::core_arch::arm_shared::neon::generated | vst3_lane_p8 | function | * Neon intrinsic unsafe | |
| 2029 | core::core_arch::arm_shared::neon::generated | vst3_lane_s16 | function | * Neon intrinsic unsafe | |
| 2030 | core::core_arch::arm_shared::neon::generated | vst3_lane_s32 | function | * Neon intrinsic unsafe | |
| 2031 | core::core_arch::arm_shared::neon::generated | vst3_lane_s8 | function | * Neon intrinsic unsafe | |
| 2032 | core::core_arch::arm_shared::neon::generated | vst3_lane_u16 | function | * Neon intrinsic unsafe | |
| 2033 | core::core_arch::arm_shared::neon::generated | vst3_lane_u32 | function | * Neon intrinsic unsafe | |
| 2034 | core::core_arch::arm_shared::neon::generated | vst3_lane_u8 | function | * Neon intrinsic unsafe | |
| 2035 | core::core_arch::arm_shared::neon::generated | vst3_p16 | function | * Neon intrinsic unsafe | |
| 2036 | core::core_arch::arm_shared::neon::generated | vst3_p64 | function | * Neon intrinsic unsafe | |
| 2037 | core::core_arch::arm_shared::neon::generated | vst3_p8 | function | * Neon intrinsic unsafe | |
| 2038 | core::core_arch::arm_shared::neon::generated | vst3_s16 | function | * Neon intrinsic unsafe | |
| 2039 | core::core_arch::arm_shared::neon::generated | vst3_s32 | function | * Neon intrinsic unsafe | |
| 2040 | core::core_arch::arm_shared::neon::generated | vst3_s64 | function | * Neon intrinsic unsafe | |
| 2041 | core::core_arch::arm_shared::neon::generated | vst3_s8 | function | * Neon intrinsic unsafe | |
| 2042 | core::core_arch::arm_shared::neon::generated | vst3_u16 | function | * Neon intrinsic unsafe | |
| 2043 | core::core_arch::arm_shared::neon::generated | vst3_u32 | function | * Neon intrinsic unsafe | |
| 2044 | core::core_arch::arm_shared::neon::generated | vst3_u64 | function | * Neon intrinsic unsafe | |
| 2045 | core::core_arch::arm_shared::neon::generated | vst3_u8 | function | * Neon intrinsic unsafe | |
| 2046 | core::core_arch::arm_shared::neon::generated | vst3q_f16 | function | * Neon intrinsic unsafe | |
| 2047 | core::core_arch::arm_shared::neon::generated | vst3q_f32 | function | * Neon intrinsic unsafe | |
| 2048 | core::core_arch::arm_shared::neon::generated | vst3q_lane_f16 | function | * Neon intrinsic unsafe | |
| 2049 | core::core_arch::arm_shared::neon::generated | vst3q_lane_f32 | function | * Neon intrinsic unsafe | |
| 2050 | core::core_arch::arm_shared::neon::generated | vst3q_lane_p16 | function | * Neon intrinsic unsafe | |
| 2051 | core::core_arch::arm_shared::neon::generated | vst3q_lane_s16 | function | * Neon intrinsic unsafe | |
| 2052 | core::core_arch::arm_shared::neon::generated | vst3q_lane_s32 | function | * Neon intrinsic unsafe | |
| 2053 | core::core_arch::arm_shared::neon::generated | vst3q_lane_u16 | function | * Neon intrinsic unsafe | |
| 2054 | core::core_arch::arm_shared::neon::generated | vst3q_lane_u32 | function | * Neon intrinsic unsafe | |
| 2055 | core::core_arch::arm_shared::neon::generated | vst3q_p16 | function | * Neon intrinsic unsafe | |
| 2056 | core::core_arch::arm_shared::neon::generated | vst3q_p8 | function | * Neon intrinsic unsafe | |
| 2057 | core::core_arch::arm_shared::neon::generated | vst3q_s16 | function | * Neon intrinsic unsafe | |
| 2058 | core::core_arch::arm_shared::neon::generated | vst3q_s32 | function | * Neon intrinsic unsafe | |
| 2059 | core::core_arch::arm_shared::neon::generated | vst3q_s8 | function | * Neon intrinsic unsafe | |
| 2060 | core::core_arch::arm_shared::neon::generated | vst3q_u16 | function | * Neon intrinsic unsafe | |
| 2061 | core::core_arch::arm_shared::neon::generated | vst3q_u32 | function | * Neon intrinsic unsafe | |
| 2062 | core::core_arch::arm_shared::neon::generated | vst3q_u8 | function | * Neon intrinsic unsafe | |
| 2063 | core::core_arch::arm_shared::neon::generated | vst4_f16 | function | * Neon intrinsic unsafe | |
| 2064 | core::core_arch::arm_shared::neon::generated | vst4_f32 | function | * Neon intrinsic unsafe | |
| 2065 | core::core_arch::arm_shared::neon::generated | vst4_lane_f16 | function | * Neon intrinsic unsafe | |
| 2066 | core::core_arch::arm_shared::neon::generated | vst4_lane_f32 | function | * Neon intrinsic unsafe | |
| 2067 | core::core_arch::arm_shared::neon::generated | vst4_lane_p16 | function | * Neon intrinsic unsafe | |
| 2068 | core::core_arch::arm_shared::neon::generated | vst4_lane_p8 | function | * Neon intrinsic unsafe | |
| 2069 | core::core_arch::arm_shared::neon::generated | vst4_lane_s16 | function | * Neon intrinsic unsafe | |
| 2070 | core::core_arch::arm_shared::neon::generated | vst4_lane_s32 | function | * Neon intrinsic unsafe | |
| 2071 | core::core_arch::arm_shared::neon::generated | vst4_lane_s8 | function | * Neon intrinsic unsafe | |
| 2072 | core::core_arch::arm_shared::neon::generated | vst4_lane_u16 | function | * Neon intrinsic unsafe | |
| 2073 | core::core_arch::arm_shared::neon::generated | vst4_lane_u32 | function | * Neon intrinsic unsafe | |
| 2074 | core::core_arch::arm_shared::neon::generated | vst4_lane_u8 | function | * Neon intrinsic unsafe | |
| 2075 | core::core_arch::arm_shared::neon::generated | vst4_p16 | function | * Neon intrinsic unsafe | |
| 2076 | core::core_arch::arm_shared::neon::generated | vst4_p64 | function | * Neon intrinsic unsafe | |
| 2077 | core::core_arch::arm_shared::neon::generated | vst4_p8 | function | * Neon intrinsic unsafe | |
| 2078 | core::core_arch::arm_shared::neon::generated | vst4_s16 | function | * Neon intrinsic unsafe | |
| 2079 | core::core_arch::arm_shared::neon::generated | vst4_s32 | function | * Neon intrinsic unsafe | |
| 2080 | core::core_arch::arm_shared::neon::generated | vst4_s64 | function | * Neon intrinsic unsafe | |
| 2081 | core::core_arch::arm_shared::neon::generated | vst4_s8 | function | * Neon intrinsic unsafe | |
| 2082 | core::core_arch::arm_shared::neon::generated | vst4_u16 | function | * Neon intrinsic unsafe | |
| 2083 | core::core_arch::arm_shared::neon::generated | vst4_u32 | function | * Neon intrinsic unsafe | |
| 2084 | core::core_arch::arm_shared::neon::generated | vst4_u64 | function | * Neon intrinsic unsafe | |
| 2085 | core::core_arch::arm_shared::neon::generated | vst4_u8 | function | * Neon intrinsic unsafe | |
| 2086 | core::core_arch::arm_shared::neon::generated | vst4q_f16 | function | * Neon intrinsic unsafe | |
| 2087 | core::core_arch::arm_shared::neon::generated | vst4q_f32 | function | * Neon intrinsic unsafe | |
| 2088 | core::core_arch::arm_shared::neon::generated | vst4q_lane_f16 | function | * Neon intrinsic unsafe | |
| 2089 | core::core_arch::arm_shared::neon::generated | vst4q_lane_f32 | function | * Neon intrinsic unsafe | |
| 2090 | core::core_arch::arm_shared::neon::generated | vst4q_lane_p16 | function | * Neon intrinsic unsafe | |
| 2091 | core::core_arch::arm_shared::neon::generated | vst4q_lane_s16 | function | * Neon intrinsic unsafe | |
| 2092 | core::core_arch::arm_shared::neon::generated | vst4q_lane_s32 | function | * Neon intrinsic unsafe | |
| 2093 | core::core_arch::arm_shared::neon::generated | vst4q_lane_u16 | function | * Neon intrinsic unsafe | |
| 2094 | core::core_arch::arm_shared::neon::generated | vst4q_lane_u32 | function | * Neon intrinsic unsafe | |
| 2095 | core::core_arch::arm_shared::neon::generated | vst4q_p16 | function | * Neon intrinsic unsafe | |
| 2096 | core::core_arch::arm_shared::neon::generated | vst4q_p8 | function | * Neon intrinsic unsafe | |
| 2097 | core::core_arch::arm_shared::neon::generated | vst4q_s16 | function | * Neon intrinsic unsafe | |
| 2098 | core::core_arch::arm_shared::neon::generated | vst4q_s32 | function | * Neon intrinsic unsafe | |
| 2099 | core::core_arch::arm_shared::neon::generated | vst4q_s8 | function | * Neon intrinsic unsafe | |
| 2100 | core::core_arch::arm_shared::neon::generated | vst4q_u16 | function | * Neon intrinsic unsafe | |
| 2101 | core::core_arch::arm_shared::neon::generated | vst4q_u32 | function | * Neon intrinsic unsafe | |
| 2102 | core::core_arch::arm_shared::neon::generated | vst4q_u8 | function | * Neon intrinsic unsafe | |
| 2103 | core::core_arch::arm_shared::neon::generated | vstrq_p128 | function | * Neon intrinsic unsafe | |
| 2104 | core::core_arch::hexagon::scalar | Q6_P_abs_P | function | ||
| 2105 | core::core_arch::hexagon::scalar | Q6_P_add_PP | function | ||
| 2106 | core::core_arch::hexagon::scalar | Q6_P_add_PP_sat | function | ||
| 2107 | core::core_arch::hexagon::scalar | Q6_P_add_RP | function | ||
| 2108 | core::core_arch::hexagon::scalar | Q6_P_and_PP | function | ||
| 2109 | core::core_arch::hexagon::scalar | Q6_P_and_PnP | function | ||
| 2110 | core::core_arch::hexagon::scalar | Q6_P_asl_PI | function | ||
| 2111 | core::core_arch::hexagon::scalar | Q6_P_asl_PR | function | ||
| 2112 | core::core_arch::hexagon::scalar | Q6_P_aslacc_PI | function | ||
| 2113 | core::core_arch::hexagon::scalar | Q6_P_aslacc_PR | function | ||
| 2114 | core::core_arch::hexagon::scalar | Q6_P_asland_PI | function | ||
| 2115 | core::core_arch::hexagon::scalar | Q6_P_asland_PR | function | ||
| 2116 | core::core_arch::hexagon::scalar | Q6_P_aslnac_PI | function | ||
| 2117 | core::core_arch::hexagon::scalar | Q6_P_aslnac_PR | function | ||
| 2118 | core::core_arch::hexagon::scalar | Q6_P_aslor_PI | function | ||
| 2119 | core::core_arch::hexagon::scalar | Q6_P_aslor_PR | function | ||
| 2120 | core::core_arch::hexagon::scalar | Q6_P_aslxacc_PI | function | ||
| 2121 | core::core_arch::hexagon::scalar | Q6_P_aslxacc_PR | function | ||
| 2122 | core::core_arch::hexagon::scalar | Q6_P_asr_PI | function | ||
| 2123 | core::core_arch::hexagon::scalar | Q6_P_asr_PI_rnd | function | ||
| 2124 | core::core_arch::hexagon::scalar | Q6_P_asr_PR | function | ||
| 2125 | core::core_arch::hexagon::scalar | Q6_P_asracc_PI | function | ||
| 2126 | core::core_arch::hexagon::scalar | Q6_P_asracc_PR | function | ||
| 2127 | core::core_arch::hexagon::scalar | Q6_P_asrand_PI | function | ||
| 2128 | core::core_arch::hexagon::scalar | Q6_P_asrand_PR | function | ||
| 2129 | core::core_arch::hexagon::scalar | Q6_P_asrnac_PI | function | ||
| 2130 | core::core_arch::hexagon::scalar | Q6_P_asrnac_PR | function | ||
| 2131 | core::core_arch::hexagon::scalar | Q6_P_asror_PI | function | ||
| 2132 | core::core_arch::hexagon::scalar | Q6_P_asror_PR | function | ||
| 2133 | core::core_arch::hexagon::scalar | Q6_P_asrrnd_PI | function | ||
| 2134 | core::core_arch::hexagon::scalar | Q6_P_asrxacc_PR | function | ||
| 2135 | core::core_arch::hexagon::scalar | Q6_P_bitsplit_RI | function | ||
| 2136 | core::core_arch::hexagon::scalar | Q6_P_bitsplit_RR | function | ||
| 2137 | core::core_arch::hexagon::scalar | Q6_P_brev_P | function | ||
| 2138 | core::core_arch::hexagon::scalar | Q6_P_cmpy_RR_conj_s1_sat | function | ||
| 2139 | core::core_arch::hexagon::scalar | Q6_P_cmpy_RR_conj_sat | function | ||
| 2140 | core::core_arch::hexagon::scalar | Q6_P_cmpy_RR_s1_sat | function | ||
| 2141 | core::core_arch::hexagon::scalar | Q6_P_cmpy_RR_sat | function | ||
| 2142 | core::core_arch::hexagon::scalar | Q6_P_cmpyacc_RR_conj_s1_sat | function | ||
| 2143 | core::core_arch::hexagon::scalar | Q6_P_cmpyacc_RR_conj_sat | function | ||
| 2144 | core::core_arch::hexagon::scalar | Q6_P_cmpyacc_RR_s1_sat | function | ||
| 2145 | core::core_arch::hexagon::scalar | Q6_P_cmpyacc_RR_sat | function | ||
| 2146 | core::core_arch::hexagon::scalar | Q6_P_cmpyi_RR | function | ||
| 2147 | core::core_arch::hexagon::scalar | Q6_P_cmpyiacc_RR | function | ||
| 2148 | core::core_arch::hexagon::scalar | Q6_P_cmpyiw_PP | function | ||
| 2149 | core::core_arch::hexagon::scalar | Q6_P_cmpyiw_PP_conj | function | ||
| 2150 | core::core_arch::hexagon::scalar | Q6_P_cmpyiwacc_PP | function | ||
| 2151 | core::core_arch::hexagon::scalar | Q6_P_cmpyiwacc_PP_conj | function | ||
| 2152 | core::core_arch::hexagon::scalar | Q6_P_cmpynac_RR_conj_s1_sat | function | ||
| 2153 | core::core_arch::hexagon::scalar | Q6_P_cmpynac_RR_conj_sat | function | ||
| 2154 | core::core_arch::hexagon::scalar | Q6_P_cmpynac_RR_s1_sat | function | ||
| 2155 | core::core_arch::hexagon::scalar | Q6_P_cmpynac_RR_sat | function | ||
| 2156 | core::core_arch::hexagon::scalar | Q6_P_cmpyr_RR | function | ||
| 2157 | core::core_arch::hexagon::scalar | Q6_P_cmpyracc_RR | function | ||
| 2158 | core::core_arch::hexagon::scalar | Q6_P_cmpyrw_PP | function | ||
| 2159 | core::core_arch::hexagon::scalar | Q6_P_cmpyrw_PP_conj | function | ||
| 2160 | core::core_arch::hexagon::scalar | Q6_P_cmpyrwacc_PP | function | ||
| 2161 | core::core_arch::hexagon::scalar | Q6_P_cmpyrwacc_PP_conj | function | ||
| 2162 | core::core_arch::hexagon::scalar | Q6_P_combine_II | function | ||
| 2163 | core::core_arch::hexagon::scalar | Q6_P_combine_IR | function | ||
| 2164 | core::core_arch::hexagon::scalar | Q6_P_combine_RI | function | ||
| 2165 | core::core_arch::hexagon::scalar | Q6_P_combine_RR | function | ||
| 2166 | core::core_arch::hexagon::scalar | Q6_P_convert_d2df_P | function | ||
| 2167 | core::core_arch::hexagon::scalar | Q6_P_convert_df2d_P | function | ||
| 2168 | core::core_arch::hexagon::scalar | Q6_P_convert_df2d_P_chop | function | ||
| 2169 | core::core_arch::hexagon::scalar | Q6_P_convert_df2ud_P | function | ||
| 2170 | core::core_arch::hexagon::scalar | Q6_P_convert_df2ud_P_chop | function | ||
| 2171 | core::core_arch::hexagon::scalar | Q6_P_convert_sf2d_R | function | ||
| 2172 | core::core_arch::hexagon::scalar | Q6_P_convert_sf2d_R_chop | function | ||
| 2173 | core::core_arch::hexagon::scalar | Q6_P_convert_sf2df_R | function | ||
| 2174 | core::core_arch::hexagon::scalar | Q6_P_convert_sf2ud_R | function | ||
| 2175 | core::core_arch::hexagon::scalar | Q6_P_convert_sf2ud_R_chop | function | ||
| 2176 | core::core_arch::hexagon::scalar | Q6_P_convert_ud2df_P | function | ||
| 2177 | core::core_arch::hexagon::scalar | Q6_P_convert_uw2df_R | function | ||
| 2178 | core::core_arch::hexagon::scalar | Q6_P_convert_w2df_R | function | ||
| 2179 | core::core_arch::hexagon::scalar | Q6_P_cround_PI | function | ||
| 2180 | core::core_arch::hexagon::scalar | Q6_P_cround_PR | function | ||
| 2181 | core::core_arch::hexagon::scalar | Q6_P_deinterleave_P | function | ||
| 2182 | core::core_arch::hexagon::scalar | Q6_P_dfadd_PP | function | ||
| 2183 | core::core_arch::hexagon::scalar | Q6_P_dfmake_I_neg | function | ||
| 2184 | core::core_arch::hexagon::scalar | Q6_P_dfmake_I_pos | function | ||
| 2185 | core::core_arch::hexagon::scalar | Q6_P_dfmax_PP | function | ||
| 2186 | core::core_arch::hexagon::scalar | Q6_P_dfmin_PP | function | ||
| 2187 | core::core_arch::hexagon::scalar | Q6_P_dfmpyfix_PP | function | ||
| 2188 | core::core_arch::hexagon::scalar | Q6_P_dfmpyhhacc_PP | function | ||
| 2189 | core::core_arch::hexagon::scalar | Q6_P_dfmpylhacc_PP | function | ||
| 2190 | core::core_arch::hexagon::scalar | Q6_P_dfmpyll_PP | function | ||
| 2191 | core::core_arch::hexagon::scalar | Q6_P_dfsub_PP | function | ||
| 2192 | core::core_arch::hexagon::scalar | Q6_P_equals_I | function | ||
| 2193 | core::core_arch::hexagon::scalar | Q6_P_equals_P | function | ||
| 2194 | core::core_arch::hexagon::scalar | Q6_P_extract_PII | function | ||
| 2195 | core::core_arch::hexagon::scalar | Q6_P_extract_PP | function | ||
| 2196 | core::core_arch::hexagon::scalar | Q6_P_extractu_PII | function | ||
| 2197 | core::core_arch::hexagon::scalar | Q6_P_extractu_PP | function | ||
| 2198 | core::core_arch::hexagon::scalar | Q6_P_insert_PII | function | ||
| 2199 | core::core_arch::hexagon::scalar | Q6_P_insert_PP | function | ||
| 2200 | core::core_arch::hexagon::scalar | Q6_P_interleave_P | function | ||
| 2201 | core::core_arch::hexagon::scalar | Q6_P_lfs_PP | function | ||
| 2202 | core::core_arch::hexagon::scalar | Q6_P_lsl_PR | function | ||
| 2203 | core::core_arch::hexagon::scalar | Q6_P_lslacc_PR | function | ||
| 2204 | core::core_arch::hexagon::scalar | Q6_P_lsland_PR | function | ||
| 2205 | core::core_arch::hexagon::scalar | Q6_P_lslnac_PR | function | ||
| 2206 | core::core_arch::hexagon::scalar | Q6_P_lslor_PR | function | ||
| 2207 | core::core_arch::hexagon::scalar | Q6_P_lslxacc_PR | function | ||
| 2208 | core::core_arch::hexagon::scalar | Q6_P_lsr_PI | function | ||
| 2209 | core::core_arch::hexagon::scalar | Q6_P_lsr_PR | function | ||
| 2210 | core::core_arch::hexagon::scalar | Q6_P_lsracc_PI | function | ||
| 2211 | core::core_arch::hexagon::scalar | Q6_P_lsracc_PR | function | ||
| 2212 | core::core_arch::hexagon::scalar | Q6_P_lsrand_PI | function | ||
| 2213 | core::core_arch::hexagon::scalar | Q6_P_lsrand_PR | function | ||
| 2214 | core::core_arch::hexagon::scalar | Q6_P_lsrnac_PI | function | ||
| 2215 | core::core_arch::hexagon::scalar | Q6_P_lsrnac_PR | function | ||
| 2216 | core::core_arch::hexagon::scalar | Q6_P_lsror_PI | function | ||
| 2217 | core::core_arch::hexagon::scalar | Q6_P_lsror_PR | function | ||
| 2218 | core::core_arch::hexagon::scalar | Q6_P_lsrxacc_PI | function | ||
| 2219 | core::core_arch::hexagon::scalar | Q6_P_lsrxacc_PR | function | ||
| 2220 | core::core_arch::hexagon::scalar | Q6_P_mask_p | function | ||
| 2221 | core::core_arch::hexagon::scalar | Q6_P_max_PP | function | ||
| 2222 | core::core_arch::hexagon::scalar | Q6_P_maxu_PP | function | ||
| 2223 | core::core_arch::hexagon::scalar | Q6_P_min_PP | function | ||
| 2224 | core::core_arch::hexagon::scalar | Q6_P_minu_PP | function | ||
| 2225 | core::core_arch::hexagon::scalar | Q6_P_mpy_RR | function | ||
| 2226 | core::core_arch::hexagon::scalar | Q6_P_mpy_RhRh | function | ||
| 2227 | core::core_arch::hexagon::scalar | Q6_P_mpy_RhRh_rnd | function | ||
| 2228 | core::core_arch::hexagon::scalar | Q6_P_mpy_RhRh_s1 | function | ||
| 2229 | core::core_arch::hexagon::scalar | Q6_P_mpy_RhRh_s1_rnd | function | ||
| 2230 | core::core_arch::hexagon::scalar | Q6_P_mpy_RhRl | function | ||
| 2231 | core::core_arch::hexagon::scalar | Q6_P_mpy_RhRl_rnd | function | ||
| 2232 | core::core_arch::hexagon::scalar | Q6_P_mpy_RhRl_s1 | function | ||
| 2233 | core::core_arch::hexagon::scalar | Q6_P_mpy_RhRl_s1_rnd | function | ||
| 2234 | core::core_arch::hexagon::scalar | Q6_P_mpy_RlRh | function | ||
| 2235 | core::core_arch::hexagon::scalar | Q6_P_mpy_RlRh_rnd | function | ||
| 2236 | core::core_arch::hexagon::scalar | Q6_P_mpy_RlRh_s1 | function | ||
| 2237 | core::core_arch::hexagon::scalar | Q6_P_mpy_RlRh_s1_rnd | function | ||
| 2238 | core::core_arch::hexagon::scalar | Q6_P_mpy_RlRl | function | ||
| 2239 | core::core_arch::hexagon::scalar | Q6_P_mpy_RlRl_rnd | function | ||
| 2240 | core::core_arch::hexagon::scalar | Q6_P_mpy_RlRl_s1 | function | ||
| 2241 | core::core_arch::hexagon::scalar | Q6_P_mpy_RlRl_s1_rnd | function | ||
| 2242 | core::core_arch::hexagon::scalar | Q6_P_mpyacc_RR | function | ||
| 2243 | core::core_arch::hexagon::scalar | Q6_P_mpyacc_RhRh | function | ||
| 2244 | core::core_arch::hexagon::scalar | Q6_P_mpyacc_RhRh_s1 | function | ||
| 2245 | core::core_arch::hexagon::scalar | Q6_P_mpyacc_RhRl | function | ||
| 2246 | core::core_arch::hexagon::scalar | Q6_P_mpyacc_RhRl_s1 | function | ||
| 2247 | core::core_arch::hexagon::scalar | Q6_P_mpyacc_RlRh | function | ||
| 2248 | core::core_arch::hexagon::scalar | Q6_P_mpyacc_RlRh_s1 | function | ||
| 2249 | core::core_arch::hexagon::scalar | Q6_P_mpyacc_RlRl | function | ||
| 2250 | core::core_arch::hexagon::scalar | Q6_P_mpyacc_RlRl_s1 | function | ||
| 2251 | core::core_arch::hexagon::scalar | Q6_P_mpynac_RR | function | ||
| 2252 | core::core_arch::hexagon::scalar | Q6_P_mpynac_RhRh | function | ||
| 2253 | core::core_arch::hexagon::scalar | Q6_P_mpynac_RhRh_s1 | function | ||
| 2254 | core::core_arch::hexagon::scalar | Q6_P_mpynac_RhRl | function | ||
| 2255 | core::core_arch::hexagon::scalar | Q6_P_mpynac_RhRl_s1 | function | ||
| 2256 | core::core_arch::hexagon::scalar | Q6_P_mpynac_RlRh | function | ||
| 2257 | core::core_arch::hexagon::scalar | Q6_P_mpynac_RlRh_s1 | function | ||
| 2258 | core::core_arch::hexagon::scalar | Q6_P_mpynac_RlRl | function | ||
| 2259 | core::core_arch::hexagon::scalar | Q6_P_mpynac_RlRl_s1 | function | ||
| 2260 | core::core_arch::hexagon::scalar | Q6_P_mpyu_RR | function | ||
| 2261 | core::core_arch::hexagon::scalar | Q6_P_mpyu_RhRh | function | ||
| 2262 | core::core_arch::hexagon::scalar | Q6_P_mpyu_RhRh_s1 | function | ||
| 2263 | core::core_arch::hexagon::scalar | Q6_P_mpyu_RhRl | function | ||
| 2264 | core::core_arch::hexagon::scalar | Q6_P_mpyu_RhRl_s1 | function | ||
| 2265 | core::core_arch::hexagon::scalar | Q6_P_mpyu_RlRh | function | ||
| 2266 | core::core_arch::hexagon::scalar | Q6_P_mpyu_RlRh_s1 | function | ||
| 2267 | core::core_arch::hexagon::scalar | Q6_P_mpyu_RlRl | function | ||
| 2268 | core::core_arch::hexagon::scalar | Q6_P_mpyu_RlRl_s1 | function | ||
| 2269 | core::core_arch::hexagon::scalar | Q6_P_mpyuacc_RR | function | ||
| 2270 | core::core_arch::hexagon::scalar | Q6_P_mpyuacc_RhRh | function | ||
| 2271 | core::core_arch::hexagon::scalar | Q6_P_mpyuacc_RhRh_s1 | function | ||
| 2272 | core::core_arch::hexagon::scalar | Q6_P_mpyuacc_RhRl | function | ||
| 2273 | core::core_arch::hexagon::scalar | Q6_P_mpyuacc_RhRl_s1 | function | ||
| 2274 | core::core_arch::hexagon::scalar | Q6_P_mpyuacc_RlRh | function | ||
| 2275 | core::core_arch::hexagon::scalar | Q6_P_mpyuacc_RlRh_s1 | function | ||
| 2276 | core::core_arch::hexagon::scalar | Q6_P_mpyuacc_RlRl | function | ||
| 2277 | core::core_arch::hexagon::scalar | Q6_P_mpyuacc_RlRl_s1 | function | ||
| 2278 | core::core_arch::hexagon::scalar | Q6_P_mpyunac_RR | function | ||
| 2279 | core::core_arch::hexagon::scalar | Q6_P_mpyunac_RhRh | function | ||
| 2280 | core::core_arch::hexagon::scalar | Q6_P_mpyunac_RhRh_s1 | function | ||
| 2281 | core::core_arch::hexagon::scalar | Q6_P_mpyunac_RhRl | function | ||
| 2282 | core::core_arch::hexagon::scalar | Q6_P_mpyunac_RhRl_s1 | function | ||
| 2283 | core::core_arch::hexagon::scalar | Q6_P_mpyunac_RlRh | function | ||
| 2284 | core::core_arch::hexagon::scalar | Q6_P_mpyunac_RlRh_s1 | function | ||
| 2285 | core::core_arch::hexagon::scalar | Q6_P_mpyunac_RlRl | function | ||
| 2286 | core::core_arch::hexagon::scalar | Q6_P_mpyunac_RlRl_s1 | function | ||
| 2287 | core::core_arch::hexagon::scalar | Q6_P_neg_P | function | ||
| 2288 | core::core_arch::hexagon::scalar | Q6_P_not_P | function | ||
| 2289 | core::core_arch::hexagon::scalar | Q6_P_or_PP | function | ||
| 2290 | core::core_arch::hexagon::scalar | Q6_P_or_PnP | function | ||
| 2291 | core::core_arch::hexagon::scalar | Q6_P_packhl_RR | function | ||
| 2292 | core::core_arch::hexagon::scalar | Q6_P_pmpyw_RR | function | ||
| 2293 | core::core_arch::hexagon::scalar | Q6_P_pmpywxacc_RR | function | ||
| 2294 | core::core_arch::hexagon::scalar | Q6_P_rol_PI | function | ||
| 2295 | core::core_arch::hexagon::scalar | Q6_P_rolacc_PI | function | ||
| 2296 | core::core_arch::hexagon::scalar | Q6_P_roland_PI | function | ||
| 2297 | core::core_arch::hexagon::scalar | Q6_P_rolnac_PI | function | ||
| 2298 | core::core_arch::hexagon::scalar | Q6_P_rolor_PI | function | ||
| 2299 | core::core_arch::hexagon::scalar | Q6_P_rolxacc_PI | function | ||
| 2300 | core::core_arch::hexagon::scalar | Q6_P_shuffeb_PP | function | ||
| 2301 | core::core_arch::hexagon::scalar | Q6_P_shuffeh_PP | function | ||
| 2302 | core::core_arch::hexagon::scalar | Q6_P_shuffob_PP | function | ||
| 2303 | core::core_arch::hexagon::scalar | Q6_P_shuffoh_PP | function | ||
| 2304 | core::core_arch::hexagon::scalar | Q6_P_sub_PP | function | ||
| 2305 | core::core_arch::hexagon::scalar | Q6_P_sxtw_R | function | ||
| 2306 | core::core_arch::hexagon::scalar | Q6_P_vabsdiffb_PP | function | ||
| 2307 | core::core_arch::hexagon::scalar | Q6_P_vabsdiffh_PP | function | ||
| 2308 | core::core_arch::hexagon::scalar | Q6_P_vabsdiffub_PP | function | ||
| 2309 | core::core_arch::hexagon::scalar | Q6_P_vabsdiffw_PP | function | ||
| 2310 | core::core_arch::hexagon::scalar | Q6_P_vabsh_P | function | ||
| 2311 | core::core_arch::hexagon::scalar | Q6_P_vabsh_P_sat | function | ||
| 2312 | core::core_arch::hexagon::scalar | Q6_P_vabsw_P | function | ||
| 2313 | core::core_arch::hexagon::scalar | Q6_P_vabsw_P_sat | function | ||
| 2314 | core::core_arch::hexagon::scalar | Q6_P_vaddb_PP | function | ||
| 2315 | core::core_arch::hexagon::scalar | Q6_P_vaddh_PP | function | ||
| 2316 | core::core_arch::hexagon::scalar | Q6_P_vaddh_PP_sat | function | ||
| 2317 | core::core_arch::hexagon::scalar | Q6_P_vaddub_PP | function | ||
| 2318 | core::core_arch::hexagon::scalar | Q6_P_vaddub_PP_sat | function | ||
| 2319 | core::core_arch::hexagon::scalar | Q6_P_vadduh_PP_sat | function | ||
| 2320 | core::core_arch::hexagon::scalar | Q6_P_vaddw_PP | function | ||
| 2321 | core::core_arch::hexagon::scalar | Q6_P_vaddw_PP_sat | function | ||
| 2322 | core::core_arch::hexagon::scalar | Q6_P_valignb_PPI | function | ||
| 2323 | core::core_arch::hexagon::scalar | Q6_P_valignb_PPp | function | ||
| 2324 | core::core_arch::hexagon::scalar | Q6_P_vaslh_PI | function | ||
| 2325 | core::core_arch::hexagon::scalar | Q6_P_vaslh_PR | function | ||
| 2326 | core::core_arch::hexagon::scalar | Q6_P_vaslw_PI | function | ||
| 2327 | core::core_arch::hexagon::scalar | Q6_P_vaslw_PR | function | ||
| 2328 | core::core_arch::hexagon::scalar | Q6_P_vasrh_PI | function | ||
| 2329 | core::core_arch::hexagon::scalar | Q6_P_vasrh_PI_rnd | function | ||
| 2330 | core::core_arch::hexagon::scalar | Q6_P_vasrh_PR | function | ||
| 2331 | core::core_arch::hexagon::scalar | Q6_P_vasrw_PI | function | ||
| 2332 | core::core_arch::hexagon::scalar | Q6_P_vasrw_PR | function | ||
| 2333 | core::core_arch::hexagon::scalar | Q6_P_vavgh_PP | function | ||
| 2334 | core::core_arch::hexagon::scalar | Q6_P_vavgh_PP_crnd | function | ||
| 2335 | core::core_arch::hexagon::scalar | Q6_P_vavgh_PP_rnd | function | ||
| 2336 | core::core_arch::hexagon::scalar | Q6_P_vavgub_PP | function | ||
| 2337 | core::core_arch::hexagon::scalar | Q6_P_vavgub_PP_rnd | function | ||
| 2338 | core::core_arch::hexagon::scalar | Q6_P_vavguh_PP | function | ||
| 2339 | core::core_arch::hexagon::scalar | Q6_P_vavguh_PP_rnd | function | ||
| 2340 | core::core_arch::hexagon::scalar | Q6_P_vavguw_PP | function | ||
| 2341 | core::core_arch::hexagon::scalar | Q6_P_vavguw_PP_rnd | function | ||
| 2342 | core::core_arch::hexagon::scalar | Q6_P_vavgw_PP | function | ||
| 2343 | core::core_arch::hexagon::scalar | Q6_P_vavgw_PP_crnd | function | ||
| 2344 | core::core_arch::hexagon::scalar | Q6_P_vavgw_PP_rnd | function | ||
| 2345 | core::core_arch::hexagon::scalar | Q6_P_vclip_PI | function | ||
| 2346 | core::core_arch::hexagon::scalar | Q6_P_vcmpyi_PP_s1_sat | function | ||
| 2347 | core::core_arch::hexagon::scalar | Q6_P_vcmpyi_PP_sat | function | ||
| 2348 | core::core_arch::hexagon::scalar | Q6_P_vcmpyiacc_PP_sat | function | ||
| 2349 | core::core_arch::hexagon::scalar | Q6_P_vcmpyr_PP_s1_sat | function | ||
| 2350 | core::core_arch::hexagon::scalar | Q6_P_vcmpyr_PP_sat | function | ||
| 2351 | core::core_arch::hexagon::scalar | Q6_P_vcmpyracc_PP_sat | function | ||
| 2352 | core::core_arch::hexagon::scalar | Q6_P_vcnegh_PR | function | ||
| 2353 | core::core_arch::hexagon::scalar | Q6_P_vconj_P_sat | function | ||
| 2354 | core::core_arch::hexagon::scalar | Q6_P_vcrotate_PR | function | ||
| 2355 | core::core_arch::hexagon::scalar | Q6_P_vdmpy_PP_s1_sat | function | ||
| 2356 | core::core_arch::hexagon::scalar | Q6_P_vdmpy_PP_sat | function | ||
| 2357 | core::core_arch::hexagon::scalar | Q6_P_vdmpyacc_PP_s1_sat | function | ||
| 2358 | core::core_arch::hexagon::scalar | Q6_P_vdmpyacc_PP_sat | function | ||
| 2359 | core::core_arch::hexagon::scalar | Q6_P_vdmpybsu_PP_sat | function | ||
| 2360 | core::core_arch::hexagon::scalar | Q6_P_vdmpybsuacc_PP_sat | function | ||
| 2361 | core::core_arch::hexagon::scalar | Q6_P_vdmpyw_PP | function | ||
| 2362 | core::core_arch::hexagon::scalar | Q6_P_vdmpywacc_PP | function | ||
| 2363 | core::core_arch::hexagon::scalar | Q6_P_vlslh_PR | function | ||
| 2364 | core::core_arch::hexagon::scalar | Q6_P_vlslw_PR | function | ||
| 2365 | core::core_arch::hexagon::scalar | Q6_P_vlsrh_PI | function | ||
| 2366 | core::core_arch::hexagon::scalar | Q6_P_vlsrh_PR | function | ||
| 2367 | core::core_arch::hexagon::scalar | Q6_P_vlsrw_PI | function | ||
| 2368 | core::core_arch::hexagon::scalar | Q6_P_vlsrw_PR | function | ||
| 2369 | core::core_arch::hexagon::scalar | Q6_P_vmaxb_PP | function | ||
| 2370 | core::core_arch::hexagon::scalar | Q6_P_vmaxh_PP | function | ||
| 2371 | core::core_arch::hexagon::scalar | Q6_P_vmaxub_PP | function | ||
| 2372 | core::core_arch::hexagon::scalar | Q6_P_vmaxuh_PP | function | ||
| 2373 | core::core_arch::hexagon::scalar | Q6_P_vmaxuw_PP | function | ||
| 2374 | core::core_arch::hexagon::scalar | Q6_P_vmaxw_PP | function | ||
| 2375 | core::core_arch::hexagon::scalar | Q6_P_vminb_PP | function | ||
| 2376 | core::core_arch::hexagon::scalar | Q6_P_vminh_PP | function | ||
| 2377 | core::core_arch::hexagon::scalar | Q6_P_vminub_PP | function | ||
| 2378 | core::core_arch::hexagon::scalar | Q6_P_vminuh_PP | function | ||
| 2379 | core::core_arch::hexagon::scalar | Q6_P_vminuw_PP | function | ||
| 2380 | core::core_arch::hexagon::scalar | Q6_P_vminw_PP | function | ||
| 2381 | core::core_arch::hexagon::scalar | Q6_P_vmpybsu_RR | function | ||
| 2382 | core::core_arch::hexagon::scalar | Q6_P_vmpybsuacc_RR | function | ||
| 2383 | core::core_arch::hexagon::scalar | Q6_P_vmpybu_RR | function | ||
| 2384 | core::core_arch::hexagon::scalar | Q6_P_vmpybuacc_RR | function | ||
| 2385 | core::core_arch::hexagon::scalar | Q6_P_vmpyeh_PP_s1_sat | function | ||
| 2386 | core::core_arch::hexagon::scalar | Q6_P_vmpyeh_PP_sat | function | ||
| 2387 | core::core_arch::hexagon::scalar | Q6_P_vmpyehacc_PP | function | ||
| 2388 | core::core_arch::hexagon::scalar | Q6_P_vmpyehacc_PP_s1_sat | function | ||
| 2389 | core::core_arch::hexagon::scalar | Q6_P_vmpyehacc_PP_sat | function | ||
| 2390 | core::core_arch::hexagon::scalar | Q6_P_vmpyh_RR_s1_sat | function | ||
| 2391 | core::core_arch::hexagon::scalar | Q6_P_vmpyh_RR_sat | function | ||
| 2392 | core::core_arch::hexagon::scalar | Q6_P_vmpyhacc_RR | function | ||
| 2393 | core::core_arch::hexagon::scalar | Q6_P_vmpyhacc_RR_s1_sat | function | ||
| 2394 | core::core_arch::hexagon::scalar | Q6_P_vmpyhacc_RR_sat | function | ||
| 2395 | core::core_arch::hexagon::scalar | Q6_P_vmpyhsu_RR_s1_sat | function | ||
| 2396 | core::core_arch::hexagon::scalar | Q6_P_vmpyhsu_RR_sat | function | ||
| 2397 | core::core_arch::hexagon::scalar | Q6_P_vmpyhsuacc_RR_s1_sat | function | ||
| 2398 | core::core_arch::hexagon::scalar | Q6_P_vmpyhsuacc_RR_sat | function | ||
| 2399 | core::core_arch::hexagon::scalar | Q6_P_vmpyweh_PP_rnd_sat | function | ||
| 2400 | core::core_arch::hexagon::scalar | Q6_P_vmpyweh_PP_s1_rnd_sat | function | ||
| 2401 | core::core_arch::hexagon::scalar | Q6_P_vmpyweh_PP_s1_sat | function | ||
| 2402 | core::core_arch::hexagon::scalar | Q6_P_vmpyweh_PP_sat | function | ||
| 2403 | core::core_arch::hexagon::scalar | Q6_P_vmpywehacc_PP_rnd_sat | function | ||
| 2404 | core::core_arch::hexagon::scalar | Q6_P_vmpywehacc_PP_s1_rnd_sat | function | ||
| 2405 | core::core_arch::hexagon::scalar | Q6_P_vmpywehacc_PP_s1_sat | function | ||
| 2406 | core::core_arch::hexagon::scalar | Q6_P_vmpywehacc_PP_sat | function | ||
| 2407 | core::core_arch::hexagon::scalar | Q6_P_vmpyweuh_PP_rnd_sat | function | ||
| 2408 | core::core_arch::hexagon::scalar | Q6_P_vmpyweuh_PP_s1_rnd_sat | function | ||
| 2409 | core::core_arch::hexagon::scalar | Q6_P_vmpyweuh_PP_s1_sat | function | ||
| 2410 | core::core_arch::hexagon::scalar | Q6_P_vmpyweuh_PP_sat | function | ||
| 2411 | core::core_arch::hexagon::scalar | Q6_P_vmpyweuhacc_PP_rnd_sat | function | ||
| 2412 | core::core_arch::hexagon::scalar | Q6_P_vmpyweuhacc_PP_s1_rnd_sat | function | ||
| 2413 | core::core_arch::hexagon::scalar | Q6_P_vmpyweuhacc_PP_s1_sat | function | ||
| 2414 | core::core_arch::hexagon::scalar | Q6_P_vmpyweuhacc_PP_sat | function | ||
| 2415 | core::core_arch::hexagon::scalar | Q6_P_vmpywoh_PP_rnd_sat | function | ||
| 2416 | core::core_arch::hexagon::scalar | Q6_P_vmpywoh_PP_s1_rnd_sat | function | ||
| 2417 | core::core_arch::hexagon::scalar | Q6_P_vmpywoh_PP_s1_sat | function | ||
| 2418 | core::core_arch::hexagon::scalar | Q6_P_vmpywoh_PP_sat | function | ||
| 2419 | core::core_arch::hexagon::scalar | Q6_P_vmpywohacc_PP_rnd_sat | function | ||
| 2420 | core::core_arch::hexagon::scalar | Q6_P_vmpywohacc_PP_s1_rnd_sat | function | ||
| 2421 | core::core_arch::hexagon::scalar | Q6_P_vmpywohacc_PP_s1_sat | function | ||
| 2422 | core::core_arch::hexagon::scalar | Q6_P_vmpywohacc_PP_sat | function | ||
| 2423 | core::core_arch::hexagon::scalar | Q6_P_vmpywouh_PP_rnd_sat | function | ||
| 2424 | core::core_arch::hexagon::scalar | Q6_P_vmpywouh_PP_s1_rnd_sat | function | ||
| 2425 | core::core_arch::hexagon::scalar | Q6_P_vmpywouh_PP_s1_sat | function | ||
| 2426 | core::core_arch::hexagon::scalar | Q6_P_vmpywouh_PP_sat | function | ||
| 2427 | core::core_arch::hexagon::scalar | Q6_P_vmpywouhacc_PP_rnd_sat | function | ||
| 2428 | core::core_arch::hexagon::scalar | Q6_P_vmpywouhacc_PP_s1_rnd_sat | function | ||
| 2429 | core::core_arch::hexagon::scalar | Q6_P_vmpywouhacc_PP_s1_sat | function | ||
| 2430 | core::core_arch::hexagon::scalar | Q6_P_vmpywouhacc_PP_sat | function | ||
| 2431 | core::core_arch::hexagon::scalar | Q6_P_vmux_pPP | function | ||
| 2432 | core::core_arch::hexagon::scalar | Q6_P_vnavgh_PP | function | ||
| 2433 | core::core_arch::hexagon::scalar | Q6_P_vnavgh_PP_crnd_sat | function | ||
| 2434 | core::core_arch::hexagon::scalar | Q6_P_vnavgh_PP_rnd_sat | function | ||
| 2435 | core::core_arch::hexagon::scalar | Q6_P_vnavgw_PP | function | ||
| 2436 | core::core_arch::hexagon::scalar | Q6_P_vnavgw_PP_crnd_sat | function | ||
| 2437 | core::core_arch::hexagon::scalar | Q6_P_vnavgw_PP_rnd_sat | function | ||
| 2438 | core::core_arch::hexagon::scalar | Q6_P_vpmpyh_RR | function | ||
| 2439 | core::core_arch::hexagon::scalar | Q6_P_vpmpyhxacc_RR | function | ||
| 2440 | core::core_arch::hexagon::scalar | Q6_P_vraddub_PP | function | ||
| 2441 | core::core_arch::hexagon::scalar | Q6_P_vraddubacc_PP | function | ||
| 2442 | core::core_arch::hexagon::scalar | Q6_P_vrcmpyi_PP | function | ||
| 2443 | core::core_arch::hexagon::scalar | Q6_P_vrcmpyi_PP_conj | function | ||
| 2444 | core::core_arch::hexagon::scalar | Q6_P_vrcmpyiacc_PP | function | ||
| 2445 | core::core_arch::hexagon::scalar | Q6_P_vrcmpyiacc_PP_conj | function | ||
| 2446 | core::core_arch::hexagon::scalar | Q6_P_vrcmpyr_PP | function | ||
| 2447 | core::core_arch::hexagon::scalar | Q6_P_vrcmpyr_PP_conj | function | ||
| 2448 | core::core_arch::hexagon::scalar | Q6_P_vrcmpyracc_PP | function | ||
| 2449 | core::core_arch::hexagon::scalar | Q6_P_vrcmpyracc_PP_conj | function | ||
| 2450 | core::core_arch::hexagon::scalar | Q6_P_vrcmpys_PR_s1_sat | function | ||
| 2451 | core::core_arch::hexagon::scalar | Q6_P_vrcmpysacc_PR_s1_sat | function | ||
| 2452 | core::core_arch::hexagon::scalar | Q6_P_vrcneghacc_PR | function | ||
| 2453 | core::core_arch::hexagon::scalar | Q6_P_vrcrotate_PRI | function | ||
| 2454 | core::core_arch::hexagon::scalar | Q6_P_vrcrotateacc_PRI | function | ||
| 2455 | core::core_arch::hexagon::scalar | Q6_P_vrmaxh_PR | function | ||
| 2456 | core::core_arch::hexagon::scalar | Q6_P_vrmaxuh_PR | function | ||
| 2457 | core::core_arch::hexagon::scalar | Q6_P_vrmaxuw_PR | function | ||
| 2458 | core::core_arch::hexagon::scalar | Q6_P_vrmaxw_PR | function | ||
| 2459 | core::core_arch::hexagon::scalar | Q6_P_vrminh_PR | function | ||
| 2460 | core::core_arch::hexagon::scalar | Q6_P_vrminuh_PR | function | ||
| 2461 | core::core_arch::hexagon::scalar | Q6_P_vrminuw_PR | function | ||
| 2462 | core::core_arch::hexagon::scalar | Q6_P_vrminw_PR | function | ||
| 2463 | core::core_arch::hexagon::scalar | Q6_P_vrmpybsu_PP | function | ||
| 2464 | core::core_arch::hexagon::scalar | Q6_P_vrmpybsuacc_PP | function | ||
| 2465 | core::core_arch::hexagon::scalar | Q6_P_vrmpybu_PP | function | ||
| 2466 | core::core_arch::hexagon::scalar | Q6_P_vrmpybuacc_PP | function | ||
| 2467 | core::core_arch::hexagon::scalar | Q6_P_vrmpyh_PP | function | ||
| 2468 | core::core_arch::hexagon::scalar | Q6_P_vrmpyhacc_PP | function | ||
| 2469 | core::core_arch::hexagon::scalar | Q6_P_vrmpyweh_PP | function | ||
| 2470 | core::core_arch::hexagon::scalar | Q6_P_vrmpyweh_PP_s1 | function | ||
| 2471 | core::core_arch::hexagon::scalar | Q6_P_vrmpywehacc_PP | function | ||
| 2472 | core::core_arch::hexagon::scalar | Q6_P_vrmpywehacc_PP_s1 | function | ||
| 2473 | core::core_arch::hexagon::scalar | Q6_P_vrmpywoh_PP | function | ||
| 2474 | core::core_arch::hexagon::scalar | Q6_P_vrmpywoh_PP_s1 | function | ||
| 2475 | core::core_arch::hexagon::scalar | Q6_P_vrmpywohacc_PP | function | ||
| 2476 | core::core_arch::hexagon::scalar | Q6_P_vrmpywohacc_PP_s1 | function | ||
| 2477 | core::core_arch::hexagon::scalar | Q6_P_vrsadub_PP | function | ||
| 2478 | core::core_arch::hexagon::scalar | Q6_P_vrsadubacc_PP | function | ||
| 2479 | core::core_arch::hexagon::scalar | Q6_P_vsathb_P | function | ||
| 2480 | core::core_arch::hexagon::scalar | Q6_P_vsathub_P | function | ||
| 2481 | core::core_arch::hexagon::scalar | Q6_P_vsatwh_P | function | ||
| 2482 | core::core_arch::hexagon::scalar | Q6_P_vsatwuh_P | function | ||
| 2483 | core::core_arch::hexagon::scalar | Q6_P_vsplatb_R | function | ||
| 2484 | core::core_arch::hexagon::scalar | Q6_P_vsplath_R | function | ||
| 2485 | core::core_arch::hexagon::scalar | Q6_P_vspliceb_PPI | function | ||
| 2486 | core::core_arch::hexagon::scalar | Q6_P_vspliceb_PPp | function | ||
| 2487 | core::core_arch::hexagon::scalar | Q6_P_vsubb_PP | function | ||
| 2488 | core::core_arch::hexagon::scalar | Q6_P_vsubh_PP | function | ||
| 2489 | core::core_arch::hexagon::scalar | Q6_P_vsubh_PP_sat | function | ||
| 2490 | core::core_arch::hexagon::scalar | Q6_P_vsubub_PP | function | ||
| 2491 | core::core_arch::hexagon::scalar | Q6_P_vsubub_PP_sat | function | ||
| 2492 | core::core_arch::hexagon::scalar | Q6_P_vsubuh_PP_sat | function | ||
| 2493 | core::core_arch::hexagon::scalar | Q6_P_vsubw_PP | function | ||
| 2494 | core::core_arch::hexagon::scalar | Q6_P_vsubw_PP_sat | function | ||
| 2495 | core::core_arch::hexagon::scalar | Q6_P_vsxtbh_R | function | ||
| 2496 | core::core_arch::hexagon::scalar | Q6_P_vsxthw_R | function | ||
| 2497 | core::core_arch::hexagon::scalar | Q6_P_vtrunehb_PP | function | ||
| 2498 | core::core_arch::hexagon::scalar | Q6_P_vtrunewh_PP | function | ||
| 2499 | core::core_arch::hexagon::scalar | Q6_P_vtrunohb_PP | function | ||
| 2500 | core::core_arch::hexagon::scalar | Q6_P_vtrunowh_PP | function | ||
| 2501 | core::core_arch::hexagon::scalar | Q6_P_vxaddsubh_PP_rnd_rs1_sat | function | ||
| 2502 | core::core_arch::hexagon::scalar | Q6_P_vxaddsubh_PP_sat | function | ||
| 2503 | core::core_arch::hexagon::scalar | Q6_P_vxaddsubw_PP_sat | function | ||
| 2504 | core::core_arch::hexagon::scalar | Q6_P_vxsubaddh_PP_rnd_rs1_sat | function | ||
| 2505 | core::core_arch::hexagon::scalar | Q6_P_vxsubaddh_PP_sat | function | ||
| 2506 | core::core_arch::hexagon::scalar | Q6_P_vxsubaddw_PP_sat | function | ||
| 2507 | core::core_arch::hexagon::scalar | Q6_P_vzxtbh_R | function | ||
| 2508 | core::core_arch::hexagon::scalar | Q6_P_vzxthw_R | function | ||
| 2509 | core::core_arch::hexagon::scalar | Q6_P_xor_PP | function | ||
| 2510 | core::core_arch::hexagon::scalar | Q6_P_xorxacc_PP | function | ||
| 2511 | core::core_arch::hexagon::scalar | Q6_R_abs_R | function | ||
| 2512 | core::core_arch::hexagon::scalar | Q6_R_abs_R_sat | function | ||
| 2513 | core::core_arch::hexagon::scalar | Q6_R_add_RI | function | ||
| 2514 | core::core_arch::hexagon::scalar | Q6_R_add_RR | function | ||
| 2515 | core::core_arch::hexagon::scalar | Q6_R_add_RR_sat | function | ||
| 2516 | core::core_arch::hexagon::scalar | Q6_R_add_RhRh_s16 | function | ||
| 2517 | core::core_arch::hexagon::scalar | Q6_R_add_RhRh_sat_s16 | function | ||
| 2518 | core::core_arch::hexagon::scalar | Q6_R_add_RhRl_s16 | function | ||
| 2519 | core::core_arch::hexagon::scalar | Q6_R_add_RhRl_sat_s16 | function | ||
| 2520 | core::core_arch::hexagon::scalar | Q6_R_add_RlRh | function | ||
| 2521 | core::core_arch::hexagon::scalar | Q6_R_add_RlRh_s16 | function | ||
| 2522 | core::core_arch::hexagon::scalar | Q6_R_add_RlRh_sat | function | ||
| 2523 | core::core_arch::hexagon::scalar | Q6_R_add_RlRh_sat_s16 | function | ||
| 2524 | core::core_arch::hexagon::scalar | Q6_R_add_RlRl | function | ||
| 2525 | core::core_arch::hexagon::scalar | Q6_R_add_RlRl_s16 | function | ||
| 2526 | core::core_arch::hexagon::scalar | Q6_R_add_RlRl_sat | function | ||
| 2527 | core::core_arch::hexagon::scalar | Q6_R_add_RlRl_sat_s16 | function | ||
| 2528 | core::core_arch::hexagon::scalar | Q6_R_add_add_RRI | function | ||
| 2529 | core::core_arch::hexagon::scalar | Q6_R_add_asl_IRI | function | ||
| 2530 | core::core_arch::hexagon::scalar | Q6_R_add_clb_PI | function | ||
| 2531 | core::core_arch::hexagon::scalar | Q6_R_add_clb_RI | function | ||
| 2532 | core::core_arch::hexagon::scalar | Q6_R_add_lsr_IRI | function | ||
| 2533 | core::core_arch::hexagon::scalar | Q6_R_add_mpyi_IRI | function | ||
| 2534 | core::core_arch::hexagon::scalar | Q6_R_add_mpyi_IRR | function | ||
| 2535 | core::core_arch::hexagon::scalar | Q6_R_add_mpyi_RIR | function | ||
| 2536 | core::core_arch::hexagon::scalar | Q6_R_add_mpyi_RRI | function | ||
| 2537 | core::core_arch::hexagon::scalar | Q6_R_add_mpyi_RRR | function | ||
| 2538 | core::core_arch::hexagon::scalar | Q6_R_add_sub_RIR | function | ||
| 2539 | core::core_arch::hexagon::scalar | Q6_R_addacc_RI | function | ||
| 2540 | core::core_arch::hexagon::scalar | Q6_R_addacc_RR | function | ||
| 2541 | core::core_arch::hexagon::scalar | Q6_R_addasl_RRI | function | ||
| 2542 | core::core_arch::hexagon::scalar | Q6_R_addnac_RI | function | ||
| 2543 | core::core_arch::hexagon::scalar | Q6_R_addnac_RR | function | ||
| 2544 | core::core_arch::hexagon::scalar | Q6_R_and_RI | function | ||
| 2545 | core::core_arch::hexagon::scalar | Q6_R_and_RR | function | ||
| 2546 | core::core_arch::hexagon::scalar | Q6_R_and_RnR | function | ||
| 2547 | core::core_arch::hexagon::scalar | Q6_R_and_asl_IRI | function | ||
| 2548 | core::core_arch::hexagon::scalar | Q6_R_and_lsr_IRI | function | ||
| 2549 | core::core_arch::hexagon::scalar | Q6_R_andand_RR | function | ||
| 2550 | core::core_arch::hexagon::scalar | Q6_R_andand_RnR | function | ||
| 2551 | core::core_arch::hexagon::scalar | Q6_R_andor_RI | function | ||
| 2552 | core::core_arch::hexagon::scalar | Q6_R_andor_RR | function | ||
| 2553 | core::core_arch::hexagon::scalar | Q6_R_andor_RnR | function | ||
| 2554 | core::core_arch::hexagon::scalar | Q6_R_andxacc_RR | function | ||
| 2555 | core::core_arch::hexagon::scalar | Q6_R_andxacc_RnR | function | ||
| 2556 | core::core_arch::hexagon::scalar | Q6_R_asl_RI | function | ||
| 2557 | core::core_arch::hexagon::scalar | Q6_R_asl_RI_sat | function | ||
| 2558 | core::core_arch::hexagon::scalar | Q6_R_asl_RR | function | ||
| 2559 | core::core_arch::hexagon::scalar | Q6_R_asl_RR_sat | function | ||
| 2560 | core::core_arch::hexagon::scalar | Q6_R_aslacc_RI | function | ||
| 2561 | core::core_arch::hexagon::scalar | Q6_R_aslacc_RR | function | ||
| 2562 | core::core_arch::hexagon::scalar | Q6_R_asland_RI | function | ||
| 2563 | core::core_arch::hexagon::scalar | Q6_R_asland_RR | function | ||
| 2564 | core::core_arch::hexagon::scalar | Q6_R_aslh_R | function | ||
| 2565 | core::core_arch::hexagon::scalar | Q6_R_aslnac_RI | function | ||
| 2566 | core::core_arch::hexagon::scalar | Q6_R_aslnac_RR | function | ||
| 2567 | core::core_arch::hexagon::scalar | Q6_R_aslor_RI | function | ||
| 2568 | core::core_arch::hexagon::scalar | Q6_R_aslor_RR | function | ||
| 2569 | core::core_arch::hexagon::scalar | Q6_R_aslxacc_RI | function | ||
| 2570 | core::core_arch::hexagon::scalar | Q6_R_asr_RI | function | ||
| 2571 | core::core_arch::hexagon::scalar | Q6_R_asr_RI_rnd | function | ||
| 2572 | core::core_arch::hexagon::scalar | Q6_R_asr_RR | function | ||
| 2573 | core::core_arch::hexagon::scalar | Q6_R_asr_RR_sat | function | ||
| 2574 | core::core_arch::hexagon::scalar | Q6_R_asracc_RI | function | ||
| 2575 | core::core_arch::hexagon::scalar | Q6_R_asracc_RR | function | ||
| 2576 | core::core_arch::hexagon::scalar | Q6_R_asrand_RI | function | ||
| 2577 | core::core_arch::hexagon::scalar | Q6_R_asrand_RR | function | ||
| 2578 | core::core_arch::hexagon::scalar | Q6_R_asrh_R | function | ||
| 2579 | core::core_arch::hexagon::scalar | Q6_R_asrnac_RI | function | ||
| 2580 | core::core_arch::hexagon::scalar | Q6_R_asrnac_RR | function | ||
| 2581 | core::core_arch::hexagon::scalar | Q6_R_asror_RI | function | ||
| 2582 | core::core_arch::hexagon::scalar | Q6_R_asror_RR | function | ||
| 2583 | core::core_arch::hexagon::scalar | Q6_R_asrrnd_RI | function | ||
| 2584 | core::core_arch::hexagon::scalar | Q6_R_brev_R | function | ||
| 2585 | core::core_arch::hexagon::scalar | Q6_R_cl0_P | function | ||
| 2586 | core::core_arch::hexagon::scalar | Q6_R_cl0_R | function | ||
| 2587 | core::core_arch::hexagon::scalar | Q6_R_cl1_P | function | ||
| 2588 | core::core_arch::hexagon::scalar | Q6_R_cl1_R | function | ||
| 2589 | core::core_arch::hexagon::scalar | Q6_R_clb_P | function | ||
| 2590 | core::core_arch::hexagon::scalar | Q6_R_clb_R | function | ||
| 2591 | core::core_arch::hexagon::scalar | Q6_R_clip_RI | function | ||
| 2592 | core::core_arch::hexagon::scalar | Q6_R_clrbit_RI | function | ||
| 2593 | core::core_arch::hexagon::scalar | Q6_R_clrbit_RR | function | ||
| 2594 | core::core_arch::hexagon::scalar | Q6_R_cmp_eq_RI | function | ||
| 2595 | core::core_arch::hexagon::scalar | Q6_R_cmp_eq_RR | function | ||
| 2596 | core::core_arch::hexagon::scalar | Q6_R_cmpy_RR_conj_rnd_sat | function | ||
| 2597 | core::core_arch::hexagon::scalar | Q6_R_cmpy_RR_conj_s1_rnd_sat | function | ||
| 2598 | core::core_arch::hexagon::scalar | Q6_R_cmpy_RR_rnd_sat | function | ||
| 2599 | core::core_arch::hexagon::scalar | Q6_R_cmpy_RR_s1_rnd_sat | function | ||
| 2600 | core::core_arch::hexagon::scalar | Q6_R_cmpyiw_PP_conj_s1_rnd_sat | function | ||
| 2601 | core::core_arch::hexagon::scalar | Q6_R_cmpyiw_PP_conj_s1_sat | function | ||
| 2602 | core::core_arch::hexagon::scalar | Q6_R_cmpyiw_PP_s1_rnd_sat | function | ||
| 2603 | core::core_arch::hexagon::scalar | Q6_R_cmpyiw_PP_s1_sat | function | ||
| 2604 | core::core_arch::hexagon::scalar | Q6_R_cmpyiwh_PR_conj_s1_rnd_sat | function | ||
| 2605 | core::core_arch::hexagon::scalar | Q6_R_cmpyiwh_PR_s1_rnd_sat | function | ||
| 2606 | core::core_arch::hexagon::scalar | Q6_R_cmpyrw_PP_conj_s1_rnd_sat | function | ||
| 2607 | core::core_arch::hexagon::scalar | Q6_R_cmpyrw_PP_conj_s1_sat | function | ||
| 2608 | core::core_arch::hexagon::scalar | Q6_R_cmpyrw_PP_s1_rnd_sat | function | ||
| 2609 | core::core_arch::hexagon::scalar | Q6_R_cmpyrw_PP_s1_sat | function | ||
| 2610 | core::core_arch::hexagon::scalar | Q6_R_cmpyrwh_PR_conj_s1_rnd_sat | function | ||
| 2611 | core::core_arch::hexagon::scalar | Q6_R_cmpyrwh_PR_s1_rnd_sat | function | ||
| 2612 | core::core_arch::hexagon::scalar | Q6_R_combine_RhRh | function | ||
| 2613 | core::core_arch::hexagon::scalar | Q6_R_combine_RhRl | function | ||
| 2614 | core::core_arch::hexagon::scalar | Q6_R_combine_RlRh | function | ||
| 2615 | core::core_arch::hexagon::scalar | Q6_R_combine_RlRl | function | ||
| 2616 | core::core_arch::hexagon::scalar | Q6_R_convert_d2sf_P | function | ||
| 2617 | core::core_arch::hexagon::scalar | Q6_R_convert_df2sf_P | function | ||
| 2618 | core::core_arch::hexagon::scalar | Q6_R_convert_df2uw_P | function | ||
| 2619 | core::core_arch::hexagon::scalar | Q6_R_convert_df2uw_P_chop | function | ||
| 2620 | core::core_arch::hexagon::scalar | Q6_R_convert_df2w_P | function | ||
| 2621 | core::core_arch::hexagon::scalar | Q6_R_convert_df2w_P_chop | function | ||
| 2622 | core::core_arch::hexagon::scalar | Q6_R_convert_sf2uw_R | function | ||
| 2623 | core::core_arch::hexagon::scalar | Q6_R_convert_sf2uw_R_chop | function | ||
| 2624 | core::core_arch::hexagon::scalar | Q6_R_convert_sf2w_R | function | ||
| 2625 | core::core_arch::hexagon::scalar | Q6_R_convert_sf2w_R_chop | function | ||
| 2626 | core::core_arch::hexagon::scalar | Q6_R_convert_ud2sf_P | function | ||
| 2627 | core::core_arch::hexagon::scalar | Q6_R_convert_uw2sf_R | function | ||
| 2628 | core::core_arch::hexagon::scalar | Q6_R_convert_w2sf_R | function | ||
| 2629 | core::core_arch::hexagon::scalar | Q6_R_cround_RI | function | ||
| 2630 | core::core_arch::hexagon::scalar | Q6_R_cround_RR | function | ||
| 2631 | core::core_arch::hexagon::scalar | Q6_R_ct0_P | function | ||
| 2632 | core::core_arch::hexagon::scalar | Q6_R_ct0_R | function | ||
| 2633 | core::core_arch::hexagon::scalar | Q6_R_ct1_P | function | ||
| 2634 | core::core_arch::hexagon::scalar | Q6_R_ct1_R | function | ||
| 2635 | core::core_arch::hexagon::scalar | Q6_R_dmpause | function | ||
| 2636 | core::core_arch::hexagon::scalar | Q6_R_dmpoll | function | ||
| 2637 | core::core_arch::hexagon::scalar | Q6_R_dmwait | function | ||
| 2638 | core::core_arch::hexagon::scalar | Q6_R_equals_I | function | ||
| 2639 | core::core_arch::hexagon::scalar | Q6_R_equals_R | function | ||
| 2640 | core::core_arch::hexagon::scalar | Q6_R_equals_p | function | ||
| 2641 | core::core_arch::hexagon::scalar | Q6_R_extract_RII | function | ||
| 2642 | core::core_arch::hexagon::scalar | Q6_R_extract_RP | function | ||
| 2643 | core::core_arch::hexagon::scalar | Q6_R_extractu_RII | function | ||
| 2644 | core::core_arch::hexagon::scalar | Q6_R_extractu_RP | function | ||
| 2645 | core::core_arch::hexagon::scalar | Q6_R_insert_RII | function | ||
| 2646 | core::core_arch::hexagon::scalar | Q6_R_insert_RP | function | ||
| 2647 | core::core_arch::hexagon::scalar | Q6_R_lsl_IR | function | ||
| 2648 | core::core_arch::hexagon::scalar | Q6_R_lsl_RR | function | ||
| 2649 | core::core_arch::hexagon::scalar | Q6_R_lslacc_RR | function | ||
| 2650 | core::core_arch::hexagon::scalar | Q6_R_lsland_RR | function | ||
| 2651 | core::core_arch::hexagon::scalar | Q6_R_lslnac_RR | function | ||
| 2652 | core::core_arch::hexagon::scalar | Q6_R_lslor_RR | function | ||
| 2653 | core::core_arch::hexagon::scalar | Q6_R_lsr_RI | function | ||
| 2654 | core::core_arch::hexagon::scalar | Q6_R_lsr_RR | function | ||
| 2655 | core::core_arch::hexagon::scalar | Q6_R_lsracc_RI | function | ||
| 2656 | core::core_arch::hexagon::scalar | Q6_R_lsracc_RR | function | ||
| 2657 | core::core_arch::hexagon::scalar | Q6_R_lsrand_RI | function | ||
| 2658 | core::core_arch::hexagon::scalar | Q6_R_lsrand_RR | function | ||
| 2659 | core::core_arch::hexagon::scalar | Q6_R_lsrnac_RI | function | ||
| 2660 | core::core_arch::hexagon::scalar | Q6_R_lsrnac_RR | function | ||
| 2661 | core::core_arch::hexagon::scalar | Q6_R_lsror_RI | function | ||
| 2662 | core::core_arch::hexagon::scalar | Q6_R_lsror_RR | function | ||
| 2663 | core::core_arch::hexagon::scalar | Q6_R_lsrxacc_RI | function | ||
| 2664 | core::core_arch::hexagon::scalar | Q6_R_mask_II | function | ||
| 2665 | core::core_arch::hexagon::scalar | Q6_R_max_RR | function | ||
| 2666 | core::core_arch::hexagon::scalar | Q6_R_maxu_RR | function | ||
| 2667 | core::core_arch::hexagon::scalar | Q6_R_min_RR | function | ||
| 2668 | core::core_arch::hexagon::scalar | Q6_R_minu_RR | function | ||
| 2669 | core::core_arch::hexagon::scalar | Q6_R_modwrap_RR | function | ||
| 2670 | core::core_arch::hexagon::scalar | Q6_R_mpy_RR | function | ||
| 2671 | core::core_arch::hexagon::scalar | Q6_R_mpy_RR_rnd | function | ||
| 2672 | core::core_arch::hexagon::scalar | Q6_R_mpy_RR_s1 | function | ||
| 2673 | core::core_arch::hexagon::scalar | Q6_R_mpy_RR_s1_sat | function | ||
| 2674 | core::core_arch::hexagon::scalar | Q6_R_mpy_RRh_s1_rnd_sat | function | ||
| 2675 | core::core_arch::hexagon::scalar | Q6_R_mpy_RRh_s1_sat | function | ||
| 2676 | core::core_arch::hexagon::scalar | Q6_R_mpy_RRl_s1_rnd_sat | function | ||
| 2677 | core::core_arch::hexagon::scalar | Q6_R_mpy_RRl_s1_sat | function | ||
| 2678 | core::core_arch::hexagon::scalar | Q6_R_mpy_RhRh | function | ||
| 2679 | core::core_arch::hexagon::scalar | Q6_R_mpy_RhRh_rnd | function | ||
| 2680 | core::core_arch::hexagon::scalar | Q6_R_mpy_RhRh_rnd_sat | function | ||
| 2681 | core::core_arch::hexagon::scalar | Q6_R_mpy_RhRh_s1 | function | ||
| 2682 | core::core_arch::hexagon::scalar | Q6_R_mpy_RhRh_s1_rnd | function | ||
| 2683 | core::core_arch::hexagon::scalar | Q6_R_mpy_RhRh_s1_rnd_sat | function | ||
| 2684 | core::core_arch::hexagon::scalar | Q6_R_mpy_RhRh_s1_sat | function | ||
| 2685 | core::core_arch::hexagon::scalar | Q6_R_mpy_RhRh_sat | function | ||
| 2686 | core::core_arch::hexagon::scalar | Q6_R_mpy_RhRl | function | ||
| 2687 | core::core_arch::hexagon::scalar | Q6_R_mpy_RhRl_rnd | function | ||
| 2688 | core::core_arch::hexagon::scalar | Q6_R_mpy_RhRl_rnd_sat | function | ||
| 2689 | core::core_arch::hexagon::scalar | Q6_R_mpy_RhRl_s1 | function | ||
| 2690 | core::core_arch::hexagon::scalar | Q6_R_mpy_RhRl_s1_rnd | function | ||
| 2691 | core::core_arch::hexagon::scalar | Q6_R_mpy_RhRl_s1_rnd_sat | function | ||
| 2692 | core::core_arch::hexagon::scalar | Q6_R_mpy_RhRl_s1_sat | function | ||
| 2693 | core::core_arch::hexagon::scalar | Q6_R_mpy_RhRl_sat | function | ||
| 2694 | core::core_arch::hexagon::scalar | Q6_R_mpy_RlRh | function | ||
| 2695 | core::core_arch::hexagon::scalar | Q6_R_mpy_RlRh_rnd | function | ||
| 2696 | core::core_arch::hexagon::scalar | Q6_R_mpy_RlRh_rnd_sat | function | ||
| 2697 | core::core_arch::hexagon::scalar | Q6_R_mpy_RlRh_s1 | function | ||
| 2698 | core::core_arch::hexagon::scalar | Q6_R_mpy_RlRh_s1_rnd | function | ||
| 2699 | core::core_arch::hexagon::scalar | Q6_R_mpy_RlRh_s1_rnd_sat | function | ||
| 2700 | core::core_arch::hexagon::scalar | Q6_R_mpy_RlRh_s1_sat | function | ||
| 2701 | core::core_arch::hexagon::scalar | Q6_R_mpy_RlRh_sat | function | ||
| 2702 | core::core_arch::hexagon::scalar | Q6_R_mpy_RlRl | function | ||
| 2703 | core::core_arch::hexagon::scalar | Q6_R_mpy_RlRl_rnd | function | ||
| 2704 | core::core_arch::hexagon::scalar | Q6_R_mpy_RlRl_rnd_sat | function | ||
| 2705 | core::core_arch::hexagon::scalar | Q6_R_mpy_RlRl_s1 | function | ||
| 2706 | core::core_arch::hexagon::scalar | Q6_R_mpy_RlRl_s1_rnd | function | ||
| 2707 | core::core_arch::hexagon::scalar | Q6_R_mpy_RlRl_s1_rnd_sat | function | ||
| 2708 | core::core_arch::hexagon::scalar | Q6_R_mpy_RlRl_s1_sat | function | ||
| 2709 | core::core_arch::hexagon::scalar | Q6_R_mpy_RlRl_sat | function | ||
| 2710 | core::core_arch::hexagon::scalar | Q6_R_mpyacc_RR_s1_sat | function | ||
| 2711 | core::core_arch::hexagon::scalar | Q6_R_mpyacc_RhRh | function | ||
| 2712 | core::core_arch::hexagon::scalar | Q6_R_mpyacc_RhRh_s1 | function | ||
| 2713 | core::core_arch::hexagon::scalar | Q6_R_mpyacc_RhRh_s1_sat | function | ||
| 2714 | core::core_arch::hexagon::scalar | Q6_R_mpyacc_RhRh_sat | function | ||
| 2715 | core::core_arch::hexagon::scalar | Q6_R_mpyacc_RhRl | function | ||
| 2716 | core::core_arch::hexagon::scalar | Q6_R_mpyacc_RhRl_s1 | function | ||
| 2717 | core::core_arch::hexagon::scalar | Q6_R_mpyacc_RhRl_s1_sat | function | ||
| 2718 | core::core_arch::hexagon::scalar | Q6_R_mpyacc_RhRl_sat | function | ||
| 2719 | core::core_arch::hexagon::scalar | Q6_R_mpyacc_RlRh | function | ||
| 2720 | core::core_arch::hexagon::scalar | Q6_R_mpyacc_RlRh_s1 | function | ||
| 2721 | core::core_arch::hexagon::scalar | Q6_R_mpyacc_RlRh_s1_sat | function | ||
| 2722 | core::core_arch::hexagon::scalar | Q6_R_mpyacc_RlRh_sat | function | ||
| 2723 | core::core_arch::hexagon::scalar | Q6_R_mpyacc_RlRl | function | ||
| 2724 | core::core_arch::hexagon::scalar | Q6_R_mpyacc_RlRl_s1 | function | ||
| 2725 | core::core_arch::hexagon::scalar | Q6_R_mpyacc_RlRl_s1_sat | function | ||
| 2726 | core::core_arch::hexagon::scalar | Q6_R_mpyacc_RlRl_sat | function | ||
| 2727 | core::core_arch::hexagon::scalar | Q6_R_mpyi_RI | function | ||
| 2728 | core::core_arch::hexagon::scalar | Q6_R_mpyi_RR | function | ||
| 2729 | core::core_arch::hexagon::scalar | Q6_R_mpyiacc_RI | function | ||
| 2730 | core::core_arch::hexagon::scalar | Q6_R_mpyiacc_RR | function | ||
| 2731 | core::core_arch::hexagon::scalar | Q6_R_mpyinac_RI | function | ||
| 2732 | core::core_arch::hexagon::scalar | Q6_R_mpyinac_RR | function | ||
| 2733 | core::core_arch::hexagon::scalar | Q6_R_mpynac_RR_s1_sat | function | ||
| 2734 | core::core_arch::hexagon::scalar | Q6_R_mpynac_RhRh | function | ||
| 2735 | core::core_arch::hexagon::scalar | Q6_R_mpynac_RhRh_s1 | function | ||
| 2736 | core::core_arch::hexagon::scalar | Q6_R_mpynac_RhRh_s1_sat | function | ||
| 2737 | core::core_arch::hexagon::scalar | Q6_R_mpynac_RhRh_sat | function | ||
| 2738 | core::core_arch::hexagon::scalar | Q6_R_mpynac_RhRl | function | ||
| 2739 | core::core_arch::hexagon::scalar | Q6_R_mpynac_RhRl_s1 | function | ||
| 2740 | core::core_arch::hexagon::scalar | Q6_R_mpynac_RhRl_s1_sat | function | ||
| 2741 | core::core_arch::hexagon::scalar | Q6_R_mpynac_RhRl_sat | function | ||
| 2742 | core::core_arch::hexagon::scalar | Q6_R_mpynac_RlRh | function | ||
| 2743 | core::core_arch::hexagon::scalar | Q6_R_mpynac_RlRh_s1 | function | ||
| 2744 | core::core_arch::hexagon::scalar | Q6_R_mpynac_RlRh_s1_sat | function | ||
| 2745 | core::core_arch::hexagon::scalar | Q6_R_mpynac_RlRh_sat | function | ||
| 2746 | core::core_arch::hexagon::scalar | Q6_R_mpynac_RlRl | function | ||
| 2747 | core::core_arch::hexagon::scalar | Q6_R_mpynac_RlRl_s1 | function | ||
| 2748 | core::core_arch::hexagon::scalar | Q6_R_mpynac_RlRl_s1_sat | function | ||
| 2749 | core::core_arch::hexagon::scalar | Q6_R_mpynac_RlRl_sat | function | ||
| 2750 | core::core_arch::hexagon::scalar | Q6_R_mpysu_RR | function | ||
| 2751 | core::core_arch::hexagon::scalar | Q6_R_mpyu_RR | function | ||
| 2752 | core::core_arch::hexagon::scalar | Q6_R_mpyu_RhRh | function | ||
| 2753 | core::core_arch::hexagon::scalar | Q6_R_mpyu_RhRh_s1 | function | ||
| 2754 | core::core_arch::hexagon::scalar | Q6_R_mpyu_RhRl | function | ||
| 2755 | core::core_arch::hexagon::scalar | Q6_R_mpyu_RhRl_s1 | function | ||
| 2756 | core::core_arch::hexagon::scalar | Q6_R_mpyu_RlRh | function | ||
| 2757 | core::core_arch::hexagon::scalar | Q6_R_mpyu_RlRh_s1 | function | ||
| 2758 | core::core_arch::hexagon::scalar | Q6_R_mpyu_RlRl | function | ||
| 2759 | core::core_arch::hexagon::scalar | Q6_R_mpyu_RlRl_s1 | function | ||
| 2760 | core::core_arch::hexagon::scalar | Q6_R_mpyuacc_RhRh | function | ||
| 2761 | core::core_arch::hexagon::scalar | Q6_R_mpyuacc_RhRh_s1 | function | ||
| 2762 | core::core_arch::hexagon::scalar | Q6_R_mpyuacc_RhRl | function | ||
| 2763 | core::core_arch::hexagon::scalar | Q6_R_mpyuacc_RhRl_s1 | function | ||
| 2764 | core::core_arch::hexagon::scalar | Q6_R_mpyuacc_RlRh | function | ||
| 2765 | core::core_arch::hexagon::scalar | Q6_R_mpyuacc_RlRh_s1 | function | ||
| 2766 | core::core_arch::hexagon::scalar | Q6_R_mpyuacc_RlRl | function | ||
| 2767 | core::core_arch::hexagon::scalar | Q6_R_mpyuacc_RlRl_s1 | function | ||
| 2768 | core::core_arch::hexagon::scalar | Q6_R_mpyui_RR | function | ||
| 2769 | core::core_arch::hexagon::scalar | Q6_R_mpyunac_RhRh | function | ||
| 2770 | core::core_arch::hexagon::scalar | Q6_R_mpyunac_RhRh_s1 | function | ||
| 2771 | core::core_arch::hexagon::scalar | Q6_R_mpyunac_RhRl | function | ||
| 2772 | core::core_arch::hexagon::scalar | Q6_R_mpyunac_RhRl_s1 | function | ||
| 2773 | core::core_arch::hexagon::scalar | Q6_R_mpyunac_RlRh | function | ||
| 2774 | core::core_arch::hexagon::scalar | Q6_R_mpyunac_RlRh_s1 | function | ||
| 2775 | core::core_arch::hexagon::scalar | Q6_R_mpyunac_RlRl | function | ||
| 2776 | core::core_arch::hexagon::scalar | Q6_R_mpyunac_RlRl_s1 | function | ||
| 2777 | core::core_arch::hexagon::scalar | Q6_R_mux_pII | function | ||
| 2778 | core::core_arch::hexagon::scalar | Q6_R_mux_pIR | function | ||
| 2779 | core::core_arch::hexagon::scalar | Q6_R_mux_pRI | function | ||
| 2780 | core::core_arch::hexagon::scalar | Q6_R_mux_pRR | function | ||
| 2781 | core::core_arch::hexagon::scalar | Q6_R_neg_R | function | ||
| 2782 | core::core_arch::hexagon::scalar | Q6_R_neg_R_sat | function | ||
| 2783 | core::core_arch::hexagon::scalar | Q6_R_normamt_P | function | ||
| 2784 | core::core_arch::hexagon::scalar | Q6_R_normamt_R | function | ||
| 2785 | core::core_arch::hexagon::scalar | Q6_R_not_R | function | ||
| 2786 | core::core_arch::hexagon::scalar | Q6_R_not_cmp_eq_RI | function | ||
| 2787 | core::core_arch::hexagon::scalar | Q6_R_not_cmp_eq_RR | function | ||
| 2788 | core::core_arch::hexagon::scalar | Q6_R_or_RI | function | ||
| 2789 | core::core_arch::hexagon::scalar | Q6_R_or_RR | function | ||
| 2790 | core::core_arch::hexagon::scalar | Q6_R_or_RnR | function | ||
| 2791 | core::core_arch::hexagon::scalar | Q6_R_or_and_RRI | function | ||
| 2792 | core::core_arch::hexagon::scalar | Q6_R_or_asl_IRI | function | ||
| 2793 | core::core_arch::hexagon::scalar | Q6_R_or_lsr_IRI | function | ||
| 2794 | core::core_arch::hexagon::scalar | Q6_R_orand_RR | function | ||
| 2795 | core::core_arch::hexagon::scalar | Q6_R_oror_RI | function | ||
| 2796 | core::core_arch::hexagon::scalar | Q6_R_oror_RR | function | ||
| 2797 | core::core_arch::hexagon::scalar | Q6_R_orxacc_RR | function | ||
| 2798 | core::core_arch::hexagon::scalar | Q6_R_parity_PP | function | ||
| 2799 | core::core_arch::hexagon::scalar | Q6_R_parity_RR | function | ||
| 2800 | core::core_arch::hexagon::scalar | Q6_R_popcount_P | function | ||
| 2801 | core::core_arch::hexagon::scalar | Q6_R_rol_RI | function | ||
| 2802 | core::core_arch::hexagon::scalar | Q6_R_rolacc_RI | function | ||
| 2803 | core::core_arch::hexagon::scalar | Q6_R_roland_RI | function | ||
| 2804 | core::core_arch::hexagon::scalar | Q6_R_rolnac_RI | function | ||
| 2805 | core::core_arch::hexagon::scalar | Q6_R_rolor_RI | function | ||
| 2806 | core::core_arch::hexagon::scalar | Q6_R_rolxacc_RI | function | ||
| 2807 | core::core_arch::hexagon::scalar | Q6_R_round_P_sat | function | ||
| 2808 | core::core_arch::hexagon::scalar | Q6_R_round_RI | function | ||
| 2809 | core::core_arch::hexagon::scalar | Q6_R_round_RI_sat | function | ||
| 2810 | core::core_arch::hexagon::scalar | Q6_R_round_RR | function | ||
| 2811 | core::core_arch::hexagon::scalar | Q6_R_round_RR_sat | function | ||
| 2812 | core::core_arch::hexagon::scalar | Q6_R_sat_P | function | ||
| 2813 | core::core_arch::hexagon::scalar | Q6_R_satb_R | function | ||
| 2814 | core::core_arch::hexagon::scalar | Q6_R_sath_R | function | ||
| 2815 | core::core_arch::hexagon::scalar | Q6_R_satub_R | function | ||
| 2816 | core::core_arch::hexagon::scalar | Q6_R_satuh_R | function | ||
| 2817 | core::core_arch::hexagon::scalar | Q6_R_setbit_RI | function | ||
| 2818 | core::core_arch::hexagon::scalar | Q6_R_setbit_RR | function | ||
| 2819 | core::core_arch::hexagon::scalar | Q6_R_sfadd_RR | function | ||
| 2820 | core::core_arch::hexagon::scalar | Q6_R_sffixupd_RR | function | ||
| 2821 | core::core_arch::hexagon::scalar | Q6_R_sffixupn_RR | function | ||
| 2822 | core::core_arch::hexagon::scalar | Q6_R_sffixupr_R | function | ||
| 2823 | core::core_arch::hexagon::scalar | Q6_R_sfmake_I_neg | function | ||
| 2824 | core::core_arch::hexagon::scalar | Q6_R_sfmake_I_pos | function | ||
| 2825 | core::core_arch::hexagon::scalar | Q6_R_sfmax_RR | function | ||
| 2826 | core::core_arch::hexagon::scalar | Q6_R_sfmin_RR | function | ||
| 2827 | core::core_arch::hexagon::scalar | Q6_R_sfmpy_RR | function | ||
| 2828 | core::core_arch::hexagon::scalar | Q6_R_sfmpyacc_RR | function | ||
| 2829 | core::core_arch::hexagon::scalar | Q6_R_sfmpyacc_RR_lib | function | ||
| 2830 | core::core_arch::hexagon::scalar | Q6_R_sfmpyacc_RRp_scale | function | ||
| 2831 | core::core_arch::hexagon::scalar | Q6_R_sfmpynac_RR | function | ||
| 2832 | core::core_arch::hexagon::scalar | Q6_R_sfmpynac_RR_lib | function | ||
| 2833 | core::core_arch::hexagon::scalar | Q6_R_sfsub_RR | function | ||
| 2834 | core::core_arch::hexagon::scalar | Q6_R_sub_IR | function | ||
| 2835 | core::core_arch::hexagon::scalar | Q6_R_sub_RR | function | ||
| 2836 | core::core_arch::hexagon::scalar | Q6_R_sub_RR_sat | function | ||
| 2837 | core::core_arch::hexagon::scalar | Q6_R_sub_RhRh_s16 | function | ||
| 2838 | core::core_arch::hexagon::scalar | Q6_R_sub_RhRh_sat_s16 | function | ||
| 2839 | core::core_arch::hexagon::scalar | Q6_R_sub_RhRl_s16 | function | ||
| 2840 | core::core_arch::hexagon::scalar | Q6_R_sub_RhRl_sat_s16 | function | ||
| 2841 | core::core_arch::hexagon::scalar | Q6_R_sub_RlRh | function | ||
| 2842 | core::core_arch::hexagon::scalar | Q6_R_sub_RlRh_s16 | function | ||
| 2843 | core::core_arch::hexagon::scalar | Q6_R_sub_RlRh_sat | function | ||
| 2844 | core::core_arch::hexagon::scalar | Q6_R_sub_RlRh_sat_s16 | function | ||
| 2845 | core::core_arch::hexagon::scalar | Q6_R_sub_RlRl | function | ||
| 2846 | core::core_arch::hexagon::scalar | Q6_R_sub_RlRl_s16 | function | ||
| 2847 | core::core_arch::hexagon::scalar | Q6_R_sub_RlRl_sat | function | ||
| 2848 | core::core_arch::hexagon::scalar | Q6_R_sub_RlRl_sat_s16 | function | ||
| 2849 | core::core_arch::hexagon::scalar | Q6_R_sub_asl_IRI | function | ||
| 2850 | core::core_arch::hexagon::scalar | Q6_R_sub_lsr_IRI | function | ||
| 2851 | core::core_arch::hexagon::scalar | Q6_R_subacc_RR | function | ||
| 2852 | core::core_arch::hexagon::scalar | Q6_R_swiz_R | function | ||
| 2853 | core::core_arch::hexagon::scalar | Q6_R_sxtb_R | function | ||
| 2854 | core::core_arch::hexagon::scalar | Q6_R_sxth_R | function | ||
| 2855 | core::core_arch::hexagon::scalar | Q6_R_tableidxb_RII | function | ||
| 2856 | core::core_arch::hexagon::scalar | Q6_R_tableidxd_RII | function | ||
| 2857 | core::core_arch::hexagon::scalar | Q6_R_tableidxh_RII | function | ||
| 2858 | core::core_arch::hexagon::scalar | Q6_R_tableidxw_RII | function | ||
| 2859 | core::core_arch::hexagon::scalar | Q6_R_togglebit_RI | function | ||
| 2860 | core::core_arch::hexagon::scalar | Q6_R_togglebit_RR | function | ||
| 2861 | core::core_arch::hexagon::scalar | Q6_R_vaddh_RR | function | ||
| 2862 | core::core_arch::hexagon::scalar | Q6_R_vaddh_RR_sat | function | ||
| 2863 | core::core_arch::hexagon::scalar | Q6_R_vaddhub_PP_sat | function | ||
| 2864 | core::core_arch::hexagon::scalar | Q6_R_vadduh_RR_sat | function | ||
| 2865 | core::core_arch::hexagon::scalar | Q6_R_vasrhub_PI_rnd_sat | function | ||
| 2866 | core::core_arch::hexagon::scalar | Q6_R_vasrhub_PI_sat | function | ||
| 2867 | core::core_arch::hexagon::scalar | Q6_R_vasrw_PI | function | ||
| 2868 | core::core_arch::hexagon::scalar | Q6_R_vasrw_PR | function | ||
| 2869 | core::core_arch::hexagon::scalar | Q6_R_vavgh_RR | function | ||
| 2870 | core::core_arch::hexagon::scalar | Q6_R_vavgh_RR_rnd | function | ||
| 2871 | core::core_arch::hexagon::scalar | Q6_R_vdmpy_PP_rnd_sat | function | ||
| 2872 | core::core_arch::hexagon::scalar | Q6_R_vdmpy_PP_s1_rnd_sat | function | ||
| 2873 | core::core_arch::hexagon::scalar | Q6_R_vitpack_pp | function | ||
| 2874 | core::core_arch::hexagon::scalar | Q6_R_vmpyh_RR_rnd_sat | function | ||
| 2875 | core::core_arch::hexagon::scalar | Q6_R_vmpyh_RR_s1_rnd_sat | function | ||
| 2876 | core::core_arch::hexagon::scalar | Q6_R_vnavgh_RR | function | ||
| 2877 | core::core_arch::hexagon::scalar | Q6_R_vraddh_PP | function | ||
| 2878 | core::core_arch::hexagon::scalar | Q6_R_vradduh_PP | function | ||
| 2879 | core::core_arch::hexagon::scalar | Q6_R_vrcmpys_PR_s1_rnd_sat | function | ||
| 2880 | core::core_arch::hexagon::scalar | Q6_R_vrndwh_P | function | ||
| 2881 | core::core_arch::hexagon::scalar | Q6_R_vrndwh_P_sat | function | ||
| 2882 | core::core_arch::hexagon::scalar | Q6_R_vsathb_P | function | ||
| 2883 | core::core_arch::hexagon::scalar | Q6_R_vsathb_R | function | ||
| 2884 | core::core_arch::hexagon::scalar | Q6_R_vsathub_P | function | ||
| 2885 | core::core_arch::hexagon::scalar | Q6_R_vsathub_R | function | ||
| 2886 | core::core_arch::hexagon::scalar | Q6_R_vsatwh_P | function | ||
| 2887 | core::core_arch::hexagon::scalar | Q6_R_vsatwuh_P | function | ||
| 2888 | core::core_arch::hexagon::scalar | Q6_R_vsplatb_R | function | ||
| 2889 | core::core_arch::hexagon::scalar | Q6_R_vsubh_RR | function | ||
| 2890 | core::core_arch::hexagon::scalar | Q6_R_vsubh_RR_sat | function | ||
| 2891 | core::core_arch::hexagon::scalar | Q6_R_vsubuh_RR_sat | function | ||
| 2892 | core::core_arch::hexagon::scalar | Q6_R_vtrunehb_P | function | ||
| 2893 | core::core_arch::hexagon::scalar | Q6_R_vtrunohb_P | function | ||
| 2894 | core::core_arch::hexagon::scalar | Q6_R_xor_RR | function | ||
| 2895 | core::core_arch::hexagon::scalar | Q6_R_xorand_RR | function | ||
| 2896 | core::core_arch::hexagon::scalar | Q6_R_xoror_RR | function | ||
| 2897 | core::core_arch::hexagon::scalar | Q6_R_xorxacc_RR | function | ||
| 2898 | core::core_arch::hexagon::scalar | Q6_R_zxtb_R | function | ||
| 2899 | core::core_arch::hexagon::scalar | Q6_R_zxth_R | function | ||
| 2900 | core::core_arch::hexagon::scalar | Q6_Rh_equals_I | function | ||
| 2901 | core::core_arch::hexagon::scalar | Q6_Rl_equals_I | function | ||
| 2902 | core::core_arch::hexagon::scalar | Q6_dccleana_A | function | ||
| 2903 | core::core_arch::hexagon::scalar | Q6_dccleaninva_A | function | ||
| 2904 | core::core_arch::hexagon::scalar | Q6_dcfetch_A | function | ||
| 2905 | core::core_arch::hexagon::scalar | Q6_dcinva_A | function | ||
| 2906 | core::core_arch::hexagon::scalar | Q6_dczeroa_A | function | ||
| 2907 | core::core_arch::hexagon::scalar | Q6_dmlink_AA | function | ||
| 2908 | core::core_arch::hexagon::scalar | Q6_dmresume_A | function | ||
| 2909 | core::core_arch::hexagon::scalar | Q6_dmstart_A | function | ||
| 2910 | core::core_arch::hexagon::scalar | Q6_l2fetch_AP | function | ||
| 2911 | core::core_arch::hexagon::scalar | Q6_l2fetch_AR | function | ||
| 2912 | core::core_arch::hexagon::scalar | Q6_p_all8_p | function | ||
| 2913 | core::core_arch::hexagon::scalar | Q6_p_and_and_ppnp | function | ||
| 2914 | core::core_arch::hexagon::scalar | Q6_p_and_and_ppp | function | ||
| 2915 | core::core_arch::hexagon::scalar | Q6_p_and_or_ppnp | function | ||
| 2916 | core::core_arch::hexagon::scalar | Q6_p_and_or_ppp | function | ||
| 2917 | core::core_arch::hexagon::scalar | Q6_p_and_pnp | function | ||
| 2918 | core::core_arch::hexagon::scalar | Q6_p_and_pp | function | ||
| 2919 | core::core_arch::hexagon::scalar | Q6_p_any8_p | function | ||
| 2920 | core::core_arch::hexagon::scalar | Q6_p_any8_vcmpb_eq_PP | function | ||
| 2921 | core::core_arch::hexagon::scalar | Q6_p_bitsclr_RI | function | ||
| 2922 | core::core_arch::hexagon::scalar | Q6_p_bitsclr_RR | function | ||
| 2923 | core::core_arch::hexagon::scalar | Q6_p_bitsset_RR | function | ||
| 2924 | core::core_arch::hexagon::scalar | Q6_p_boundscheck_RP | function | ||
| 2925 | core::core_arch::hexagon::scalar | Q6_p_cmp_eq_PP | function | ||
| 2926 | core::core_arch::hexagon::scalar | Q6_p_cmp_eq_RI | function | ||
| 2927 | core::core_arch::hexagon::scalar | Q6_p_cmp_eq_RR | function | ||
| 2928 | core::core_arch::hexagon::scalar | Q6_p_cmp_ge_RI | function | ||
| 2929 | core::core_arch::hexagon::scalar | Q6_p_cmp_geu_RI | function | ||
| 2930 | core::core_arch::hexagon::scalar | Q6_p_cmp_gt_PP | function | ||
| 2931 | core::core_arch::hexagon::scalar | Q6_p_cmp_gt_RI | function | ||
| 2932 | core::core_arch::hexagon::scalar | Q6_p_cmp_gt_RR | function | ||
| 2933 | core::core_arch::hexagon::scalar | Q6_p_cmp_gtu_PP | function | ||
| 2934 | core::core_arch::hexagon::scalar | Q6_p_cmp_gtu_RI | function | ||
| 2935 | core::core_arch::hexagon::scalar | Q6_p_cmp_gtu_RR | function | ||
| 2936 | core::core_arch::hexagon::scalar | Q6_p_cmp_lt_RR | function | ||
| 2937 | core::core_arch::hexagon::scalar | Q6_p_cmp_ltu_RR | function | ||
| 2938 | core::core_arch::hexagon::scalar | Q6_p_cmpb_eq_RI | function | ||
| 2939 | core::core_arch::hexagon::scalar | Q6_p_cmpb_eq_RR | function | ||
| 2940 | core::core_arch::hexagon::scalar | Q6_p_cmpb_gt_RI | function | ||
| 2941 | core::core_arch::hexagon::scalar | Q6_p_cmpb_gt_RR | function | ||
| 2942 | core::core_arch::hexagon::scalar | Q6_p_cmpb_gtu_RI | function | ||
| 2943 | core::core_arch::hexagon::scalar | Q6_p_cmpb_gtu_RR | function | ||
| 2944 | core::core_arch::hexagon::scalar | Q6_p_cmph_eq_RI | function | ||
| 2945 | core::core_arch::hexagon::scalar | Q6_p_cmph_eq_RR | function | ||
| 2946 | core::core_arch::hexagon::scalar | Q6_p_cmph_gt_RI | function | ||
| 2947 | core::core_arch::hexagon::scalar | Q6_p_cmph_gt_RR | function | ||
| 2948 | core::core_arch::hexagon::scalar | Q6_p_cmph_gtu_RI | function | ||
| 2949 | core::core_arch::hexagon::scalar | Q6_p_cmph_gtu_RR | function | ||
| 2950 | core::core_arch::hexagon::scalar | Q6_p_dfclass_PI | function | ||
| 2951 | core::core_arch::hexagon::scalar | Q6_p_dfcmp_eq_PP | function | ||
| 2952 | core::core_arch::hexagon::scalar | Q6_p_dfcmp_ge_PP | function | ||
| 2953 | core::core_arch::hexagon::scalar | Q6_p_dfcmp_gt_PP | function | ||
| 2954 | core::core_arch::hexagon::scalar | Q6_p_dfcmp_uo_PP | function | ||
| 2955 | core::core_arch::hexagon::scalar | Q6_p_equals_R | function | ||
| 2956 | core::core_arch::hexagon::scalar | Q6_p_equals_p | function | ||
| 2957 | core::core_arch::hexagon::scalar | Q6_p_fastcorner9_pp | function | ||
| 2958 | core::core_arch::hexagon::scalar | Q6_p_not_any8_vcmpb_eq_PP | function | ||
| 2959 | core::core_arch::hexagon::scalar | Q6_p_not_bitsclr_RI | function | ||
| 2960 | core::core_arch::hexagon::scalar | Q6_p_not_bitsclr_RR | function | ||
| 2961 | core::core_arch::hexagon::scalar | Q6_p_not_bitsset_RR | function | ||
| 2962 | core::core_arch::hexagon::scalar | Q6_p_not_cmp_eq_RI | function | ||
| 2963 | core::core_arch::hexagon::scalar | Q6_p_not_cmp_eq_RR | function | ||
| 2964 | core::core_arch::hexagon::scalar | Q6_p_not_cmp_gt_RI | function | ||
| 2965 | core::core_arch::hexagon::scalar | Q6_p_not_cmp_gt_RR | function | ||
| 2966 | core::core_arch::hexagon::scalar | Q6_p_not_cmp_gtu_RI | function | ||
| 2967 | core::core_arch::hexagon::scalar | Q6_p_not_cmp_gtu_RR | function | ||
| 2968 | core::core_arch::hexagon::scalar | Q6_p_not_fastcorner9_pp | function | ||
| 2969 | core::core_arch::hexagon::scalar | Q6_p_not_p | function | ||
| 2970 | core::core_arch::hexagon::scalar | Q6_p_not_tstbit_RI | function | ||
| 2971 | core::core_arch::hexagon::scalar | Q6_p_not_tstbit_RR | function | ||
| 2972 | core::core_arch::hexagon::scalar | Q6_p_or_and_ppnp | function | ||
| 2973 | core::core_arch::hexagon::scalar | Q6_p_or_and_ppp | function | ||
| 2974 | core::core_arch::hexagon::scalar | Q6_p_or_or_ppnp | function | ||
| 2975 | core::core_arch::hexagon::scalar | Q6_p_or_or_ppp | function | ||
| 2976 | core::core_arch::hexagon::scalar | Q6_p_or_pnp | function | ||
| 2977 | core::core_arch::hexagon::scalar | Q6_p_or_pp | function | ||
| 2978 | core::core_arch::hexagon::scalar | Q6_p_sfclass_RI | function | ||
| 2979 | core::core_arch::hexagon::scalar | Q6_p_sfcmp_eq_RR | function | ||
| 2980 | core::core_arch::hexagon::scalar | Q6_p_sfcmp_ge_RR | function | ||
| 2981 | core::core_arch::hexagon::scalar | Q6_p_sfcmp_gt_RR | function | ||
| 2982 | core::core_arch::hexagon::scalar | Q6_p_sfcmp_uo_RR | function | ||
| 2983 | core::core_arch::hexagon::scalar | Q6_p_tlbmatch_PR | function | ||
| 2984 | core::core_arch::hexagon::scalar | Q6_p_tstbit_RI | function | ||
| 2985 | core::core_arch::hexagon::scalar | Q6_p_tstbit_RR | function | ||
| 2986 | core::core_arch::hexagon::scalar | Q6_p_vcmpb_eq_PI | function | ||
| 2987 | core::core_arch::hexagon::scalar | Q6_p_vcmpb_eq_PP | function | ||
| 2988 | core::core_arch::hexagon::scalar | Q6_p_vcmpb_gt_PI | function | ||
| 2989 | core::core_arch::hexagon::scalar | Q6_p_vcmpb_gt_PP | function | ||
| 2990 | core::core_arch::hexagon::scalar | Q6_p_vcmpb_gtu_PI | function | ||
| 2991 | core::core_arch::hexagon::scalar | Q6_p_vcmpb_gtu_PP | function | ||
| 2992 | core::core_arch::hexagon::scalar | Q6_p_vcmph_eq_PI | function | ||
| 2993 | core::core_arch::hexagon::scalar | Q6_p_vcmph_eq_PP | function | ||
| 2994 | core::core_arch::hexagon::scalar | Q6_p_vcmph_gt_PI | function | ||
| 2995 | core::core_arch::hexagon::scalar | Q6_p_vcmph_gt_PP | function | ||
| 2996 | core::core_arch::hexagon::scalar | Q6_p_vcmph_gtu_PI | function | ||
| 2997 | core::core_arch::hexagon::scalar | Q6_p_vcmph_gtu_PP | function | ||
| 2998 | core::core_arch::hexagon::scalar | Q6_p_vcmpw_eq_PI | function | ||
| 2999 | core::core_arch::hexagon::scalar | Q6_p_vcmpw_eq_PP | function | ||
| 3000 | core::core_arch::hexagon::scalar | Q6_p_vcmpw_gt_PI | function | ||
| 3001 | core::core_arch::hexagon::scalar | Q6_p_vcmpw_gt_PP | function | ||
| 3002 | core::core_arch::hexagon::scalar | Q6_p_vcmpw_gtu_PI | function | ||
| 3003 | core::core_arch::hexagon::scalar | Q6_p_vcmpw_gtu_PP | function | ||
| 3004 | core::core_arch::hexagon::scalar | Q6_p_xor_pp | function | ||
| 3005 | core::core_arch::hexagon::v128 | Q6_Q_and_QQ | function | ||
| 3006 | core::core_arch::hexagon::v128 | Q6_Q_and_QQn | function | ||
| 3007 | core::core_arch::hexagon::v128 | Q6_Q_not_Q | function | ||
| 3008 | core::core_arch::hexagon::v128 | Q6_Q_or_QQ | function | ||
| 3009 | core::core_arch::hexagon::v128 | Q6_Q_or_QQn | function | ||
| 3010 | core::core_arch::hexagon::v128 | Q6_Q_vand_VR | function | ||
| 3011 | core::core_arch::hexagon::v128 | Q6_Q_vandor_QVR | function | ||
| 3012 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_eq_VbVb | function | ||
| 3013 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_eq_VhVh | function | ||
| 3014 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_eq_VwVw | function | ||
| 3015 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_eqand_QVbVb | function | ||
| 3016 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_eqand_QVhVh | function | ||
| 3017 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_eqand_QVwVw | function | ||
| 3018 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_eqor_QVbVb | function | ||
| 3019 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_eqor_QVhVh | function | ||
| 3020 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_eqor_QVwVw | function | ||
| 3021 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_eqxacc_QVbVb | function | ||
| 3022 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_eqxacc_QVhVh | function | ||
| 3023 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_eqxacc_QVwVw | function | ||
| 3024 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_gt_VbVb | function | ||
| 3025 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_gt_VhVh | function | ||
| 3026 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_gt_VhfVhf | function | ||
| 3027 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_gt_VsfVsf | function | ||
| 3028 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_gt_VubVub | function | ||
| 3029 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_gt_VuhVuh | function | ||
| 3030 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_gt_VuwVuw | function | ||
| 3031 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_gt_VwVw | function | ||
| 3032 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_gtand_QVbVb | function | ||
| 3033 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_gtand_QVhVh | function | ||
| 3034 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_gtand_QVhfVhf | function | ||
| 3035 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_gtand_QVsfVsf | function | ||
| 3036 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_gtand_QVubVub | function | ||
| 3037 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_gtand_QVuhVuh | function | ||
| 3038 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_gtand_QVuwVuw | function | ||
| 3039 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_gtand_QVwVw | function | ||
| 3040 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_gtor_QVbVb | function | ||
| 3041 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_gtor_QVhVh | function | ||
| 3042 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_gtor_QVhfVhf | function | ||
| 3043 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_gtor_QVsfVsf | function | ||
| 3044 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_gtor_QVubVub | function | ||
| 3045 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_gtor_QVuhVuh | function | ||
| 3046 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_gtor_QVuwVuw | function | ||
| 3047 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_gtor_QVwVw | function | ||
| 3048 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_gtxacc_QVbVb | function | ||
| 3049 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_gtxacc_QVhVh | function | ||
| 3050 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_gtxacc_QVhfVhf | function | ||
| 3051 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_gtxacc_QVsfVsf | function | ||
| 3052 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_gtxacc_QVubVub | function | ||
| 3053 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_gtxacc_QVuhVuh | function | ||
| 3054 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_gtxacc_QVuwVuw | function | ||
| 3055 | core::core_arch::hexagon::v128 | Q6_Q_vcmp_gtxacc_QVwVw | function | ||
| 3056 | core::core_arch::hexagon::v128 | Q6_Q_vsetq2_R | function | ||
| 3057 | core::core_arch::hexagon::v128 | Q6_Q_vsetq_R | function | ||
| 3058 | core::core_arch::hexagon::v128 | Q6_Q_xor_QQ | function | ||
| 3059 | core::core_arch::hexagon::v128 | Q6_Qb_vshuffe_QhQh | function | ||
| 3060 | core::core_arch::hexagon::v128 | Q6_Qh_vshuffe_QwQw | function | ||
| 3061 | core::core_arch::hexagon::v128 | Q6_R_vextract_VR | function | ||
| 3062 | core::core_arch::hexagon::v128 | Q6_V_equals_V | function | ||
| 3063 | core::core_arch::hexagon::v128 | Q6_V_hi_W | function | ||
| 3064 | core::core_arch::hexagon::v128 | Q6_V_lo_W | function | ||
| 3065 | core::core_arch::hexagon::v128 | Q6_V_vabs_V | function | ||
| 3066 | core::core_arch::hexagon::v128 | Q6_V_valign_VVI | function | ||
| 3067 | core::core_arch::hexagon::v128 | Q6_V_valign_VVR | function | ||
| 3068 | core::core_arch::hexagon::v128 | Q6_V_vand_QR | function | ||
| 3069 | core::core_arch::hexagon::v128 | Q6_V_vand_QV | function | ||
| 3070 | core::core_arch::hexagon::v128 | Q6_V_vand_QnR | function | ||
| 3071 | core::core_arch::hexagon::v128 | Q6_V_vand_QnV | function | ||
| 3072 | core::core_arch::hexagon::v128 | Q6_V_vand_VV | function | ||
| 3073 | core::core_arch::hexagon::v128 | Q6_V_vandor_VQR | function | ||
| 3074 | core::core_arch::hexagon::v128 | Q6_V_vandor_VQnR | function | ||
| 3075 | core::core_arch::hexagon::v128 | Q6_V_vdelta_VV | function | ||
| 3076 | core::core_arch::hexagon::v128 | Q6_V_vfmax_VV | function | ||
| 3077 | core::core_arch::hexagon::v128 | Q6_V_vfmin_VV | function | ||
| 3078 | core::core_arch::hexagon::v128 | Q6_V_vfneg_V | function | ||
| 3079 | core::core_arch::hexagon::v128 | Q6_V_vgetqfext_VR | function | ||
| 3080 | core::core_arch::hexagon::v128 | Q6_V_vlalign_VVI | function | ||
| 3081 | core::core_arch::hexagon::v128 | Q6_V_vlalign_VVR | function | ||
| 3082 | core::core_arch::hexagon::v128 | Q6_V_vmux_QVV | function | ||
| 3083 | core::core_arch::hexagon::v128 | Q6_V_vnot_V | function | ||
| 3084 | core::core_arch::hexagon::v128 | Q6_V_vor_VV | function | ||
| 3085 | core::core_arch::hexagon::v128 | Q6_V_vrdelta_VV | function | ||
| 3086 | core::core_arch::hexagon::v128 | Q6_V_vror_VR | function | ||
| 3087 | core::core_arch::hexagon::v128 | Q6_V_vsetqfext_VR | function | ||
| 3088 | core::core_arch::hexagon::v128 | Q6_V_vsplat_R | function | ||
| 3089 | core::core_arch::hexagon::v128 | Q6_V_vxor_VV | function | ||
| 3090 | core::core_arch::hexagon::v128 | Q6_V_vzero | function | ||
| 3091 | core::core_arch::hexagon::v128 | Q6_Vb_condacc_QVbVb | function | ||
| 3092 | core::core_arch::hexagon::v128 | Q6_Vb_condacc_QnVbVb | function | ||
| 3093 | core::core_arch::hexagon::v128 | Q6_Vb_condnac_QVbVb | function | ||
| 3094 | core::core_arch::hexagon::v128 | Q6_Vb_condnac_QnVbVb | function | ||
| 3095 | core::core_arch::hexagon::v128 | Q6_Vb_prefixsum_Q | function | ||
| 3096 | core::core_arch::hexagon::v128 | Q6_Vb_vabs_Vb | function | ||
| 3097 | core::core_arch::hexagon::v128 | Q6_Vb_vabs_Vb_sat | function | ||
| 3098 | core::core_arch::hexagon::v128 | Q6_Vb_vadd_VbVb | function | ||
| 3099 | core::core_arch::hexagon::v128 | Q6_Vb_vadd_VbVb_sat | function | ||
| 3100 | core::core_arch::hexagon::v128 | Q6_Vb_vasr_VhVhR_rnd_sat | function | ||
| 3101 | core::core_arch::hexagon::v128 | Q6_Vb_vasr_VhVhR_sat | function | ||
| 3102 | core::core_arch::hexagon::v128 | Q6_Vb_vavg_VbVb | function | ||
| 3103 | core::core_arch::hexagon::v128 | Q6_Vb_vavg_VbVb_rnd | function | ||
| 3104 | core::core_arch::hexagon::v128 | Q6_Vb_vcvt_VhfVhf | function | ||
| 3105 | core::core_arch::hexagon::v128 | Q6_Vb_vdeal_Vb | function | ||
| 3106 | core::core_arch::hexagon::v128 | Q6_Vb_vdeale_VbVb | function | ||
| 3107 | core::core_arch::hexagon::v128 | Q6_Vb_vlut32_VbVbI | function | ||
| 3108 | core::core_arch::hexagon::v128 | Q6_Vb_vlut32_VbVbR | function | ||
| 3109 | core::core_arch::hexagon::v128 | Q6_Vb_vlut32_VbVbR_nomatch | function | ||
| 3110 | core::core_arch::hexagon::v128 | Q6_Vb_vlut32or_VbVbVbI | function | ||
| 3111 | core::core_arch::hexagon::v128 | Q6_Vb_vlut32or_VbVbVbR | function | ||
| 3112 | core::core_arch::hexagon::v128 | Q6_Vb_vmax_VbVb | function | ||
| 3113 | core::core_arch::hexagon::v128 | Q6_Vb_vmin_VbVb | function | ||
| 3114 | core::core_arch::hexagon::v128 | Q6_Vb_vnavg_VbVb | function | ||
| 3115 | core::core_arch::hexagon::v128 | Q6_Vb_vnavg_VubVub | function | ||
| 3116 | core::core_arch::hexagon::v128 | Q6_Vb_vpack_VhVh_sat | function | ||
| 3117 | core::core_arch::hexagon::v128 | Q6_Vb_vpacke_VhVh | function | ||
| 3118 | core::core_arch::hexagon::v128 | Q6_Vb_vpacko_VhVh | function | ||
| 3119 | core::core_arch::hexagon::v128 | Q6_Vb_vround_VhVh_sat | function | ||
| 3120 | core::core_arch::hexagon::v128 | Q6_Vb_vshuff_Vb | function | ||
| 3121 | core::core_arch::hexagon::v128 | Q6_Vb_vshuffe_VbVb | function | ||
| 3122 | core::core_arch::hexagon::v128 | Q6_Vb_vshuffo_VbVb | function | ||
| 3123 | core::core_arch::hexagon::v128 | Q6_Vb_vsplat_R | function | ||
| 3124 | core::core_arch::hexagon::v128 | Q6_Vb_vsub_VbVb | function | ||
| 3125 | core::core_arch::hexagon::v128 | Q6_Vb_vsub_VbVb_sat | function | ||
| 3126 | core::core_arch::hexagon::v128 | Q6_Vh_condacc_QVhVh | function | ||
| 3127 | core::core_arch::hexagon::v128 | Q6_Vh_condacc_QnVhVh | function | ||
| 3128 | core::core_arch::hexagon::v128 | Q6_Vh_condnac_QVhVh | function | ||
| 3129 | core::core_arch::hexagon::v128 | Q6_Vh_condnac_QnVhVh | function | ||
| 3130 | core::core_arch::hexagon::v128 | Q6_Vh_equals_Vhf | function | ||
| 3131 | core::core_arch::hexagon::v128 | Q6_Vh_prefixsum_Q | function | ||
| 3132 | core::core_arch::hexagon::v128 | Q6_Vh_vabs_Vh | function | ||
| 3133 | core::core_arch::hexagon::v128 | Q6_Vh_vabs_Vh_sat | function | ||
| 3134 | core::core_arch::hexagon::v128 | Q6_Vh_vadd_VhVh | function | ||
| 3135 | core::core_arch::hexagon::v128 | Q6_Vh_vadd_VhVh_sat | function | ||
| 3136 | core::core_arch::hexagon::v128 | Q6_Vh_vadd_vclb_VhVh | function | ||
| 3137 | core::core_arch::hexagon::v128 | Q6_Vh_vasl_VhR | function | ||
| 3138 | core::core_arch::hexagon::v128 | Q6_Vh_vasl_VhVh | function | ||
| 3139 | core::core_arch::hexagon::v128 | Q6_Vh_vaslacc_VhVhR | function | ||
| 3140 | core::core_arch::hexagon::v128 | Q6_Vh_vasr_VhR | function | ||
| 3141 | core::core_arch::hexagon::v128 | Q6_Vh_vasr_VhVh | function | ||
| 3142 | core::core_arch::hexagon::v128 | Q6_Vh_vasr_VwVwR | function | ||
| 3143 | core::core_arch::hexagon::v128 | Q6_Vh_vasr_VwVwR_rnd_sat | function | ||
| 3144 | core::core_arch::hexagon::v128 | Q6_Vh_vasr_VwVwR_sat | function | ||
| 3145 | core::core_arch::hexagon::v128 | Q6_Vh_vasracc_VhVhR | function | ||
| 3146 | core::core_arch::hexagon::v128 | Q6_Vh_vavg_VhVh | function | ||
| 3147 | core::core_arch::hexagon::v128 | Q6_Vh_vavg_VhVh_rnd | function | ||
| 3148 | core::core_arch::hexagon::v128 | Q6_Vh_vcvt_Vhf | function | ||
| 3149 | core::core_arch::hexagon::v128 | Q6_Vh_vdeal_Vh | function | ||
| 3150 | core::core_arch::hexagon::v128 | Q6_Vh_vdmpy_VubRb | function | ||
| 3151 | core::core_arch::hexagon::v128 | Q6_Vh_vdmpyacc_VhVubRb | function | ||
| 3152 | core::core_arch::hexagon::v128 | Q6_Vh_vlsr_VhVh | function | ||
| 3153 | core::core_arch::hexagon::v128 | Q6_Vh_vmax_VhVh | function | ||
| 3154 | core::core_arch::hexagon::v128 | Q6_Vh_vmin_VhVh | function | ||
| 3155 | core::core_arch::hexagon::v128 | Q6_Vh_vmpy_VhRh_s1_rnd_sat | function | ||
| 3156 | core::core_arch::hexagon::v128 | Q6_Vh_vmpy_VhRh_s1_sat | function | ||
| 3157 | core::core_arch::hexagon::v128 | Q6_Vh_vmpy_VhVh_s1_rnd_sat | function | ||
| 3158 | core::core_arch::hexagon::v128 | Q6_Vh_vmpyi_VhRb | function | ||
| 3159 | core::core_arch::hexagon::v128 | Q6_Vh_vmpyi_VhVh | function | ||
| 3160 | core::core_arch::hexagon::v128 | Q6_Vh_vmpyiacc_VhVhRb | function | ||
| 3161 | core::core_arch::hexagon::v128 | Q6_Vh_vmpyiacc_VhVhVh | function | ||
| 3162 | core::core_arch::hexagon::v128 | Q6_Vh_vnavg_VhVh | function | ||
| 3163 | core::core_arch::hexagon::v128 | Q6_Vh_vnormamt_Vh | function | ||
| 3164 | core::core_arch::hexagon::v128 | Q6_Vh_vpack_VwVw_sat | function | ||
| 3165 | core::core_arch::hexagon::v128 | Q6_Vh_vpacke_VwVw | function | ||
| 3166 | core::core_arch::hexagon::v128 | Q6_Vh_vpacko_VwVw | function | ||
| 3167 | core::core_arch::hexagon::v128 | Q6_Vh_vpopcount_Vh | function | ||
| 3168 | core::core_arch::hexagon::v128 | Q6_Vh_vround_VwVw_sat | function | ||
| 3169 | core::core_arch::hexagon::v128 | Q6_Vh_vsat_VwVw | function | ||
| 3170 | core::core_arch::hexagon::v128 | Q6_Vh_vshuff_Vh | function | ||
| 3171 | core::core_arch::hexagon::v128 | Q6_Vh_vshuffe_VhVh | function | ||
| 3172 | core::core_arch::hexagon::v128 | Q6_Vh_vshuffo_VhVh | function | ||
| 3173 | core::core_arch::hexagon::v128 | Q6_Vh_vsplat_R | function | ||
| 3174 | core::core_arch::hexagon::v128 | Q6_Vh_vsub_VhVh | function | ||
| 3175 | core::core_arch::hexagon::v128 | Q6_Vh_vsub_VhVh_sat | function | ||
| 3176 | core::core_arch::hexagon::v128 | Q6_Vhf_equals_Vh | function | ||
| 3177 | core::core_arch::hexagon::v128 | Q6_Vhf_equals_Vqf16 | function | ||
| 3178 | core::core_arch::hexagon::v128 | Q6_Vhf_equals_Wqf32 | function | ||
| 3179 | core::core_arch::hexagon::v128 | Q6_Vhf_vabs_Vhf | function | ||
| 3180 | core::core_arch::hexagon::v128 | Q6_Vhf_vadd_VhfVhf | function | ||
| 3181 | core::core_arch::hexagon::v128 | Q6_Vhf_vcvt_Vh | function | ||
| 3182 | core::core_arch::hexagon::v128 | Q6_Vhf_vcvt_VsfVsf | function | ||
| 3183 | core::core_arch::hexagon::v128 | Q6_Vhf_vcvt_Vuh | function | ||
| 3184 | core::core_arch::hexagon::v128 | Q6_Vhf_vfmax_VhfVhf | function | ||
| 3185 | core::core_arch::hexagon::v128 | Q6_Vhf_vfmin_VhfVhf | function | ||
| 3186 | core::core_arch::hexagon::v128 | Q6_Vhf_vfneg_Vhf | function | ||
| 3187 | core::core_arch::hexagon::v128 | Q6_Vhf_vmax_VhfVhf | function | ||
| 3188 | core::core_arch::hexagon::v128 | Q6_Vhf_vmin_VhfVhf | function | ||
| 3189 | core::core_arch::hexagon::v128 | Q6_Vhf_vmpy_VhfVhf | function | ||
| 3190 | core::core_arch::hexagon::v128 | Q6_Vhf_vmpyacc_VhfVhfVhf | function | ||
| 3191 | core::core_arch::hexagon::v128 | Q6_Vhf_vsub_VhfVhf | function | ||
| 3192 | core::core_arch::hexagon::v128 | Q6_Vqf16_vadd_VhfVhf | function | ||
| 3193 | core::core_arch::hexagon::v128 | Q6_Vqf16_vadd_Vqf16Vhf | function | ||
| 3194 | core::core_arch::hexagon::v128 | Q6_Vqf16_vadd_Vqf16Vqf16 | function | ||
| 3195 | core::core_arch::hexagon::v128 | Q6_Vqf16_vmpy_VhfVhf | function | ||
| 3196 | core::core_arch::hexagon::v128 | Q6_Vqf16_vmpy_Vqf16Vhf | function | ||
| 3197 | core::core_arch::hexagon::v128 | Q6_Vqf16_vmpy_Vqf16Vqf16 | function | ||
| 3198 | core::core_arch::hexagon::v128 | Q6_Vqf16_vsub_VhfVhf | function | ||
| 3199 | core::core_arch::hexagon::v128 | Q6_Vqf16_vsub_Vqf16Vhf | function | ||
| 3200 | core::core_arch::hexagon::v128 | Q6_Vqf16_vsub_Vqf16Vqf16 | function | ||
| 3201 | core::core_arch::hexagon::v128 | Q6_Vqf32_vadd_Vqf32Vqf32 | function | ||
| 3202 | core::core_arch::hexagon::v128 | Q6_Vqf32_vadd_Vqf32Vsf | function | ||
| 3203 | core::core_arch::hexagon::v128 | Q6_Vqf32_vadd_VsfVsf | function | ||
| 3204 | core::core_arch::hexagon::v128 | Q6_Vqf32_vmpy_Vqf32Vqf32 | function | ||
| 3205 | core::core_arch::hexagon::v128 | Q6_Vqf32_vmpy_VsfVsf | function | ||
| 3206 | core::core_arch::hexagon::v128 | Q6_Vqf32_vsub_Vqf32Vqf32 | function | ||
| 3207 | core::core_arch::hexagon::v128 | Q6_Vqf32_vsub_Vqf32Vsf | function | ||
| 3208 | core::core_arch::hexagon::v128 | Q6_Vqf32_vsub_VsfVsf | function | ||
| 3209 | core::core_arch::hexagon::v128 | Q6_Vsf_equals_Vqf32 | function | ||
| 3210 | core::core_arch::hexagon::v128 | Q6_Vsf_equals_Vw | function | ||
| 3211 | core::core_arch::hexagon::v128 | Q6_Vsf_vabs_Vsf | function | ||
| 3212 | core::core_arch::hexagon::v128 | Q6_Vsf_vadd_VsfVsf | function | ||
| 3213 | core::core_arch::hexagon::v128 | Q6_Vsf_vdmpy_VhfVhf | function | ||
| 3214 | core::core_arch::hexagon::v128 | Q6_Vsf_vdmpyacc_VsfVhfVhf | function | ||
| 3215 | core::core_arch::hexagon::v128 | Q6_Vsf_vfmax_VsfVsf | function | ||
| 3216 | core::core_arch::hexagon::v128 | Q6_Vsf_vfmin_VsfVsf | function | ||
| 3217 | core::core_arch::hexagon::v128 | Q6_Vsf_vfneg_Vsf | function | ||
| 3218 | core::core_arch::hexagon::v128 | Q6_Vsf_vmax_VsfVsf | function | ||
| 3219 | core::core_arch::hexagon::v128 | Q6_Vsf_vmin_VsfVsf | function | ||
| 3220 | core::core_arch::hexagon::v128 | Q6_Vsf_vmpy_VsfVsf | function | ||
| 3221 | core::core_arch::hexagon::v128 | Q6_Vsf_vsub_VsfVsf | function | ||
| 3222 | core::core_arch::hexagon::v128 | Q6_Vub_vabsdiff_VubVub | function | ||
| 3223 | core::core_arch::hexagon::v128 | Q6_Vub_vadd_VubVb_sat | function | ||
| 3224 | core::core_arch::hexagon::v128 | Q6_Vub_vadd_VubVub_sat | function | ||
| 3225 | core::core_arch::hexagon::v128 | Q6_Vub_vasr_VhVhR_rnd_sat | function | ||
| 3226 | core::core_arch::hexagon::v128 | Q6_Vub_vasr_VhVhR_sat | function | ||
| 3227 | core::core_arch::hexagon::v128 | Q6_Vub_vasr_VuhVuhR_rnd_sat | function | ||
| 3228 | core::core_arch::hexagon::v128 | Q6_Vub_vasr_VuhVuhR_sat | function | ||
| 3229 | core::core_arch::hexagon::v128 | Q6_Vub_vasr_WuhVub_rnd_sat | function | ||
| 3230 | core::core_arch::hexagon::v128 | Q6_Vub_vasr_WuhVub_sat | function | ||
| 3231 | core::core_arch::hexagon::v128 | Q6_Vub_vavg_VubVub | function | ||
| 3232 | core::core_arch::hexagon::v128 | Q6_Vub_vavg_VubVub_rnd | function | ||
| 3233 | core::core_arch::hexagon::v128 | Q6_Vub_vcvt_VhfVhf | function | ||
| 3234 | core::core_arch::hexagon::v128 | Q6_Vub_vlsr_VubR | function | ||
| 3235 | core::core_arch::hexagon::v128 | Q6_Vub_vmax_VubVub | function | ||
| 3236 | core::core_arch::hexagon::v128 | Q6_Vub_vmin_VubVub | function | ||
| 3237 | core::core_arch::hexagon::v128 | Q6_Vub_vpack_VhVh_sat | function | ||
| 3238 | core::core_arch::hexagon::v128 | Q6_Vub_vround_VhVh_sat | function | ||
| 3239 | core::core_arch::hexagon::v128 | Q6_Vub_vround_VuhVuh_sat | function | ||
| 3240 | core::core_arch::hexagon::v128 | Q6_Vub_vsat_VhVh | function | ||
| 3241 | core::core_arch::hexagon::v128 | Q6_Vub_vsub_VubVb_sat | function | ||
| 3242 | core::core_arch::hexagon::v128 | Q6_Vub_vsub_VubVub_sat | function | ||
| 3243 | core::core_arch::hexagon::v128 | Q6_Vuh_vabsdiff_VhVh | function | ||
| 3244 | core::core_arch::hexagon::v128 | Q6_Vuh_vabsdiff_VuhVuh | function | ||
| 3245 | core::core_arch::hexagon::v128 | Q6_Vuh_vadd_VuhVuh_sat | function | ||
| 3246 | core::core_arch::hexagon::v128 | Q6_Vuh_vasr_VuwVuwR_rnd_sat | function | ||
| 3247 | core::core_arch::hexagon::v128 | Q6_Vuh_vasr_VuwVuwR_sat | function | ||
| 3248 | core::core_arch::hexagon::v128 | Q6_Vuh_vasr_VwVwR_rnd_sat | function | ||
| 3249 | core::core_arch::hexagon::v128 | Q6_Vuh_vasr_VwVwR_sat | function | ||
| 3250 | core::core_arch::hexagon::v128 | Q6_Vuh_vasr_WwVuh_rnd_sat | function | ||
| 3251 | core::core_arch::hexagon::v128 | Q6_Vuh_vasr_WwVuh_sat | function | ||
| 3252 | core::core_arch::hexagon::v128 | Q6_Vuh_vavg_VuhVuh | function | ||
| 3253 | core::core_arch::hexagon::v128 | Q6_Vuh_vavg_VuhVuh_rnd | function | ||
| 3254 | core::core_arch::hexagon::v128 | Q6_Vuh_vcl0_Vuh | function | ||
| 3255 | core::core_arch::hexagon::v128 | Q6_Vuh_vcvt_Vhf | function | ||
| 3256 | core::core_arch::hexagon::v128 | Q6_Vuh_vlsr_VuhR | function | ||
| 3257 | core::core_arch::hexagon::v128 | Q6_Vuh_vmax_VuhVuh | function | ||
| 3258 | core::core_arch::hexagon::v128 | Q6_Vuh_vmin_VuhVuh | function | ||
| 3259 | core::core_arch::hexagon::v128 | Q6_Vuh_vmpy_VuhVuh_rs16 | function | ||
| 3260 | core::core_arch::hexagon::v128 | Q6_Vuh_vpack_VwVw_sat | function | ||
| 3261 | core::core_arch::hexagon::v128 | Q6_Vuh_vround_VuwVuw_sat | function | ||
| 3262 | core::core_arch::hexagon::v128 | Q6_Vuh_vround_VwVw_sat | function | ||
| 3263 | core::core_arch::hexagon::v128 | Q6_Vuh_vsat_VuwVuw | function | ||
| 3264 | core::core_arch::hexagon::v128 | Q6_Vuh_vsub_VuhVuh_sat | function | ||
| 3265 | core::core_arch::hexagon::v128 | Q6_Vuw_vabsdiff_VwVw | function | ||
| 3266 | core::core_arch::hexagon::v128 | Q6_Vuw_vadd_VuwVuw_sat | function | ||
| 3267 | core::core_arch::hexagon::v128 | Q6_Vuw_vavg_VuwVuw | function | ||
| 3268 | core::core_arch::hexagon::v128 | Q6_Vuw_vavg_VuwVuw_rnd | function | ||
| 3269 | core::core_arch::hexagon::v128 | Q6_Vuw_vcl0_Vuw | function | ||
| 3270 | core::core_arch::hexagon::v128 | Q6_Vuw_vlsr_VuwR | function | ||
| 3271 | core::core_arch::hexagon::v128 | Q6_Vuw_vmpye_VuhRuh | function | ||
| 3272 | core::core_arch::hexagon::v128 | Q6_Vuw_vmpyeacc_VuwVuhRuh | function | ||
| 3273 | core::core_arch::hexagon::v128 | Q6_Vuw_vrmpy_VubRub | function | ||
| 3274 | core::core_arch::hexagon::v128 | Q6_Vuw_vrmpy_VubVub | function | ||
| 3275 | core::core_arch::hexagon::v128 | Q6_Vuw_vrmpyacc_VuwVubRub | function | ||
| 3276 | core::core_arch::hexagon::v128 | Q6_Vuw_vrmpyacc_VuwVubVub | function | ||
| 3277 | core::core_arch::hexagon::v128 | Q6_Vuw_vrotr_VuwVuw | function | ||
| 3278 | core::core_arch::hexagon::v128 | Q6_Vuw_vsub_VuwVuw_sat | function | ||
| 3279 | core::core_arch::hexagon::v128 | Q6_Vw_condacc_QVwVw | function | ||
| 3280 | core::core_arch::hexagon::v128 | Q6_Vw_condacc_QnVwVw | function | ||
| 3281 | core::core_arch::hexagon::v128 | Q6_Vw_condnac_QVwVw | function | ||
| 3282 | core::core_arch::hexagon::v128 | Q6_Vw_condnac_QnVwVw | function | ||
| 3283 | core::core_arch::hexagon::v128 | Q6_Vw_equals_Vsf | function | ||
| 3284 | core::core_arch::hexagon::v128 | Q6_Vw_prefixsum_Q | function | ||
| 3285 | core::core_arch::hexagon::v128 | Q6_Vw_vabs_Vw | function | ||
| 3286 | core::core_arch::hexagon::v128 | Q6_Vw_vabs_Vw_sat | function | ||
| 3287 | core::core_arch::hexagon::v128 | Q6_Vw_vadd_VwVw | function | ||
| 3288 | core::core_arch::hexagon::v128 | Q6_Vw_vadd_VwVwQ_carry_sat | function | ||
| 3289 | core::core_arch::hexagon::v128 | Q6_Vw_vadd_VwVw_sat | function | ||
| 3290 | core::core_arch::hexagon::v128 | Q6_Vw_vadd_vclb_VwVw | function | ||
| 3291 | core::core_arch::hexagon::v128 | Q6_Vw_vasl_VwR | function | ||
| 3292 | core::core_arch::hexagon::v128 | Q6_Vw_vasl_VwVw | function | ||
| 3293 | core::core_arch::hexagon::v128 | Q6_Vw_vaslacc_VwVwR | function | ||
| 3294 | core::core_arch::hexagon::v128 | Q6_Vw_vasr_VwR | function | ||
| 3295 | core::core_arch::hexagon::v128 | Q6_Vw_vasr_VwVw | function | ||
| 3296 | core::core_arch::hexagon::v128 | Q6_Vw_vasracc_VwVwR | function | ||
| 3297 | core::core_arch::hexagon::v128 | Q6_Vw_vavg_VwVw | function | ||
| 3298 | core::core_arch::hexagon::v128 | Q6_Vw_vavg_VwVw_rnd | function | ||
| 3299 | core::core_arch::hexagon::v128 | Q6_Vw_vdmpy_VhRb | function | ||
| 3300 | core::core_arch::hexagon::v128 | Q6_Vw_vdmpy_VhRh_sat | function | ||
| 3301 | core::core_arch::hexagon::v128 | Q6_Vw_vdmpy_VhRuh_sat | function | ||
| 3302 | core::core_arch::hexagon::v128 | Q6_Vw_vdmpy_VhVh_sat | function | ||
| 3303 | core::core_arch::hexagon::v128 | Q6_Vw_vdmpy_WhRh_sat | function | ||
| 3304 | core::core_arch::hexagon::v128 | Q6_Vw_vdmpy_WhRuh_sat | function | ||
| 3305 | core::core_arch::hexagon::v128 | Q6_Vw_vdmpyacc_VwVhRb | function | ||
| 3306 | core::core_arch::hexagon::v128 | Q6_Vw_vdmpyacc_VwVhRh_sat | function | ||
| 3307 | core::core_arch::hexagon::v128 | Q6_Vw_vdmpyacc_VwVhRuh_sat | function | ||
| 3308 | core::core_arch::hexagon::v128 | Q6_Vw_vdmpyacc_VwVhVh_sat | function | ||
| 3309 | core::core_arch::hexagon::v128 | Q6_Vw_vdmpyacc_VwWhRh_sat | function | ||
| 3310 | core::core_arch::hexagon::v128 | Q6_Vw_vdmpyacc_VwWhRuh_sat | function | ||
| 3311 | core::core_arch::hexagon::v128 | Q6_Vw_vfmv_Vw | function | ||
| 3312 | core::core_arch::hexagon::v128 | Q6_Vw_vinsert_VwR | function | ||
| 3313 | core::core_arch::hexagon::v128 | Q6_Vw_vlsr_VwVw | function | ||
| 3314 | core::core_arch::hexagon::v128 | Q6_Vw_vmax_VwVw | function | ||
| 3315 | core::core_arch::hexagon::v128 | Q6_Vw_vmin_VwVw | function | ||
| 3316 | core::core_arch::hexagon::v128 | Q6_Vw_vmpye_VwVuh | function | ||
| 3317 | core::core_arch::hexagon::v128 | Q6_Vw_vmpyi_VwRb | function | ||
| 3318 | core::core_arch::hexagon::v128 | Q6_Vw_vmpyi_VwRh | function | ||
| 3319 | core::core_arch::hexagon::v128 | Q6_Vw_vmpyi_VwRub | function | ||
| 3320 | core::core_arch::hexagon::v128 | Q6_Vw_vmpyiacc_VwVwRb | function | ||
| 3321 | core::core_arch::hexagon::v128 | Q6_Vw_vmpyiacc_VwVwRh | function | ||
| 3322 | core::core_arch::hexagon::v128 | Q6_Vw_vmpyiacc_VwVwRub | function | ||
| 3323 | core::core_arch::hexagon::v128 | Q6_Vw_vmpyie_VwVuh | function | ||
| 3324 | core::core_arch::hexagon::v128 | Q6_Vw_vmpyieacc_VwVwVh | function | ||
| 3325 | core::core_arch::hexagon::v128 | Q6_Vw_vmpyieacc_VwVwVuh | function | ||
| 3326 | core::core_arch::hexagon::v128 | Q6_Vw_vmpyieo_VhVh | function | ||
| 3327 | core::core_arch::hexagon::v128 | Q6_Vw_vmpyio_VwVh | function | ||
| 3328 | core::core_arch::hexagon::v128 | Q6_Vw_vmpyo_VwVh_s1_rnd_sat | function | ||
| 3329 | core::core_arch::hexagon::v128 | Q6_Vw_vmpyo_VwVh_s1_sat | function | ||
| 3330 | core::core_arch::hexagon::v128 | Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shift | function | ||
| 3331 | core::core_arch::hexagon::v128 | Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shift | function | ||
| 3332 | core::core_arch::hexagon::v128 | Q6_Vw_vnavg_VwVw | function | ||
| 3333 | core::core_arch::hexagon::v128 | Q6_Vw_vnormamt_Vw | function | ||
| 3334 | core::core_arch::hexagon::v128 | Q6_Vw_vrmpy_VbVb | function | ||
| 3335 | core::core_arch::hexagon::v128 | Q6_Vw_vrmpy_VubRb | function | ||
| 3336 | core::core_arch::hexagon::v128 | Q6_Vw_vrmpy_VubVb | function | ||
| 3337 | core::core_arch::hexagon::v128 | Q6_Vw_vrmpyacc_VwVbVb | function | ||
| 3338 | core::core_arch::hexagon::v128 | Q6_Vw_vrmpyacc_VwVubRb | function | ||
| 3339 | core::core_arch::hexagon::v128 | Q6_Vw_vrmpyacc_VwVubVb | function | ||
| 3340 | core::core_arch::hexagon::v128 | Q6_Vw_vsatdw_VwVw | function | ||
| 3341 | core::core_arch::hexagon::v128 | Q6_Vw_vsub_VwVw | function | ||
| 3342 | core::core_arch::hexagon::v128 | Q6_Vw_vsub_VwVw_sat | function | ||
| 3343 | core::core_arch::hexagon::v128 | Q6_W_equals_W | function | ||
| 3344 | core::core_arch::hexagon::v128 | Q6_W_vcombine_VV | function | ||
| 3345 | core::core_arch::hexagon::v128 | Q6_W_vdeal_VVR | function | ||
| 3346 | core::core_arch::hexagon::v128 | Q6_W_vmpye_VwVuh | function | ||
| 3347 | core::core_arch::hexagon::v128 | Q6_W_vmpyoacc_WVwVh | function | ||
| 3348 | core::core_arch::hexagon::v128 | Q6_W_vshuff_VVR | function | ||
| 3349 | core::core_arch::hexagon::v128 | Q6_W_vswap_QVV | function | ||
| 3350 | core::core_arch::hexagon::v128 | Q6_W_vzero | function | ||
| 3351 | core::core_arch::hexagon::v128 | Q6_Wb_vadd_WbWb | function | ||
| 3352 | core::core_arch::hexagon::v128 | Q6_Wb_vadd_WbWb_sat | function | ||
| 3353 | core::core_arch::hexagon::v128 | Q6_Wb_vshuffoe_VbVb | function | ||
| 3354 | core::core_arch::hexagon::v128 | Q6_Wb_vsub_WbWb | function | ||
| 3355 | core::core_arch::hexagon::v128 | Q6_Wb_vsub_WbWb_sat | function | ||
| 3356 | core::core_arch::hexagon::v128 | Q6_Wh_vadd_VubVub | function | ||
| 3357 | core::core_arch::hexagon::v128 | Q6_Wh_vadd_WhWh | function | ||
| 3358 | core::core_arch::hexagon::v128 | Q6_Wh_vadd_WhWh_sat | function | ||
| 3359 | core::core_arch::hexagon::v128 | Q6_Wh_vaddacc_WhVubVub | function | ||
| 3360 | core::core_arch::hexagon::v128 | Q6_Wh_vdmpy_WubRb | function | ||
| 3361 | core::core_arch::hexagon::v128 | Q6_Wh_vdmpyacc_WhWubRb | function | ||
| 3362 | core::core_arch::hexagon::v128 | Q6_Wh_vlut16_VbVhI | function | ||
| 3363 | core::core_arch::hexagon::v128 | Q6_Wh_vlut16_VbVhR | function | ||
| 3364 | core::core_arch::hexagon::v128 | Q6_Wh_vlut16_VbVhR_nomatch | function | ||
| 3365 | core::core_arch::hexagon::v128 | Q6_Wh_vlut16or_WhVbVhI | function | ||
| 3366 | core::core_arch::hexagon::v128 | Q6_Wh_vlut16or_WhVbVhR | function | ||
| 3367 | core::core_arch::hexagon::v128 | Q6_Wh_vmpa_WubRb | function | ||
| 3368 | core::core_arch::hexagon::v128 | Q6_Wh_vmpa_WubRub | function | ||
| 3369 | core::core_arch::hexagon::v128 | Q6_Wh_vmpa_WubWb | function | ||
| 3370 | core::core_arch::hexagon::v128 | Q6_Wh_vmpa_WubWub | function | ||
| 3371 | core::core_arch::hexagon::v128 | Q6_Wh_vmpaacc_WhWubRb | function | ||
| 3372 | core::core_arch::hexagon::v128 | Q6_Wh_vmpaacc_WhWubRub | function | ||
| 3373 | core::core_arch::hexagon::v128 | Q6_Wh_vmpy_VbVb | function | ||
| 3374 | core::core_arch::hexagon::v128 | Q6_Wh_vmpy_VubRb | function | ||
| 3375 | core::core_arch::hexagon::v128 | Q6_Wh_vmpy_VubVb | function | ||
| 3376 | core::core_arch::hexagon::v128 | Q6_Wh_vmpyacc_WhVbVb | function | ||
| 3377 | core::core_arch::hexagon::v128 | Q6_Wh_vmpyacc_WhVubRb | function | ||
| 3378 | core::core_arch::hexagon::v128 | Q6_Wh_vmpyacc_WhVubVb | function | ||
| 3379 | core::core_arch::hexagon::v128 | Q6_Wh_vshuffoe_VhVh | function | ||
| 3380 | core::core_arch::hexagon::v128 | Q6_Wh_vsub_VubVub | function | ||
| 3381 | core::core_arch::hexagon::v128 | Q6_Wh_vsub_WhWh | function | ||
| 3382 | core::core_arch::hexagon::v128 | Q6_Wh_vsub_WhWh_sat | function | ||
| 3383 | core::core_arch::hexagon::v128 | Q6_Wh_vsxt_Vb | function | ||
| 3384 | core::core_arch::hexagon::v128 | Q6_Wh_vtmpy_WbRb | function | ||
| 3385 | core::core_arch::hexagon::v128 | Q6_Wh_vtmpy_WubRb | function | ||
| 3386 | core::core_arch::hexagon::v128 | Q6_Wh_vtmpyacc_WhWbRb | function | ||
| 3387 | core::core_arch::hexagon::v128 | Q6_Wh_vtmpyacc_WhWubRb | function | ||
| 3388 | core::core_arch::hexagon::v128 | Q6_Wh_vunpack_Vb | function | ||
| 3389 | core::core_arch::hexagon::v128 | Q6_Wh_vunpackoor_WhVb | function | ||
| 3390 | core::core_arch::hexagon::v128 | Q6_Whf_vcvt2_Vb | function | ||
| 3391 | core::core_arch::hexagon::v128 | Q6_Whf_vcvt2_Vub | function | ||
| 3392 | core::core_arch::hexagon::v128 | Q6_Whf_vcvt_V | function | ||
| 3393 | core::core_arch::hexagon::v128 | Q6_Whf_vcvt_Vb | function | ||
| 3394 | core::core_arch::hexagon::v128 | Q6_Whf_vcvt_Vub | function | ||
| 3395 | core::core_arch::hexagon::v128 | Q6_Wqf32_vmpy_VhfVhf | function | ||
| 3396 | core::core_arch::hexagon::v128 | Q6_Wqf32_vmpy_Vqf16Vhf | function | ||
| 3397 | core::core_arch::hexagon::v128 | Q6_Wqf32_vmpy_Vqf16Vqf16 | function | ||
| 3398 | core::core_arch::hexagon::v128 | Q6_Wsf_vadd_VhfVhf | function | ||
| 3399 | core::core_arch::hexagon::v128 | Q6_Wsf_vcvt_Vhf | function | ||
| 3400 | core::core_arch::hexagon::v128 | Q6_Wsf_vmpy_VhfVhf | function | ||
| 3401 | core::core_arch::hexagon::v128 | Q6_Wsf_vmpyacc_WsfVhfVhf | function | ||
| 3402 | core::core_arch::hexagon::v128 | Q6_Wsf_vsub_VhfVhf | function | ||
| 3403 | core::core_arch::hexagon::v128 | Q6_Wub_vadd_WubWub_sat | function | ||
| 3404 | core::core_arch::hexagon::v128 | Q6_Wub_vsub_WubWub_sat | function | ||
| 3405 | core::core_arch::hexagon::v128 | Q6_Wuh_vadd_WuhWuh_sat | function | ||
| 3406 | core::core_arch::hexagon::v128 | Q6_Wuh_vmpy_VubRub | function | ||
| 3407 | core::core_arch::hexagon::v128 | Q6_Wuh_vmpy_VubVub | function | ||
| 3408 | core::core_arch::hexagon::v128 | Q6_Wuh_vmpyacc_WuhVubRub | function | ||
| 3409 | core::core_arch::hexagon::v128 | Q6_Wuh_vmpyacc_WuhVubVub | function | ||
| 3410 | core::core_arch::hexagon::v128 | Q6_Wuh_vsub_WuhWuh_sat | function | ||
| 3411 | core::core_arch::hexagon::v128 | Q6_Wuh_vunpack_Vub | function | ||
| 3412 | core::core_arch::hexagon::v128 | Q6_Wuh_vzxt_Vub | function | ||
| 3413 | core::core_arch::hexagon::v128 | Q6_Wuw_vadd_WuwWuw_sat | function | ||
| 3414 | core::core_arch::hexagon::v128 | Q6_Wuw_vdsad_WuhRuh | function | ||
| 3415 | core::core_arch::hexagon::v128 | Q6_Wuw_vdsadacc_WuwWuhRuh | function | ||
| 3416 | core::core_arch::hexagon::v128 | Q6_Wuw_vmpy_VuhRuh | function | ||
| 3417 | core::core_arch::hexagon::v128 | Q6_Wuw_vmpy_VuhVuh | function | ||
| 3418 | core::core_arch::hexagon::v128 | Q6_Wuw_vmpyacc_WuwVuhRuh | function | ||
| 3419 | core::core_arch::hexagon::v128 | Q6_Wuw_vmpyacc_WuwVuhVuh | function | ||
| 3420 | core::core_arch::hexagon::v128 | Q6_Wuw_vrmpy_WubRubI | function | ||
| 3421 | core::core_arch::hexagon::v128 | Q6_Wuw_vrmpyacc_WuwWubRubI | function | ||
| 3422 | core::core_arch::hexagon::v128 | Q6_Wuw_vrsad_WubRubI | function | ||
| 3423 | core::core_arch::hexagon::v128 | Q6_Wuw_vrsadacc_WuwWubRubI | function | ||
| 3424 | core::core_arch::hexagon::v128 | Q6_Wuw_vsub_WuwWuw_sat | function | ||
| 3425 | core::core_arch::hexagon::v128 | Q6_Wuw_vunpack_Vuh | function | ||
| 3426 | core::core_arch::hexagon::v128 | Q6_Wuw_vzxt_Vuh | function | ||
| 3427 | core::core_arch::hexagon::v128 | Q6_Ww_v6mpy_WubWbI_h | function | ||
| 3428 | core::core_arch::hexagon::v128 | Q6_Ww_v6mpy_WubWbI_v | function | ||
| 3429 | core::core_arch::hexagon::v128 | Q6_Ww_v6mpyacc_WwWubWbI_h | function | ||
| 3430 | core::core_arch::hexagon::v128 | Q6_Ww_v6mpyacc_WwWubWbI_v | function | ||
| 3431 | core::core_arch::hexagon::v128 | Q6_Ww_vadd_VhVh | function | ||
| 3432 | core::core_arch::hexagon::v128 | Q6_Ww_vadd_VuhVuh | function | ||
| 3433 | core::core_arch::hexagon::v128 | Q6_Ww_vadd_WwWw | function | ||
| 3434 | core::core_arch::hexagon::v128 | Q6_Ww_vadd_WwWw_sat | function | ||
| 3435 | core::core_arch::hexagon::v128 | Q6_Ww_vaddacc_WwVhVh | function | ||
| 3436 | core::core_arch::hexagon::v128 | Q6_Ww_vaddacc_WwVuhVuh | function | ||
| 3437 | core::core_arch::hexagon::v128 | Q6_Ww_vasrinto_WwVwVw | function | ||
| 3438 | core::core_arch::hexagon::v128 | Q6_Ww_vdmpy_WhRb | function | ||
| 3439 | core::core_arch::hexagon::v128 | Q6_Ww_vdmpyacc_WwWhRb | function | ||
| 3440 | core::core_arch::hexagon::v128 | Q6_Ww_vmpa_WhRb | function | ||
| 3441 | core::core_arch::hexagon::v128 | Q6_Ww_vmpa_WuhRb | function | ||
| 3442 | core::core_arch::hexagon::v128 | Q6_Ww_vmpaacc_WwWhRb | function | ||
| 3443 | core::core_arch::hexagon::v128 | Q6_Ww_vmpaacc_WwWuhRb | function | ||
| 3444 | core::core_arch::hexagon::v128 | Q6_Ww_vmpy_VhRh | function | ||
| 3445 | core::core_arch::hexagon::v128 | Q6_Ww_vmpy_VhVh | function | ||
| 3446 | core::core_arch::hexagon::v128 | Q6_Ww_vmpy_VhVuh | function | ||
| 3447 | core::core_arch::hexagon::v128 | Q6_Ww_vmpyacc_WwVhRh | function | ||
| 3448 | core::core_arch::hexagon::v128 | Q6_Ww_vmpyacc_WwVhRh_sat | function | ||
| 3449 | core::core_arch::hexagon::v128 | Q6_Ww_vmpyacc_WwVhVh | function | ||
| 3450 | core::core_arch::hexagon::v128 | Q6_Ww_vmpyacc_WwVhVuh | function | ||
| 3451 | core::core_arch::hexagon::v128 | Q6_Ww_vrmpy_WubRbI | function | ||
| 3452 | core::core_arch::hexagon::v128 | Q6_Ww_vrmpyacc_WwWubRbI | function | ||
| 3453 | core::core_arch::hexagon::v128 | Q6_Ww_vsub_VhVh | function | ||
| 3454 | core::core_arch::hexagon::v128 | Q6_Ww_vsub_VuhVuh | function | ||
| 3455 | core::core_arch::hexagon::v128 | Q6_Ww_vsub_WwWw | function | ||
| 3456 | core::core_arch::hexagon::v128 | Q6_Ww_vsub_WwWw_sat | function | ||
| 3457 | core::core_arch::hexagon::v128 | Q6_Ww_vsxt_Vh | function | ||
| 3458 | core::core_arch::hexagon::v128 | Q6_Ww_vtmpy_WhRb | function | ||
| 3459 | core::core_arch::hexagon::v128 | Q6_Ww_vtmpyacc_WwWhRb | function | ||
| 3460 | core::core_arch::hexagon::v128 | Q6_Ww_vunpack_Vh | function | ||
| 3461 | core::core_arch::hexagon::v128 | Q6_Ww_vunpackoor_WwVh | function | ||
| 3462 | core::core_arch::hexagon::v128 | Q6_vgather_AQRMVh | function | ||
| 3463 | core::core_arch::hexagon::v128 | Q6_vgather_AQRMVw | function | ||
| 3464 | core::core_arch::hexagon::v128 | Q6_vgather_AQRMWw | function | ||
| 3465 | core::core_arch::hexagon::v128 | Q6_vgather_ARMVh | function | ||
| 3466 | core::core_arch::hexagon::v128 | Q6_vgather_ARMVw | function | ||
| 3467 | core::core_arch::hexagon::v128 | Q6_vgather_ARMWw | function | ||
| 3468 | core::core_arch::hexagon::v128 | Q6_vmem_QRIV | function | ||
| 3469 | core::core_arch::hexagon::v128 | Q6_vmem_QRIV_nt | function | ||
| 3470 | core::core_arch::hexagon::v128 | Q6_vmem_QnRIV | function | ||
| 3471 | core::core_arch::hexagon::v128 | Q6_vmem_QnRIV_nt | function | ||
| 3472 | core::core_arch::hexagon::v128 | Q6_vscatter_QRMVhV | function | ||
| 3473 | core::core_arch::hexagon::v128 | Q6_vscatter_QRMVwV | function | ||
| 3474 | core::core_arch::hexagon::v128 | Q6_vscatter_QRMWwV | function | ||
| 3475 | core::core_arch::hexagon::v128 | Q6_vscatter_RMVhV | function | ||
| 3476 | core::core_arch::hexagon::v128 | Q6_vscatter_RMVwV | function | ||
| 3477 | core::core_arch::hexagon::v128 | Q6_vscatter_RMWwV | function | ||
| 3478 | core::core_arch::hexagon::v128 | Q6_vscatteracc_RMVhV | function | ||
| 3479 | core::core_arch::hexagon::v128 | Q6_vscatteracc_RMVwV | function | ||
| 3480 | core::core_arch::hexagon::v128 | Q6_vscatteracc_RMWwV | function | ||
| 3481 | core::core_arch::hexagon::v64 | Q6_Q_and_QQ | function | ||
| 3482 | core::core_arch::hexagon::v64 | Q6_Q_and_QQn | function | ||
| 3483 | core::core_arch::hexagon::v64 | Q6_Q_not_Q | function | ||
| 3484 | core::core_arch::hexagon::v64 | Q6_Q_or_QQ | function | ||
| 3485 | core::core_arch::hexagon::v64 | Q6_Q_or_QQn | function | ||
| 3486 | core::core_arch::hexagon::v64 | Q6_Q_vand_VR | function | ||
| 3487 | core::core_arch::hexagon::v64 | Q6_Q_vandor_QVR | function | ||
| 3488 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_eq_VbVb | function | ||
| 3489 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_eq_VhVh | function | ||
| 3490 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_eq_VwVw | function | ||
| 3491 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_eqand_QVbVb | function | ||
| 3492 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_eqand_QVhVh | function | ||
| 3493 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_eqand_QVwVw | function | ||
| 3494 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_eqor_QVbVb | function | ||
| 3495 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_eqor_QVhVh | function | ||
| 3496 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_eqor_QVwVw | function | ||
| 3497 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_eqxacc_QVbVb | function | ||
| 3498 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_eqxacc_QVhVh | function | ||
| 3499 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_eqxacc_QVwVw | function | ||
| 3500 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_gt_VbVb | function | ||
| 3501 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_gt_VhVh | function | ||
| 3502 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_gt_VhfVhf | function | ||
| 3503 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_gt_VsfVsf | function | ||
| 3504 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_gt_VubVub | function | ||
| 3505 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_gt_VuhVuh | function | ||
| 3506 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_gt_VuwVuw | function | ||
| 3507 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_gt_VwVw | function | ||
| 3508 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_gtand_QVbVb | function | ||
| 3509 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_gtand_QVhVh | function | ||
| 3510 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_gtand_QVhfVhf | function | ||
| 3511 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_gtand_QVsfVsf | function | ||
| 3512 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_gtand_QVubVub | function | ||
| 3513 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_gtand_QVuhVuh | function | ||
| 3514 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_gtand_QVuwVuw | function | ||
| 3515 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_gtand_QVwVw | function | ||
| 3516 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_gtor_QVbVb | function | ||
| 3517 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_gtor_QVhVh | function | ||
| 3518 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_gtor_QVhfVhf | function | ||
| 3519 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_gtor_QVsfVsf | function | ||
| 3520 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_gtor_QVubVub | function | ||
| 3521 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_gtor_QVuhVuh | function | ||
| 3522 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_gtor_QVuwVuw | function | ||
| 3523 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_gtor_QVwVw | function | ||
| 3524 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_gtxacc_QVbVb | function | ||
| 3525 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_gtxacc_QVhVh | function | ||
| 3526 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_gtxacc_QVhfVhf | function | ||
| 3527 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_gtxacc_QVsfVsf | function | ||
| 3528 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_gtxacc_QVubVub | function | ||
| 3529 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_gtxacc_QVuhVuh | function | ||
| 3530 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_gtxacc_QVuwVuw | function | ||
| 3531 | core::core_arch::hexagon::v64 | Q6_Q_vcmp_gtxacc_QVwVw | function | ||
| 3532 | core::core_arch::hexagon::v64 | Q6_Q_vsetq2_R | function | ||
| 3533 | core::core_arch::hexagon::v64 | Q6_Q_vsetq_R | function | ||
| 3534 | core::core_arch::hexagon::v64 | Q6_Q_xor_QQ | function | ||
| 3535 | core::core_arch::hexagon::v64 | Q6_Qb_vshuffe_QhQh | function | ||
| 3536 | core::core_arch::hexagon::v64 | Q6_Qh_vshuffe_QwQw | function | ||
| 3537 | core::core_arch::hexagon::v64 | Q6_R_vextract_VR | function | ||
| 3538 | core::core_arch::hexagon::v64 | Q6_V_equals_V | function | ||
| 3539 | core::core_arch::hexagon::v64 | Q6_V_hi_W | function | ||
| 3540 | core::core_arch::hexagon::v64 | Q6_V_lo_W | function | ||
| 3541 | core::core_arch::hexagon::v64 | Q6_V_vabs_V | function | ||
| 3542 | core::core_arch::hexagon::v64 | Q6_V_valign_VVI | function | ||
| 3543 | core::core_arch::hexagon::v64 | Q6_V_valign_VVR | function | ||
| 3544 | core::core_arch::hexagon::v64 | Q6_V_vand_QR | function | ||
| 3545 | core::core_arch::hexagon::v64 | Q6_V_vand_QV | function | ||
| 3546 | core::core_arch::hexagon::v64 | Q6_V_vand_QnR | function | ||
| 3547 | core::core_arch::hexagon::v64 | Q6_V_vand_QnV | function | ||
| 3548 | core::core_arch::hexagon::v64 | Q6_V_vand_VV | function | ||
| 3549 | core::core_arch::hexagon::v64 | Q6_V_vandor_VQR | function | ||
| 3550 | core::core_arch::hexagon::v64 | Q6_V_vandor_VQnR | function | ||
| 3551 | core::core_arch::hexagon::v64 | Q6_V_vdelta_VV | function | ||
| 3552 | core::core_arch::hexagon::v64 | Q6_V_vfmax_VV | function | ||
| 3553 | core::core_arch::hexagon::v64 | Q6_V_vfmin_VV | function | ||
| 3554 | core::core_arch::hexagon::v64 | Q6_V_vfneg_V | function | ||
| 3555 | core::core_arch::hexagon::v64 | Q6_V_vgetqfext_VR | function | ||
| 3556 | core::core_arch::hexagon::v64 | Q6_V_vlalign_VVI | function | ||
| 3557 | core::core_arch::hexagon::v64 | Q6_V_vlalign_VVR | function | ||
| 3558 | core::core_arch::hexagon::v64 | Q6_V_vmux_QVV | function | ||
| 3559 | core::core_arch::hexagon::v64 | Q6_V_vnot_V | function | ||
| 3560 | core::core_arch::hexagon::v64 | Q6_V_vor_VV | function | ||
| 3561 | core::core_arch::hexagon::v64 | Q6_V_vrdelta_VV | function | ||
| 3562 | core::core_arch::hexagon::v64 | Q6_V_vror_VR | function | ||
| 3563 | core::core_arch::hexagon::v64 | Q6_V_vsetqfext_VR | function | ||
| 3564 | core::core_arch::hexagon::v64 | Q6_V_vsplat_R | function | ||
| 3565 | core::core_arch::hexagon::v64 | Q6_V_vxor_VV | function | ||
| 3566 | core::core_arch::hexagon::v64 | Q6_V_vzero | function | ||
| 3567 | core::core_arch::hexagon::v64 | Q6_Vb_condacc_QVbVb | function | ||
| 3568 | core::core_arch::hexagon::v64 | Q6_Vb_condacc_QnVbVb | function | ||
| 3569 | core::core_arch::hexagon::v64 | Q6_Vb_condnac_QVbVb | function | ||
| 3570 | core::core_arch::hexagon::v64 | Q6_Vb_condnac_QnVbVb | function | ||
| 3571 | core::core_arch::hexagon::v64 | Q6_Vb_prefixsum_Q | function | ||
| 3572 | core::core_arch::hexagon::v64 | Q6_Vb_vabs_Vb | function | ||
| 3573 | core::core_arch::hexagon::v64 | Q6_Vb_vabs_Vb_sat | function | ||
| 3574 | core::core_arch::hexagon::v64 | Q6_Vb_vadd_VbVb | function | ||
| 3575 | core::core_arch::hexagon::v64 | Q6_Vb_vadd_VbVb_sat | function | ||
| 3576 | core::core_arch::hexagon::v64 | Q6_Vb_vasr_VhVhR_rnd_sat | function | ||
| 3577 | core::core_arch::hexagon::v64 | Q6_Vb_vasr_VhVhR_sat | function | ||
| 3578 | core::core_arch::hexagon::v64 | Q6_Vb_vavg_VbVb | function | ||
| 3579 | core::core_arch::hexagon::v64 | Q6_Vb_vavg_VbVb_rnd | function | ||
| 3580 | core::core_arch::hexagon::v64 | Q6_Vb_vcvt_VhfVhf | function | ||
| 3581 | core::core_arch::hexagon::v64 | Q6_Vb_vdeal_Vb | function | ||
| 3582 | core::core_arch::hexagon::v64 | Q6_Vb_vdeale_VbVb | function | ||
| 3583 | core::core_arch::hexagon::v64 | Q6_Vb_vlut32_VbVbI | function | ||
| 3584 | core::core_arch::hexagon::v64 | Q6_Vb_vlut32_VbVbR | function | ||
| 3585 | core::core_arch::hexagon::v64 | Q6_Vb_vlut32_VbVbR_nomatch | function | ||
| 3586 | core::core_arch::hexagon::v64 | Q6_Vb_vlut32or_VbVbVbI | function | ||
| 3587 | core::core_arch::hexagon::v64 | Q6_Vb_vlut32or_VbVbVbR | function | ||
| 3588 | core::core_arch::hexagon::v64 | Q6_Vb_vmax_VbVb | function | ||
| 3589 | core::core_arch::hexagon::v64 | Q6_Vb_vmin_VbVb | function | ||
| 3590 | core::core_arch::hexagon::v64 | Q6_Vb_vnavg_VbVb | function | ||
| 3591 | core::core_arch::hexagon::v64 | Q6_Vb_vnavg_VubVub | function | ||
| 3592 | core::core_arch::hexagon::v64 | Q6_Vb_vpack_VhVh_sat | function | ||
| 3593 | core::core_arch::hexagon::v64 | Q6_Vb_vpacke_VhVh | function | ||
| 3594 | core::core_arch::hexagon::v64 | Q6_Vb_vpacko_VhVh | function | ||
| 3595 | core::core_arch::hexagon::v64 | Q6_Vb_vround_VhVh_sat | function | ||
| 3596 | core::core_arch::hexagon::v64 | Q6_Vb_vshuff_Vb | function | ||
| 3597 | core::core_arch::hexagon::v64 | Q6_Vb_vshuffe_VbVb | function | ||
| 3598 | core::core_arch::hexagon::v64 | Q6_Vb_vshuffo_VbVb | function | ||
| 3599 | core::core_arch::hexagon::v64 | Q6_Vb_vsplat_R | function | ||
| 3600 | core::core_arch::hexagon::v64 | Q6_Vb_vsub_VbVb | function | ||
| 3601 | core::core_arch::hexagon::v64 | Q6_Vb_vsub_VbVb_sat | function | ||
| 3602 | core::core_arch::hexagon::v64 | Q6_Vh_condacc_QVhVh | function | ||
| 3603 | core::core_arch::hexagon::v64 | Q6_Vh_condacc_QnVhVh | function | ||
| 3604 | core::core_arch::hexagon::v64 | Q6_Vh_condnac_QVhVh | function | ||
| 3605 | core::core_arch::hexagon::v64 | Q6_Vh_condnac_QnVhVh | function | ||
| 3606 | core::core_arch::hexagon::v64 | Q6_Vh_equals_Vhf | function | ||
| 3607 | core::core_arch::hexagon::v64 | Q6_Vh_prefixsum_Q | function | ||
| 3608 | core::core_arch::hexagon::v64 | Q6_Vh_vabs_Vh | function | ||
| 3609 | core::core_arch::hexagon::v64 | Q6_Vh_vabs_Vh_sat | function | ||
| 3610 | core::core_arch::hexagon::v64 | Q6_Vh_vadd_VhVh | function | ||
| 3611 | core::core_arch::hexagon::v64 | Q6_Vh_vadd_VhVh_sat | function | ||
| 3612 | core::core_arch::hexagon::v64 | Q6_Vh_vadd_vclb_VhVh | function | ||
| 3613 | core::core_arch::hexagon::v64 | Q6_Vh_vasl_VhR | function | ||
| 3614 | core::core_arch::hexagon::v64 | Q6_Vh_vasl_VhVh | function | ||
| 3615 | core::core_arch::hexagon::v64 | Q6_Vh_vaslacc_VhVhR | function | ||
| 3616 | core::core_arch::hexagon::v64 | Q6_Vh_vasr_VhR | function | ||
| 3617 | core::core_arch::hexagon::v64 | Q6_Vh_vasr_VhVh | function | ||
| 3618 | core::core_arch::hexagon::v64 | Q6_Vh_vasr_VwVwR | function | ||
| 3619 | core::core_arch::hexagon::v64 | Q6_Vh_vasr_VwVwR_rnd_sat | function | ||
| 3620 | core::core_arch::hexagon::v64 | Q6_Vh_vasr_VwVwR_sat | function | ||
| 3621 | core::core_arch::hexagon::v64 | Q6_Vh_vasracc_VhVhR | function | ||
| 3622 | core::core_arch::hexagon::v64 | Q6_Vh_vavg_VhVh | function | ||
| 3623 | core::core_arch::hexagon::v64 | Q6_Vh_vavg_VhVh_rnd | function | ||
| 3624 | core::core_arch::hexagon::v64 | Q6_Vh_vcvt_Vhf | function | ||
| 3625 | core::core_arch::hexagon::v64 | Q6_Vh_vdeal_Vh | function | ||
| 3626 | core::core_arch::hexagon::v64 | Q6_Vh_vdmpy_VubRb | function | ||
| 3627 | core::core_arch::hexagon::v64 | Q6_Vh_vdmpyacc_VhVubRb | function | ||
| 3628 | core::core_arch::hexagon::v64 | Q6_Vh_vlsr_VhVh | function | ||
| 3629 | core::core_arch::hexagon::v64 | Q6_Vh_vmax_VhVh | function | ||
| 3630 | core::core_arch::hexagon::v64 | Q6_Vh_vmin_VhVh | function | ||
| 3631 | core::core_arch::hexagon::v64 | Q6_Vh_vmpy_VhRh_s1_rnd_sat | function | ||
| 3632 | core::core_arch::hexagon::v64 | Q6_Vh_vmpy_VhRh_s1_sat | function | ||
| 3633 | core::core_arch::hexagon::v64 | Q6_Vh_vmpy_VhVh_s1_rnd_sat | function | ||
| 3634 | core::core_arch::hexagon::v64 | Q6_Vh_vmpyi_VhRb | function | ||
| 3635 | core::core_arch::hexagon::v64 | Q6_Vh_vmpyi_VhVh | function | ||
| 3636 | core::core_arch::hexagon::v64 | Q6_Vh_vmpyiacc_VhVhRb | function | ||
| 3637 | core::core_arch::hexagon::v64 | Q6_Vh_vmpyiacc_VhVhVh | function | ||
| 3638 | core::core_arch::hexagon::v64 | Q6_Vh_vnavg_VhVh | function | ||
| 3639 | core::core_arch::hexagon::v64 | Q6_Vh_vnormamt_Vh | function | ||
| 3640 | core::core_arch::hexagon::v64 | Q6_Vh_vpack_VwVw_sat | function | ||
| 3641 | core::core_arch::hexagon::v64 | Q6_Vh_vpacke_VwVw | function | ||
| 3642 | core::core_arch::hexagon::v64 | Q6_Vh_vpacko_VwVw | function | ||
| 3643 | core::core_arch::hexagon::v64 | Q6_Vh_vpopcount_Vh | function | ||
| 3644 | core::core_arch::hexagon::v64 | Q6_Vh_vround_VwVw_sat | function | ||
| 3645 | core::core_arch::hexagon::v64 | Q6_Vh_vsat_VwVw | function | ||
| 3646 | core::core_arch::hexagon::v64 | Q6_Vh_vshuff_Vh | function | ||
| 3647 | core::core_arch::hexagon::v64 | Q6_Vh_vshuffe_VhVh | function | ||
| 3648 | core::core_arch::hexagon::v64 | Q6_Vh_vshuffo_VhVh | function | ||
| 3649 | core::core_arch::hexagon::v64 | Q6_Vh_vsplat_R | function | ||
| 3650 | core::core_arch::hexagon::v64 | Q6_Vh_vsub_VhVh | function | ||
| 3651 | core::core_arch::hexagon::v64 | Q6_Vh_vsub_VhVh_sat | function | ||
| 3652 | core::core_arch::hexagon::v64 | Q6_Vhf_equals_Vh | function | ||
| 3653 | core::core_arch::hexagon::v64 | Q6_Vhf_equals_Vqf16 | function | ||
| 3654 | core::core_arch::hexagon::v64 | Q6_Vhf_equals_Wqf32 | function | ||
| 3655 | core::core_arch::hexagon::v64 | Q6_Vhf_vabs_Vhf | function | ||
| 3656 | core::core_arch::hexagon::v64 | Q6_Vhf_vadd_VhfVhf | function | ||
| 3657 | core::core_arch::hexagon::v64 | Q6_Vhf_vcvt_Vh | function | ||
| 3658 | core::core_arch::hexagon::v64 | Q6_Vhf_vcvt_VsfVsf | function | ||
| 3659 | core::core_arch::hexagon::v64 | Q6_Vhf_vcvt_Vuh | function | ||
| 3660 | core::core_arch::hexagon::v64 | Q6_Vhf_vfmax_VhfVhf | function | ||
| 3661 | core::core_arch::hexagon::v64 | Q6_Vhf_vfmin_VhfVhf | function | ||
| 3662 | core::core_arch::hexagon::v64 | Q6_Vhf_vfneg_Vhf | function | ||
| 3663 | core::core_arch::hexagon::v64 | Q6_Vhf_vmax_VhfVhf | function | ||
| 3664 | core::core_arch::hexagon::v64 | Q6_Vhf_vmin_VhfVhf | function | ||
| 3665 | core::core_arch::hexagon::v64 | Q6_Vhf_vmpy_VhfVhf | function | ||
| 3666 | core::core_arch::hexagon::v64 | Q6_Vhf_vmpyacc_VhfVhfVhf | function | ||
| 3667 | core::core_arch::hexagon::v64 | Q6_Vhf_vsub_VhfVhf | function | ||
| 3668 | core::core_arch::hexagon::v64 | Q6_Vqf16_vadd_VhfVhf | function | ||
| 3669 | core::core_arch::hexagon::v64 | Q6_Vqf16_vadd_Vqf16Vhf | function | ||
| 3670 | core::core_arch::hexagon::v64 | Q6_Vqf16_vadd_Vqf16Vqf16 | function | ||
| 3671 | core::core_arch::hexagon::v64 | Q6_Vqf16_vmpy_VhfVhf | function | ||
| 3672 | core::core_arch::hexagon::v64 | Q6_Vqf16_vmpy_Vqf16Vhf | function | ||
| 3673 | core::core_arch::hexagon::v64 | Q6_Vqf16_vmpy_Vqf16Vqf16 | function | ||
| 3674 | core::core_arch::hexagon::v64 | Q6_Vqf16_vsub_VhfVhf | function | ||
| 3675 | core::core_arch::hexagon::v64 | Q6_Vqf16_vsub_Vqf16Vhf | function | ||
| 3676 | core::core_arch::hexagon::v64 | Q6_Vqf16_vsub_Vqf16Vqf16 | function | ||
| 3677 | core::core_arch::hexagon::v64 | Q6_Vqf32_vadd_Vqf32Vqf32 | function | ||
| 3678 | core::core_arch::hexagon::v64 | Q6_Vqf32_vadd_Vqf32Vsf | function | ||
| 3679 | core::core_arch::hexagon::v64 | Q6_Vqf32_vadd_VsfVsf | function | ||
| 3680 | core::core_arch::hexagon::v64 | Q6_Vqf32_vmpy_Vqf32Vqf32 | function | ||
| 3681 | core::core_arch::hexagon::v64 | Q6_Vqf32_vmpy_VsfVsf | function | ||
| 3682 | core::core_arch::hexagon::v64 | Q6_Vqf32_vsub_Vqf32Vqf32 | function | ||
| 3683 | core::core_arch::hexagon::v64 | Q6_Vqf32_vsub_Vqf32Vsf | function | ||
| 3684 | core::core_arch::hexagon::v64 | Q6_Vqf32_vsub_VsfVsf | function | ||
| 3685 | core::core_arch::hexagon::v64 | Q6_Vsf_equals_Vqf32 | function | ||
| 3686 | core::core_arch::hexagon::v64 | Q6_Vsf_equals_Vw | function | ||
| 3687 | core::core_arch::hexagon::v64 | Q6_Vsf_vabs_Vsf | function | ||
| 3688 | core::core_arch::hexagon::v64 | Q6_Vsf_vadd_VsfVsf | function | ||
| 3689 | core::core_arch::hexagon::v64 | Q6_Vsf_vdmpy_VhfVhf | function | ||
| 3690 | core::core_arch::hexagon::v64 | Q6_Vsf_vdmpyacc_VsfVhfVhf | function | ||
| 3691 | core::core_arch::hexagon::v64 | Q6_Vsf_vfmax_VsfVsf | function | ||
| 3692 | core::core_arch::hexagon::v64 | Q6_Vsf_vfmin_VsfVsf | function | ||
| 3693 | core::core_arch::hexagon::v64 | Q6_Vsf_vfneg_Vsf | function | ||
| 3694 | core::core_arch::hexagon::v64 | Q6_Vsf_vmax_VsfVsf | function | ||
| 3695 | core::core_arch::hexagon::v64 | Q6_Vsf_vmin_VsfVsf | function | ||
| 3696 | core::core_arch::hexagon::v64 | Q6_Vsf_vmpy_VsfVsf | function | ||
| 3697 | core::core_arch::hexagon::v64 | Q6_Vsf_vsub_VsfVsf | function | ||
| 3698 | core::core_arch::hexagon::v64 | Q6_Vub_vabsdiff_VubVub | function | ||
| 3699 | core::core_arch::hexagon::v64 | Q6_Vub_vadd_VubVb_sat | function | ||
| 3700 | core::core_arch::hexagon::v64 | Q6_Vub_vadd_VubVub_sat | function | ||
| 3701 | core::core_arch::hexagon::v64 | Q6_Vub_vasr_VhVhR_rnd_sat | function | ||
| 3702 | core::core_arch::hexagon::v64 | Q6_Vub_vasr_VhVhR_sat | function | ||
| 3703 | core::core_arch::hexagon::v64 | Q6_Vub_vasr_VuhVuhR_rnd_sat | function | ||
| 3704 | core::core_arch::hexagon::v64 | Q6_Vub_vasr_VuhVuhR_sat | function | ||
| 3705 | core::core_arch::hexagon::v64 | Q6_Vub_vasr_WuhVub_rnd_sat | function | ||
| 3706 | core::core_arch::hexagon::v64 | Q6_Vub_vasr_WuhVub_sat | function | ||
| 3707 | core::core_arch::hexagon::v64 | Q6_Vub_vavg_VubVub | function | ||
| 3708 | core::core_arch::hexagon::v64 | Q6_Vub_vavg_VubVub_rnd | function | ||
| 3709 | core::core_arch::hexagon::v64 | Q6_Vub_vcvt_VhfVhf | function | ||
| 3710 | core::core_arch::hexagon::v64 | Q6_Vub_vlsr_VubR | function | ||
| 3711 | core::core_arch::hexagon::v64 | Q6_Vub_vmax_VubVub | function | ||
| 3712 | core::core_arch::hexagon::v64 | Q6_Vub_vmin_VubVub | function | ||
| 3713 | core::core_arch::hexagon::v64 | Q6_Vub_vpack_VhVh_sat | function | ||
| 3714 | core::core_arch::hexagon::v64 | Q6_Vub_vround_VhVh_sat | function | ||
| 3715 | core::core_arch::hexagon::v64 | Q6_Vub_vround_VuhVuh_sat | function | ||
| 3716 | core::core_arch::hexagon::v64 | Q6_Vub_vsat_VhVh | function | ||
| 3717 | core::core_arch::hexagon::v64 | Q6_Vub_vsub_VubVb_sat | function | ||
| 3718 | core::core_arch::hexagon::v64 | Q6_Vub_vsub_VubVub_sat | function | ||
| 3719 | core::core_arch::hexagon::v64 | Q6_Vuh_vabsdiff_VhVh | function | ||
| 3720 | core::core_arch::hexagon::v64 | Q6_Vuh_vabsdiff_VuhVuh | function | ||
| 3721 | core::core_arch::hexagon::v64 | Q6_Vuh_vadd_VuhVuh_sat | function | ||
| 3722 | core::core_arch::hexagon::v64 | Q6_Vuh_vasr_VuwVuwR_rnd_sat | function | ||
| 3723 | core::core_arch::hexagon::v64 | Q6_Vuh_vasr_VuwVuwR_sat | function | ||
| 3724 | core::core_arch::hexagon::v64 | Q6_Vuh_vasr_VwVwR_rnd_sat | function | ||
| 3725 | core::core_arch::hexagon::v64 | Q6_Vuh_vasr_VwVwR_sat | function | ||
| 3726 | core::core_arch::hexagon::v64 | Q6_Vuh_vasr_WwVuh_rnd_sat | function | ||
| 3727 | core::core_arch::hexagon::v64 | Q6_Vuh_vasr_WwVuh_sat | function | ||
| 3728 | core::core_arch::hexagon::v64 | Q6_Vuh_vavg_VuhVuh | function | ||
| 3729 | core::core_arch::hexagon::v64 | Q6_Vuh_vavg_VuhVuh_rnd | function | ||
| 3730 | core::core_arch::hexagon::v64 | Q6_Vuh_vcl0_Vuh | function | ||
| 3731 | core::core_arch::hexagon::v64 | Q6_Vuh_vcvt_Vhf | function | ||
| 3732 | core::core_arch::hexagon::v64 | Q6_Vuh_vlsr_VuhR | function | ||
| 3733 | core::core_arch::hexagon::v64 | Q6_Vuh_vmax_VuhVuh | function | ||
| 3734 | core::core_arch::hexagon::v64 | Q6_Vuh_vmin_VuhVuh | function | ||
| 3735 | core::core_arch::hexagon::v64 | Q6_Vuh_vmpy_VuhVuh_rs16 | function | ||
| 3736 | core::core_arch::hexagon::v64 | Q6_Vuh_vpack_VwVw_sat | function | ||
| 3737 | core::core_arch::hexagon::v64 | Q6_Vuh_vround_VuwVuw_sat | function | ||
| 3738 | core::core_arch::hexagon::v64 | Q6_Vuh_vround_VwVw_sat | function | ||
| 3739 | core::core_arch::hexagon::v64 | Q6_Vuh_vsat_VuwVuw | function | ||
| 3740 | core::core_arch::hexagon::v64 | Q6_Vuh_vsub_VuhVuh_sat | function | ||
| 3741 | core::core_arch::hexagon::v64 | Q6_Vuw_vabsdiff_VwVw | function | ||
| 3742 | core::core_arch::hexagon::v64 | Q6_Vuw_vadd_VuwVuw_sat | function | ||
| 3743 | core::core_arch::hexagon::v64 | Q6_Vuw_vavg_VuwVuw | function | ||
| 3744 | core::core_arch::hexagon::v64 | Q6_Vuw_vavg_VuwVuw_rnd | function | ||
| 3745 | core::core_arch::hexagon::v64 | Q6_Vuw_vcl0_Vuw | function | ||
| 3746 | core::core_arch::hexagon::v64 | Q6_Vuw_vlsr_VuwR | function | ||
| 3747 | core::core_arch::hexagon::v64 | Q6_Vuw_vmpye_VuhRuh | function | ||
| 3748 | core::core_arch::hexagon::v64 | Q6_Vuw_vmpyeacc_VuwVuhRuh | function | ||
| 3749 | core::core_arch::hexagon::v64 | Q6_Vuw_vrmpy_VubRub | function | ||
| 3750 | core::core_arch::hexagon::v64 | Q6_Vuw_vrmpy_VubVub | function | ||
| 3751 | core::core_arch::hexagon::v64 | Q6_Vuw_vrmpyacc_VuwVubRub | function | ||
| 3752 | core::core_arch::hexagon::v64 | Q6_Vuw_vrmpyacc_VuwVubVub | function | ||
| 3753 | core::core_arch::hexagon::v64 | Q6_Vuw_vrotr_VuwVuw | function | ||
| 3754 | core::core_arch::hexagon::v64 | Q6_Vuw_vsub_VuwVuw_sat | function | ||
| 3755 | core::core_arch::hexagon::v64 | Q6_Vw_condacc_QVwVw | function | ||
| 3756 | core::core_arch::hexagon::v64 | Q6_Vw_condacc_QnVwVw | function | ||
| 3757 | core::core_arch::hexagon::v64 | Q6_Vw_condnac_QVwVw | function | ||
| 3758 | core::core_arch::hexagon::v64 | Q6_Vw_condnac_QnVwVw | function | ||
| 3759 | core::core_arch::hexagon::v64 | Q6_Vw_equals_Vsf | function | ||
| 3760 | core::core_arch::hexagon::v64 | Q6_Vw_prefixsum_Q | function | ||
| 3761 | core::core_arch::hexagon::v64 | Q6_Vw_vabs_Vw | function | ||
| 3762 | core::core_arch::hexagon::v64 | Q6_Vw_vabs_Vw_sat | function | ||
| 3763 | core::core_arch::hexagon::v64 | Q6_Vw_vadd_VwVw | function | ||
| 3764 | core::core_arch::hexagon::v64 | Q6_Vw_vadd_VwVwQ_carry_sat | function | ||
| 3765 | core::core_arch::hexagon::v64 | Q6_Vw_vadd_VwVw_sat | function | ||
| 3766 | core::core_arch::hexagon::v64 | Q6_Vw_vadd_vclb_VwVw | function | ||
| 3767 | core::core_arch::hexagon::v64 | Q6_Vw_vasl_VwR | function | ||
| 3768 | core::core_arch::hexagon::v64 | Q6_Vw_vasl_VwVw | function | ||
| 3769 | core::core_arch::hexagon::v64 | Q6_Vw_vaslacc_VwVwR | function | ||
| 3770 | core::core_arch::hexagon::v64 | Q6_Vw_vasr_VwR | function | ||
| 3771 | core::core_arch::hexagon::v64 | Q6_Vw_vasr_VwVw | function | ||
| 3772 | core::core_arch::hexagon::v64 | Q6_Vw_vasracc_VwVwR | function | ||
| 3773 | core::core_arch::hexagon::v64 | Q6_Vw_vavg_VwVw | function | ||
| 3774 | core::core_arch::hexagon::v64 | Q6_Vw_vavg_VwVw_rnd | function | ||
| 3775 | core::core_arch::hexagon::v64 | Q6_Vw_vdmpy_VhRb | function | ||
| 3776 | core::core_arch::hexagon::v64 | Q6_Vw_vdmpy_VhRh_sat | function | ||
| 3777 | core::core_arch::hexagon::v64 | Q6_Vw_vdmpy_VhRuh_sat | function | ||
| 3778 | core::core_arch::hexagon::v64 | Q6_Vw_vdmpy_VhVh_sat | function | ||
| 3779 | core::core_arch::hexagon::v64 | Q6_Vw_vdmpy_WhRh_sat | function | ||
| 3780 | core::core_arch::hexagon::v64 | Q6_Vw_vdmpy_WhRuh_sat | function | ||
| 3781 | core::core_arch::hexagon::v64 | Q6_Vw_vdmpyacc_VwVhRb | function | ||
| 3782 | core::core_arch::hexagon::v64 | Q6_Vw_vdmpyacc_VwVhRh_sat | function | ||
| 3783 | core::core_arch::hexagon::v64 | Q6_Vw_vdmpyacc_VwVhRuh_sat | function | ||
| 3784 | core::core_arch::hexagon::v64 | Q6_Vw_vdmpyacc_VwVhVh_sat | function | ||
| 3785 | core::core_arch::hexagon::v64 | Q6_Vw_vdmpyacc_VwWhRh_sat | function | ||
| 3786 | core::core_arch::hexagon::v64 | Q6_Vw_vdmpyacc_VwWhRuh_sat | function | ||
| 3787 | core::core_arch::hexagon::v64 | Q6_Vw_vfmv_Vw | function | ||
| 3788 | core::core_arch::hexagon::v64 | Q6_Vw_vinsert_VwR | function | ||
| 3789 | core::core_arch::hexagon::v64 | Q6_Vw_vlsr_VwVw | function | ||
| 3790 | core::core_arch::hexagon::v64 | Q6_Vw_vmax_VwVw | function | ||
| 3791 | core::core_arch::hexagon::v64 | Q6_Vw_vmin_VwVw | function | ||
| 3792 | core::core_arch::hexagon::v64 | Q6_Vw_vmpye_VwVuh | function | ||
| 3793 | core::core_arch::hexagon::v64 | Q6_Vw_vmpyi_VwRb | function | ||
| 3794 | core::core_arch::hexagon::v64 | Q6_Vw_vmpyi_VwRh | function | ||
| 3795 | core::core_arch::hexagon::v64 | Q6_Vw_vmpyi_VwRub | function | ||
| 3796 | core::core_arch::hexagon::v64 | Q6_Vw_vmpyiacc_VwVwRb | function | ||
| 3797 | core::core_arch::hexagon::v64 | Q6_Vw_vmpyiacc_VwVwRh | function | ||
| 3798 | core::core_arch::hexagon::v64 | Q6_Vw_vmpyiacc_VwVwRub | function | ||
| 3799 | core::core_arch::hexagon::v64 | Q6_Vw_vmpyie_VwVuh | function | ||
| 3800 | core::core_arch::hexagon::v64 | Q6_Vw_vmpyieacc_VwVwVh | function | ||
| 3801 | core::core_arch::hexagon::v64 | Q6_Vw_vmpyieacc_VwVwVuh | function | ||
| 3802 | core::core_arch::hexagon::v64 | Q6_Vw_vmpyieo_VhVh | function | ||
| 3803 | core::core_arch::hexagon::v64 | Q6_Vw_vmpyio_VwVh | function | ||
| 3804 | core::core_arch::hexagon::v64 | Q6_Vw_vmpyo_VwVh_s1_rnd_sat | function | ||
| 3805 | core::core_arch::hexagon::v64 | Q6_Vw_vmpyo_VwVh_s1_sat | function | ||
| 3806 | core::core_arch::hexagon::v64 | Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shift | function | ||
| 3807 | core::core_arch::hexagon::v64 | Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shift | function | ||
| 3808 | core::core_arch::hexagon::v64 | Q6_Vw_vnavg_VwVw | function | ||
| 3809 | core::core_arch::hexagon::v64 | Q6_Vw_vnormamt_Vw | function | ||
| 3810 | core::core_arch::hexagon::v64 | Q6_Vw_vrmpy_VbVb | function | ||
| 3811 | core::core_arch::hexagon::v64 | Q6_Vw_vrmpy_VubRb | function | ||
| 3812 | core::core_arch::hexagon::v64 | Q6_Vw_vrmpy_VubVb | function | ||
| 3813 | core::core_arch::hexagon::v64 | Q6_Vw_vrmpyacc_VwVbVb | function | ||
| 3814 | core::core_arch::hexagon::v64 | Q6_Vw_vrmpyacc_VwVubRb | function | ||
| 3815 | core::core_arch::hexagon::v64 | Q6_Vw_vrmpyacc_VwVubVb | function | ||
| 3816 | core::core_arch::hexagon::v64 | Q6_Vw_vsatdw_VwVw | function | ||
| 3817 | core::core_arch::hexagon::v64 | Q6_Vw_vsub_VwVw | function | ||
| 3818 | core::core_arch::hexagon::v64 | Q6_Vw_vsub_VwVw_sat | function | ||
| 3819 | core::core_arch::hexagon::v64 | Q6_W_equals_W | function | ||
| 3820 | core::core_arch::hexagon::v64 | Q6_W_vcombine_VV | function | ||
| 3821 | core::core_arch::hexagon::v64 | Q6_W_vdeal_VVR | function | ||
| 3822 | core::core_arch::hexagon::v64 | Q6_W_vmpye_VwVuh | function | ||
| 3823 | core::core_arch::hexagon::v64 | Q6_W_vmpyoacc_WVwVh | function | ||
| 3824 | core::core_arch::hexagon::v64 | Q6_W_vshuff_VVR | function | ||
| 3825 | core::core_arch::hexagon::v64 | Q6_W_vswap_QVV | function | ||
| 3826 | core::core_arch::hexagon::v64 | Q6_W_vzero | function | ||
| 3827 | core::core_arch::hexagon::v64 | Q6_Wb_vadd_WbWb | function | ||
| 3828 | core::core_arch::hexagon::v64 | Q6_Wb_vadd_WbWb_sat | function | ||
| 3829 | core::core_arch::hexagon::v64 | Q6_Wb_vshuffoe_VbVb | function | ||
| 3830 | core::core_arch::hexagon::v64 | Q6_Wb_vsub_WbWb | function | ||
| 3831 | core::core_arch::hexagon::v64 | Q6_Wb_vsub_WbWb_sat | function | ||
| 3832 | core::core_arch::hexagon::v64 | Q6_Wh_vadd_VubVub | function | ||
| 3833 | core::core_arch::hexagon::v64 | Q6_Wh_vadd_WhWh | function | ||
| 3834 | core::core_arch::hexagon::v64 | Q6_Wh_vadd_WhWh_sat | function | ||
| 3835 | core::core_arch::hexagon::v64 | Q6_Wh_vaddacc_WhVubVub | function | ||
| 3836 | core::core_arch::hexagon::v64 | Q6_Wh_vdmpy_WubRb | function | ||
| 3837 | core::core_arch::hexagon::v64 | Q6_Wh_vdmpyacc_WhWubRb | function | ||
| 3838 | core::core_arch::hexagon::v64 | Q6_Wh_vlut16_VbVhI | function | ||
| 3839 | core::core_arch::hexagon::v64 | Q6_Wh_vlut16_VbVhR | function | ||
| 3840 | core::core_arch::hexagon::v64 | Q6_Wh_vlut16_VbVhR_nomatch | function | ||
| 3841 | core::core_arch::hexagon::v64 | Q6_Wh_vlut16or_WhVbVhI | function | ||
| 3842 | core::core_arch::hexagon::v64 | Q6_Wh_vlut16or_WhVbVhR | function | ||
| 3843 | core::core_arch::hexagon::v64 | Q6_Wh_vmpa_WubRb | function | ||
| 3844 | core::core_arch::hexagon::v64 | Q6_Wh_vmpa_WubRub | function | ||
| 3845 | core::core_arch::hexagon::v64 | Q6_Wh_vmpa_WubWb | function | ||
| 3846 | core::core_arch::hexagon::v64 | Q6_Wh_vmpa_WubWub | function | ||
| 3847 | core::core_arch::hexagon::v64 | Q6_Wh_vmpaacc_WhWubRb | function | ||
| 3848 | core::core_arch::hexagon::v64 | Q6_Wh_vmpaacc_WhWubRub | function | ||
| 3849 | core::core_arch::hexagon::v64 | Q6_Wh_vmpy_VbVb | function | ||
| 3850 | core::core_arch::hexagon::v64 | Q6_Wh_vmpy_VubRb | function | ||
| 3851 | core::core_arch::hexagon::v64 | Q6_Wh_vmpy_VubVb | function | ||
| 3852 | core::core_arch::hexagon::v64 | Q6_Wh_vmpyacc_WhVbVb | function | ||
| 3853 | core::core_arch::hexagon::v64 | Q6_Wh_vmpyacc_WhVubRb | function | ||
| 3854 | core::core_arch::hexagon::v64 | Q6_Wh_vmpyacc_WhVubVb | function | ||
| 3855 | core::core_arch::hexagon::v64 | Q6_Wh_vshuffoe_VhVh | function | ||
| 3856 | core::core_arch::hexagon::v64 | Q6_Wh_vsub_VubVub | function | ||
| 3857 | core::core_arch::hexagon::v64 | Q6_Wh_vsub_WhWh | function | ||
| 3858 | core::core_arch::hexagon::v64 | Q6_Wh_vsub_WhWh_sat | function | ||
| 3859 | core::core_arch::hexagon::v64 | Q6_Wh_vsxt_Vb | function | ||
| 3860 | core::core_arch::hexagon::v64 | Q6_Wh_vtmpy_WbRb | function | ||
| 3861 | core::core_arch::hexagon::v64 | Q6_Wh_vtmpy_WubRb | function | ||
| 3862 | core::core_arch::hexagon::v64 | Q6_Wh_vtmpyacc_WhWbRb | function | ||
| 3863 | core::core_arch::hexagon::v64 | Q6_Wh_vtmpyacc_WhWubRb | function | ||
| 3864 | core::core_arch::hexagon::v64 | Q6_Wh_vunpack_Vb | function | ||
| 3865 | core::core_arch::hexagon::v64 | Q6_Wh_vunpackoor_WhVb | function | ||
| 3866 | core::core_arch::hexagon::v64 | Q6_Whf_vcvt2_Vb | function | ||
| 3867 | core::core_arch::hexagon::v64 | Q6_Whf_vcvt2_Vub | function | ||
| 3868 | core::core_arch::hexagon::v64 | Q6_Whf_vcvt_V | function | ||
| 3869 | core::core_arch::hexagon::v64 | Q6_Whf_vcvt_Vb | function | ||
| 3870 | core::core_arch::hexagon::v64 | Q6_Whf_vcvt_Vub | function | ||
| 3871 | core::core_arch::hexagon::v64 | Q6_Wqf32_vmpy_VhfVhf | function | ||
| 3872 | core::core_arch::hexagon::v64 | Q6_Wqf32_vmpy_Vqf16Vhf | function | ||
| 3873 | core::core_arch::hexagon::v64 | Q6_Wqf32_vmpy_Vqf16Vqf16 | function | ||
| 3874 | core::core_arch::hexagon::v64 | Q6_Wsf_vadd_VhfVhf | function | ||
| 3875 | core::core_arch::hexagon::v64 | Q6_Wsf_vcvt_Vhf | function | ||
| 3876 | core::core_arch::hexagon::v64 | Q6_Wsf_vmpy_VhfVhf | function | ||
| 3877 | core::core_arch::hexagon::v64 | Q6_Wsf_vmpyacc_WsfVhfVhf | function | ||
| 3878 | core::core_arch::hexagon::v64 | Q6_Wsf_vsub_VhfVhf | function | ||
| 3879 | core::core_arch::hexagon::v64 | Q6_Wub_vadd_WubWub_sat | function | ||
| 3880 | core::core_arch::hexagon::v64 | Q6_Wub_vsub_WubWub_sat | function | ||
| 3881 | core::core_arch::hexagon::v64 | Q6_Wuh_vadd_WuhWuh_sat | function | ||
| 3882 | core::core_arch::hexagon::v64 | Q6_Wuh_vmpy_VubRub | function | ||
| 3883 | core::core_arch::hexagon::v64 | Q6_Wuh_vmpy_VubVub | function | ||
| 3884 | core::core_arch::hexagon::v64 | Q6_Wuh_vmpyacc_WuhVubRub | function | ||
| 3885 | core::core_arch::hexagon::v64 | Q6_Wuh_vmpyacc_WuhVubVub | function | ||
| 3886 | core::core_arch::hexagon::v64 | Q6_Wuh_vsub_WuhWuh_sat | function | ||
| 3887 | core::core_arch::hexagon::v64 | Q6_Wuh_vunpack_Vub | function | ||
| 3888 | core::core_arch::hexagon::v64 | Q6_Wuh_vzxt_Vub | function | ||
| 3889 | core::core_arch::hexagon::v64 | Q6_Wuw_vadd_WuwWuw_sat | function | ||
| 3890 | core::core_arch::hexagon::v64 | Q6_Wuw_vdsad_WuhRuh | function | ||
| 3891 | core::core_arch::hexagon::v64 | Q6_Wuw_vdsadacc_WuwWuhRuh | function | ||
| 3892 | core::core_arch::hexagon::v64 | Q6_Wuw_vmpy_VuhRuh | function | ||
| 3893 | core::core_arch::hexagon::v64 | Q6_Wuw_vmpy_VuhVuh | function | ||
| 3894 | core::core_arch::hexagon::v64 | Q6_Wuw_vmpyacc_WuwVuhRuh | function | ||
| 3895 | core::core_arch::hexagon::v64 | Q6_Wuw_vmpyacc_WuwVuhVuh | function | ||
| 3896 | core::core_arch::hexagon::v64 | Q6_Wuw_vrmpy_WubRubI | function | ||
| 3897 | core::core_arch::hexagon::v64 | Q6_Wuw_vrmpyacc_WuwWubRubI | function | ||
| 3898 | core::core_arch::hexagon::v64 | Q6_Wuw_vrsad_WubRubI | function | ||
| 3899 | core::core_arch::hexagon::v64 | Q6_Wuw_vrsadacc_WuwWubRubI | function | ||
| 3900 | core::core_arch::hexagon::v64 | Q6_Wuw_vsub_WuwWuw_sat | function | ||
| 3901 | core::core_arch::hexagon::v64 | Q6_Wuw_vunpack_Vuh | function | ||
| 3902 | core::core_arch::hexagon::v64 | Q6_Wuw_vzxt_Vuh | function | ||
| 3903 | core::core_arch::hexagon::v64 | Q6_Ww_v6mpy_WubWbI_h | function | ||
| 3904 | core::core_arch::hexagon::v64 | Q6_Ww_v6mpy_WubWbI_v | function | ||
| 3905 | core::core_arch::hexagon::v64 | Q6_Ww_v6mpyacc_WwWubWbI_h | function | ||
| 3906 | core::core_arch::hexagon::v64 | Q6_Ww_v6mpyacc_WwWubWbI_v | function | ||
| 3907 | core::core_arch::hexagon::v64 | Q6_Ww_vadd_VhVh | function | ||
| 3908 | core::core_arch::hexagon::v64 | Q6_Ww_vadd_VuhVuh | function | ||
| 3909 | core::core_arch::hexagon::v64 | Q6_Ww_vadd_WwWw | function | ||
| 3910 | core::core_arch::hexagon::v64 | Q6_Ww_vadd_WwWw_sat | function | ||
| 3911 | core::core_arch::hexagon::v64 | Q6_Ww_vaddacc_WwVhVh | function | ||
| 3912 | core::core_arch::hexagon::v64 | Q6_Ww_vaddacc_WwVuhVuh | function | ||
| 3913 | core::core_arch::hexagon::v64 | Q6_Ww_vasrinto_WwVwVw | function | ||
| 3914 | core::core_arch::hexagon::v64 | Q6_Ww_vdmpy_WhRb | function | ||
| 3915 | core::core_arch::hexagon::v64 | Q6_Ww_vdmpyacc_WwWhRb | function | ||
| 3916 | core::core_arch::hexagon::v64 | Q6_Ww_vmpa_WhRb | function | ||
| 3917 | core::core_arch::hexagon::v64 | Q6_Ww_vmpa_WuhRb | function | ||
| 3918 | core::core_arch::hexagon::v64 | Q6_Ww_vmpaacc_WwWhRb | function | ||
| 3919 | core::core_arch::hexagon::v64 | Q6_Ww_vmpaacc_WwWuhRb | function | ||
| 3920 | core::core_arch::hexagon::v64 | Q6_Ww_vmpy_VhRh | function | ||
| 3921 | core::core_arch::hexagon::v64 | Q6_Ww_vmpy_VhVh | function | ||
| 3922 | core::core_arch::hexagon::v64 | Q6_Ww_vmpy_VhVuh | function | ||
| 3923 | core::core_arch::hexagon::v64 | Q6_Ww_vmpyacc_WwVhRh | function | ||
| 3924 | core::core_arch::hexagon::v64 | Q6_Ww_vmpyacc_WwVhRh_sat | function | ||
| 3925 | core::core_arch::hexagon::v64 | Q6_Ww_vmpyacc_WwVhVh | function | ||
| 3926 | core::core_arch::hexagon::v64 | Q6_Ww_vmpyacc_WwVhVuh | function | ||
| 3927 | core::core_arch::hexagon::v64 | Q6_Ww_vrmpy_WubRbI | function | ||
| 3928 | core::core_arch::hexagon::v64 | Q6_Ww_vrmpyacc_WwWubRbI | function | ||
| 3929 | core::core_arch::hexagon::v64 | Q6_Ww_vsub_VhVh | function | ||
| 3930 | core::core_arch::hexagon::v64 | Q6_Ww_vsub_VuhVuh | function | ||
| 3931 | core::core_arch::hexagon::v64 | Q6_Ww_vsub_WwWw | function | ||
| 3932 | core::core_arch::hexagon::v64 | Q6_Ww_vsub_WwWw_sat | function | ||
| 3933 | core::core_arch::hexagon::v64 | Q6_Ww_vsxt_Vh | function | ||
| 3934 | core::core_arch::hexagon::v64 | Q6_Ww_vtmpy_WhRb | function | ||
| 3935 | core::core_arch::hexagon::v64 | Q6_Ww_vtmpyacc_WwWhRb | function | ||
| 3936 | core::core_arch::hexagon::v64 | Q6_Ww_vunpack_Vh | function | ||
| 3937 | core::core_arch::hexagon::v64 | Q6_Ww_vunpackoor_WwVh | function | ||
| 3938 | core::core_arch::hexagon::v64 | Q6_vgather_AQRMVh | function | ||
| 3939 | core::core_arch::hexagon::v64 | Q6_vgather_AQRMVw | function | ||
| 3940 | core::core_arch::hexagon::v64 | Q6_vgather_AQRMWw | function | ||
| 3941 | core::core_arch::hexagon::v64 | Q6_vgather_ARMVh | function | ||
| 3942 | core::core_arch::hexagon::v64 | Q6_vgather_ARMVw | function | ||
| 3943 | core::core_arch::hexagon::v64 | Q6_vgather_ARMWw | function | ||
| 3944 | core::core_arch::hexagon::v64 | Q6_vmem_QRIV | function | ||
| 3945 | core::core_arch::hexagon::v64 | Q6_vmem_QRIV_nt | function | ||
| 3946 | core::core_arch::hexagon::v64 | Q6_vmem_QnRIV | function | ||
| 3947 | core::core_arch::hexagon::v64 | Q6_vmem_QnRIV_nt | function | ||
| 3948 | core::core_arch::hexagon::v64 | Q6_vscatter_QRMVhV | function | ||
| 3949 | core::core_arch::hexagon::v64 | Q6_vscatter_QRMVwV | function | ||
| 3950 | core::core_arch::hexagon::v64 | Q6_vscatter_QRMWwV | function | ||
| 3951 | core::core_arch::hexagon::v64 | Q6_vscatter_RMVhV | function | ||
| 3952 | core::core_arch::hexagon::v64 | Q6_vscatter_RMVwV | function | ||
| 3953 | core::core_arch::hexagon::v64 | Q6_vscatter_RMWwV | function | ||
| 3954 | core::core_arch::hexagon::v64 | Q6_vscatteracc_RMVhV | function | ||
| 3955 | core::core_arch::hexagon::v64 | Q6_vscatteracc_RMVwV | function | ||
| 3956 | core::core_arch::hexagon::v64 | Q6_vscatteracc_RMWwV | function | ||
| 3957 | core::core_arch::loongarch32 | cacop | function | ||
| 3958 | core::core_arch::loongarch32 | csrrd | function | ||
| 3959 | core::core_arch::loongarch32 | csrwr | function | ||
| 3960 | core::core_arch::loongarch32 | csrxchg | function | ||
| 3961 | core::core_arch::loongarch64 | asrtgt | function | ||
| 3962 | core::core_arch::loongarch64 | asrtle | function | ||
| 3963 | core::core_arch::loongarch64 | cacop | function | ||
| 3964 | core::core_arch::loongarch64 | csrrd | function | ||
| 3965 | core::core_arch::loongarch64 | csrwr | function | ||
| 3966 | core::core_arch::loongarch64 | csrxchg | function | ||
| 3967 | core::core_arch::loongarch64 | iocsrrd_d | function | ||
| 3968 | core::core_arch::loongarch64 | iocsrwr_d | function | ||
| 3969 | core::core_arch::loongarch64 | lddir | function | ||
| 3970 | core::core_arch::loongarch64 | ldpte | function | ||
| 3971 | core::core_arch::loongarch64::lasx::generated | lasx_xvld | function | ||
| 3972 | core::core_arch::loongarch64::lasx::generated | lasx_xvldrepl_b | function | ||
| 3973 | core::core_arch::loongarch64::lasx::generated | lasx_xvldrepl_d | function | ||
| 3974 | core::core_arch::loongarch64::lasx::generated | lasx_xvldrepl_h | function | ||
| 3975 | core::core_arch::loongarch64::lasx::generated | lasx_xvldrepl_w | function | ||
| 3976 | core::core_arch::loongarch64::lasx::generated | lasx_xvldx | function | ||
| 3977 | core::core_arch::loongarch64::lasx::generated | lasx_xvst | function | ||
| 3978 | core::core_arch::loongarch64::lasx::generated | lasx_xvstelm_b | function | ||
| 3979 | core::core_arch::loongarch64::lasx::generated | lasx_xvstelm_d | function | ||
| 3980 | core::core_arch::loongarch64::lasx::generated | lasx_xvstelm_h | function | ||
| 3981 | core::core_arch::loongarch64::lasx::generated | lasx_xvstelm_w | function | ||
| 3982 | core::core_arch::loongarch64::lasx::generated | lasx_xvstx | function | ||
| 3983 | core::core_arch::loongarch64::lsx::generated | lsx_vld | function | ||
| 3984 | core::core_arch::loongarch64::lsx::generated | lsx_vldrepl_b | function | ||
| 3985 | core::core_arch::loongarch64::lsx::generated | lsx_vldrepl_d | function | ||
| 3986 | core::core_arch::loongarch64::lsx::generated | lsx_vldrepl_h | function | ||
| 3987 | core::core_arch::loongarch64::lsx::generated | lsx_vldrepl_w | function | ||
| 3988 | core::core_arch::loongarch64::lsx::generated | lsx_vldx | function | ||
| 3989 | core::core_arch::loongarch64::lsx::generated | lsx_vst | function | ||
| 3990 | core::core_arch::loongarch64::lsx::generated | lsx_vstelm_b | function | ||
| 3991 | core::core_arch::loongarch64::lsx::generated | lsx_vstelm_d | function | ||
| 3992 | core::core_arch::loongarch64::lsx::generated | lsx_vstelm_h | function | ||
| 3993 | core::core_arch::loongarch64::lsx::generated | lsx_vstelm_w | function | ||
| 3994 | core::core_arch::loongarch64::lsx::generated | lsx_vstx | function | ||
| 3995 | core::core_arch::loongarch_shared | brk | function | ||
| 3996 | core::core_arch::loongarch_shared | iocsrrd_b | function | ||
| 3997 | core::core_arch::loongarch_shared | iocsrrd_h | function | ||
| 3998 | core::core_arch::loongarch_shared | iocsrrd_w | function | ||
| 3999 | core::core_arch::loongarch_shared | iocsrwr_b | function | ||
| 4000 | core::core_arch::loongarch_shared | iocsrwr_h | function | ||
| 4001 | core::core_arch::loongarch_shared | iocsrwr_w | function | ||
| 4002 | core::core_arch::loongarch_shared | movgr2fcsr | function | ||
| 4003 | core::core_arch::loongarch_shared | syscall | function | ||
| 4004 | core::core_arch::mips | break_ | function | ||
| 4005 | core::core_arch::nvptx | __assert_fail | function | ||
| 4006 | core::core_arch::nvptx | _block_dim_x | function | ||
| 4007 | core::core_arch::nvptx | _block_dim_y | function | ||
| 4008 | core::core_arch::nvptx | _block_dim_z | function | ||
| 4009 | core::core_arch::nvptx | _block_idx_x | function | ||
| 4010 | core::core_arch::nvptx | _block_idx_y | function | ||
| 4011 | core::core_arch::nvptx | _block_idx_z | function | ||
| 4012 | core::core_arch::nvptx | _grid_dim_x | function | ||
| 4013 | core::core_arch::nvptx | _grid_dim_y | function | ||
| 4014 | core::core_arch::nvptx | _grid_dim_z | function | ||
| 4015 | core::core_arch::nvptx | _syncthreads | function | ||
| 4016 | core::core_arch::nvptx | _thread_idx_x | function | ||
| 4017 | core::core_arch::nvptx | _thread_idx_y | function | ||
| 4018 | core::core_arch::nvptx | _thread_idx_z | function | ||
| 4019 | core::core_arch::nvptx | free | function | ||
| 4020 | core::core_arch::nvptx | malloc | function | ||
| 4021 | core::core_arch::nvptx | trap | function | ||
| 4022 | core::core_arch::nvptx | vprintf | function | ||
| 4023 | core::core_arch::nvptx::packed | f16x2_add | function | ||
| 4024 | core::core_arch::nvptx::packed | f16x2_fma | function | ||
| 4025 | core::core_arch::nvptx::packed | f16x2_max | function | ||
| 4026 | core::core_arch::nvptx::packed | f16x2_max_nan | function | ||
| 4027 | core::core_arch::nvptx::packed | f16x2_min | function | ||
| 4028 | core::core_arch::nvptx::packed | f16x2_min_nan | function | ||
| 4029 | core::core_arch::nvptx::packed | f16x2_mul | function | ||
| 4030 | core::core_arch::nvptx::packed | f16x2_neg | function | ||
| 4031 | core::core_arch::nvptx::packed | f16x2_sub | function | ||
| 4032 | core::core_arch::powerpc | trap | function | ||
| 4033 | core::core_arch::powerpc64::vsx | vec_xl_len | function | ||
| 4034 | core::core_arch::powerpc64::vsx | vec_xst_len | function | ||
| 4035 | core::core_arch::powerpc::altivec | vec_abs | function | ||
| 4036 | core::core_arch::powerpc::altivec | vec_abss | function | ||
| 4037 | core::core_arch::powerpc::altivec | vec_add | function | ||
| 4038 | core::core_arch::powerpc::altivec | vec_addc | function | ||
| 4039 | core::core_arch::powerpc::altivec | vec_adde | function | ||
| 4040 | core::core_arch::powerpc::altivec | vec_adds | function | ||
| 4041 | core::core_arch::powerpc::altivec | vec_all_eq | function | ||
| 4042 | core::core_arch::powerpc::altivec | vec_all_ge | function | ||
| 4043 | core::core_arch::powerpc::altivec | vec_all_gt | function | ||
| 4044 | core::core_arch::powerpc::altivec | vec_all_in | function | ||
| 4045 | core::core_arch::powerpc::altivec | vec_all_le | function | ||
| 4046 | core::core_arch::powerpc::altivec | vec_all_lt | function | ||
| 4047 | core::core_arch::powerpc::altivec | vec_all_nan | function | ||
| 4048 | core::core_arch::powerpc::altivec | vec_all_ne | function | ||
| 4049 | core::core_arch::powerpc::altivec | vec_all_nge | function | ||
| 4050 | core::core_arch::powerpc::altivec | vec_all_ngt | function | ||
| 4051 | core::core_arch::powerpc::altivec | vec_all_nle | function | ||
| 4052 | core::core_arch::powerpc::altivec | vec_all_nlt | function | ||
| 4053 | core::core_arch::powerpc::altivec | vec_all_numeric | function | ||
| 4054 | core::core_arch::powerpc::altivec | vec_and | function | ||
| 4055 | core::core_arch::powerpc::altivec | vec_andc | function | ||
| 4056 | core::core_arch::powerpc::altivec | vec_any_eq | function | ||
| 4057 | core::core_arch::powerpc::altivec | vec_any_ge | function | ||
| 4058 | core::core_arch::powerpc::altivec | vec_any_gt | function | ||
| 4059 | core::core_arch::powerpc::altivec | vec_any_le | function | ||
| 4060 | core::core_arch::powerpc::altivec | vec_any_lt | function | ||
| 4061 | core::core_arch::powerpc::altivec | vec_any_nan | function | ||
| 4062 | core::core_arch::powerpc::altivec | vec_any_ne | function | ||
| 4063 | core::core_arch::powerpc::altivec | vec_any_nge | function | ||
| 4064 | core::core_arch::powerpc::altivec | vec_any_ngt | function | ||
| 4065 | core::core_arch::powerpc::altivec | vec_any_nle | function | ||
| 4066 | core::core_arch::powerpc::altivec | vec_any_nlt | function | ||
| 4067 | core::core_arch::powerpc::altivec | vec_any_numeric | function | ||
| 4068 | core::core_arch::powerpc::altivec | vec_any_out | function | ||
| 4069 | core::core_arch::powerpc::altivec | vec_avg | function | ||
| 4070 | core::core_arch::powerpc::altivec | vec_ceil | function | ||
| 4071 | core::core_arch::powerpc::altivec | vec_cmpb | function | ||
| 4072 | core::core_arch::powerpc::altivec | vec_cmpeq | function | ||
| 4073 | core::core_arch::powerpc::altivec | vec_cmpge | function | ||
| 4074 | core::core_arch::powerpc::altivec | vec_cmpgt | function | ||
| 4075 | core::core_arch::powerpc::altivec | vec_cmple | function | ||
| 4076 | core::core_arch::powerpc::altivec | vec_cmplt | function | ||
| 4077 | core::core_arch::powerpc::altivec | vec_cmpne | function | ||
| 4078 | core::core_arch::powerpc::altivec | vec_cntlz | function | ||
| 4079 | core::core_arch::powerpc::altivec | vec_ctf | function | ||
| 4080 | core::core_arch::powerpc::altivec | vec_cts | function | ||
| 4081 | core::core_arch::powerpc::altivec | vec_ctu | function | ||
| 4082 | core::core_arch::powerpc::altivec | vec_expte | function | ||
| 4083 | core::core_arch::powerpc::altivec | vec_extract | function | ||
| 4084 | core::core_arch::powerpc::altivec | vec_floor | function | ||
| 4085 | core::core_arch::powerpc::altivec | vec_insert | function | ||
| 4086 | core::core_arch::powerpc::altivec | vec_ld | function | ||
| 4087 | core::core_arch::powerpc::altivec | vec_lde | function | ||
| 4088 | core::core_arch::powerpc::altivec | vec_ldl | function | ||
| 4089 | core::core_arch::powerpc::altivec | vec_loge | function | ||
| 4090 | core::core_arch::powerpc::altivec | vec_madd | function | ||
| 4091 | core::core_arch::powerpc::altivec | vec_madds | function | ||
| 4092 | core::core_arch::powerpc::altivec | vec_max | function | ||
| 4093 | core::core_arch::powerpc::altivec | vec_mergeh | function | ||
| 4094 | core::core_arch::powerpc::altivec | vec_mergel | function | ||
| 4095 | core::core_arch::powerpc::altivec | vec_mfvscr | function | ||
| 4096 | core::core_arch::powerpc::altivec | vec_min | function | ||
| 4097 | core::core_arch::powerpc::altivec | vec_mladd | function | ||
| 4098 | core::core_arch::powerpc::altivec | vec_mradds | function | ||
| 4099 | core::core_arch::powerpc::altivec | vec_msum | function | ||
| 4100 | core::core_arch::powerpc::altivec | vec_msums | function | ||
| 4101 | core::core_arch::powerpc::altivec | vec_mul | function | ||
| 4102 | core::core_arch::powerpc::altivec | vec_nand | function | ||
| 4103 | core::core_arch::powerpc::altivec | vec_neg | function | ||
| 4104 | core::core_arch::powerpc::altivec | vec_nmsub | function | ||
| 4105 | core::core_arch::powerpc::altivec | vec_nor | function | ||
| 4106 | core::core_arch::powerpc::altivec | vec_or | function | ||
| 4107 | core::core_arch::powerpc::altivec | vec_orc | function | ||
| 4108 | core::core_arch::powerpc::altivec | vec_pack | function | ||
| 4109 | core::core_arch::powerpc::altivec | vec_packs | function | ||
| 4110 | core::core_arch::powerpc::altivec | vec_packsu | function | ||
| 4111 | core::core_arch::powerpc::altivec | vec_rl | function | ||
| 4112 | core::core_arch::powerpc::altivec | vec_round | function | ||
| 4113 | core::core_arch::powerpc::altivec | vec_sel | function | ||
| 4114 | core::core_arch::powerpc::altivec | vec_sl | function | ||
| 4115 | core::core_arch::powerpc::altivec | vec_sld | function | ||
| 4116 | core::core_arch::powerpc::altivec | vec_sldw | function | ||
| 4117 | core::core_arch::powerpc::altivec | vec_sll | function | ||
| 4118 | core::core_arch::powerpc::altivec | vec_slo | function | ||
| 4119 | core::core_arch::powerpc::altivec | vec_slv | function | ||
| 4120 | core::core_arch::powerpc::altivec | vec_splat | function | ||
| 4121 | core::core_arch::powerpc::altivec | vec_splat_s16 | function | ||
| 4122 | core::core_arch::powerpc::altivec | vec_splat_s32 | function | ||
| 4123 | core::core_arch::powerpc::altivec | vec_splat_s8 | function | ||
| 4124 | core::core_arch::powerpc::altivec | vec_splat_u16 | function | ||
| 4125 | core::core_arch::powerpc::altivec | vec_splat_u32 | function | ||
| 4126 | core::core_arch::powerpc::altivec | vec_splat_u8 | function | ||
| 4127 | core::core_arch::powerpc::altivec | vec_splats | function | ||
| 4128 | core::core_arch::powerpc::altivec | vec_sr | function | ||
| 4129 | core::core_arch::powerpc::altivec | vec_sra | function | ||
| 4130 | core::core_arch::powerpc::altivec | vec_srl | function | ||
| 4131 | core::core_arch::powerpc::altivec | vec_sro | function | ||
| 4132 | core::core_arch::powerpc::altivec | vec_srv | function | ||
| 4133 | core::core_arch::powerpc::altivec | vec_st | function | ||
| 4134 | core::core_arch::powerpc::altivec | vec_ste | function | ||
| 4135 | core::core_arch::powerpc::altivec | vec_stl | function | ||
| 4136 | core::core_arch::powerpc::altivec | vec_sub | function | ||
| 4137 | core::core_arch::powerpc::altivec | vec_subc | function | ||
| 4138 | core::core_arch::powerpc::altivec | vec_subs | function | ||
| 4139 | core::core_arch::powerpc::altivec | vec_sum4s | function | ||
| 4140 | core::core_arch::powerpc::altivec | vec_unpackh | function | ||
| 4141 | core::core_arch::powerpc::altivec | vec_unpackl | function | ||
| 4142 | core::core_arch::powerpc::altivec | vec_xl | function | ||
| 4143 | core::core_arch::powerpc::altivec | vec_xor | function | ||
| 4144 | core::core_arch::powerpc::altivec | vec_xst | function | ||
| 4145 | core::core_arch::powerpc::altivec::endian | vec_mule | function | ||
| 4146 | core::core_arch::powerpc::altivec::endian | vec_mulo | function | ||
| 4147 | core::core_arch::powerpc::altivec::endian | vec_perm | function | ||
| 4148 | core::core_arch::powerpc::altivec::endian | vec_sum2s | function | ||
| 4149 | core::core_arch::powerpc::vsx | vec_mergee | function | ||
| 4150 | core::core_arch::powerpc::vsx | vec_mergeo | function | ||
| 4151 | core::core_arch::powerpc::vsx | vec_xxpermdi | function | ||
| 4152 | core::core_arch::riscv64 | hlv_d | function | ||
| 4153 | core::core_arch::riscv64 | hlv_wu | function | ||
| 4154 | core::core_arch::riscv64 | hsv_d | function | ||
| 4155 | core::core_arch::riscv_shared | fence_i | function | ||
| 4156 | core::core_arch::riscv_shared | hfence_gvma | function | ||
| 4157 | core::core_arch::riscv_shared | hfence_gvma_all | function | ||
| 4158 | core::core_arch::riscv_shared | hfence_gvma_gaddr | function | ||
| 4159 | core::core_arch::riscv_shared | hfence_gvma_vmid | function | ||
| 4160 | core::core_arch::riscv_shared | hfence_vvma | function | ||
| 4161 | core::core_arch::riscv_shared | hfence_vvma_all | function | ||
| 4162 | core::core_arch::riscv_shared | hfence_vvma_asid | function | ||
| 4163 | core::core_arch::riscv_shared | hfence_vvma_vaddr | function | ||
| 4164 | core::core_arch::riscv_shared | hinval_gvma | function | ||
| 4165 | core::core_arch::riscv_shared | hinval_gvma_all | function | ||
| 4166 | core::core_arch::riscv_shared | hinval_gvma_gaddr | function | ||
| 4167 | core::core_arch::riscv_shared | hinval_gvma_vmid | function | ||
| 4168 | core::core_arch::riscv_shared | hinval_vvma | function | ||
| 4169 | core::core_arch::riscv_shared | hinval_vvma_all | function | ||
| 4170 | core::core_arch::riscv_shared | hinval_vvma_asid | function | ||
| 4171 | core::core_arch::riscv_shared | hinval_vvma_vaddr | function | ||
| 4172 | core::core_arch::riscv_shared | hlv_b | function | ||
| 4173 | core::core_arch::riscv_shared | hlv_bu | function | ||
| 4174 | core::core_arch::riscv_shared | hlv_h | function | ||
| 4175 | core::core_arch::riscv_shared | hlv_hu | function | ||
| 4176 | core::core_arch::riscv_shared | hlv_w | function | ||
| 4177 | core::core_arch::riscv_shared | hlvx_hu | function | ||
| 4178 | core::core_arch::riscv_shared | hlvx_wu | function | ||
| 4179 | core::core_arch::riscv_shared | hsv_b | function | ||
| 4180 | core::core_arch::riscv_shared | hsv_h | function | ||
| 4181 | core::core_arch::riscv_shared | hsv_w | function | ||
| 4182 | core::core_arch::riscv_shared | sfence_inval_ir | function | ||
| 4183 | core::core_arch::riscv_shared | sfence_vma | function | ||
| 4184 | core::core_arch::riscv_shared | sfence_vma_all | function | ||
| 4185 | core::core_arch::riscv_shared | sfence_vma_asid | function | ||
| 4186 | core::core_arch::riscv_shared | sfence_vma_vaddr | function | ||
| 4187 | core::core_arch::riscv_shared | sfence_w_inval | function | ||
| 4188 | core::core_arch::riscv_shared | sinval_vma | function | ||
| 4189 | core::core_arch::riscv_shared | sinval_vma_all | function | ||
| 4190 | core::core_arch::riscv_shared | sinval_vma_asid | function | ||
| 4191 | core::core_arch::riscv_shared | sinval_vma_vaddr | function | ||
| 4192 | core::core_arch::riscv_shared | wfi | function | ||
| 4193 | core::core_arch::s390x::vector | vec_abs | function | ||
| 4194 | core::core_arch::s390x::vector | vec_add | function | ||
| 4195 | core::core_arch::s390x::vector | vec_add_u128 | function | ||
| 4196 | core::core_arch::s390x::vector | vec_addc_u128 | function | ||
| 4197 | core::core_arch::s390x::vector | vec_adde_u128 | function | ||
| 4198 | core::core_arch::s390x::vector | vec_addec_u128 | function | ||
| 4199 | core::core_arch::s390x::vector | vec_all_eq | function | ||
| 4200 | core::core_arch::s390x::vector | vec_all_ge | function | ||
| 4201 | core::core_arch::s390x::vector | vec_all_gt | function | ||
| 4202 | core::core_arch::s390x::vector | vec_all_le | function | ||
| 4203 | core::core_arch::s390x::vector | vec_all_lt | function | ||
| 4204 | core::core_arch::s390x::vector | vec_all_nan | function | ||
| 4205 | core::core_arch::s390x::vector | vec_all_ne | function | ||
| 4206 | core::core_arch::s390x::vector | vec_all_nge | function | ||
| 4207 | core::core_arch::s390x::vector | vec_all_ngt | function | ||
| 4208 | core::core_arch::s390x::vector | vec_all_nle | function | ||
| 4209 | core::core_arch::s390x::vector | vec_all_nlt | function | ||
| 4210 | core::core_arch::s390x::vector | vec_all_numeric | function | ||
| 4211 | core::core_arch::s390x::vector | vec_and | function | ||
| 4212 | core::core_arch::s390x::vector | vec_andc | function | ||
| 4213 | core::core_arch::s390x::vector | vec_any_eq | function | ||
| 4214 | core::core_arch::s390x::vector | vec_any_ge | function | ||
| 4215 | core::core_arch::s390x::vector | vec_any_gt | function | ||
| 4216 | core::core_arch::s390x::vector | vec_any_le | function | ||
| 4217 | core::core_arch::s390x::vector | vec_any_lt | function | ||
| 4218 | core::core_arch::s390x::vector | vec_any_nan | function | ||
| 4219 | core::core_arch::s390x::vector | vec_any_ne | function | ||
| 4220 | core::core_arch::s390x::vector | vec_any_nge | function | ||
| 4221 | core::core_arch::s390x::vector | vec_any_ngt | function | ||
| 4222 | core::core_arch::s390x::vector | vec_any_nle | function | ||
| 4223 | core::core_arch::s390x::vector | vec_any_nlt | function | ||
| 4224 | core::core_arch::s390x::vector | vec_any_numeric | function | ||
| 4225 | core::core_arch::s390x::vector | vec_avg | function | ||
| 4226 | core::core_arch::s390x::vector | vec_bperm_u128 | function | ||
| 4227 | core::core_arch::s390x::vector | vec_ceil | function | ||
| 4228 | core::core_arch::s390x::vector | vec_checksum | function | ||
| 4229 | core::core_arch::s390x::vector | vec_cmpeq | function | ||
| 4230 | core::core_arch::s390x::vector | vec_cmpeq_idx | function | ||
| 4231 | core::core_arch::s390x::vector | vec_cmpeq_idx_cc | function | ||
| 4232 | core::core_arch::s390x::vector | vec_cmpeq_or_0_idx | function | ||
| 4233 | core::core_arch::s390x::vector | vec_cmpeq_or_0_idx_cc | function | ||
| 4234 | core::core_arch::s390x::vector | vec_cmpge | function | ||
| 4235 | core::core_arch::s390x::vector | vec_cmpgt | function | ||
| 4236 | core::core_arch::s390x::vector | vec_cmple | function | ||
| 4237 | core::core_arch::s390x::vector | vec_cmplt | function | ||
| 4238 | core::core_arch::s390x::vector | vec_cmpne | function | ||
| 4239 | core::core_arch::s390x::vector | vec_cmpne_idx | function | ||
| 4240 | core::core_arch::s390x::vector | vec_cmpne_idx_cc | function | ||
| 4241 | core::core_arch::s390x::vector | vec_cmpne_or_0_idx | function | ||
| 4242 | core::core_arch::s390x::vector | vec_cmpne_or_0_idx_cc | function | ||
| 4243 | core::core_arch::s390x::vector | vec_cmpnrg | function | ||
| 4244 | core::core_arch::s390x::vector | vec_cmpnrg_cc | function | ||
| 4245 | core::core_arch::s390x::vector | vec_cmpnrg_idx | function | ||
| 4246 | core::core_arch::s390x::vector | vec_cmpnrg_idx_cc | function | ||
| 4247 | core::core_arch::s390x::vector | vec_cmpnrg_or_0_idx | function | ||
| 4248 | core::core_arch::s390x::vector | vec_cmpnrg_or_0_idx_cc | function | ||
| 4249 | core::core_arch::s390x::vector | vec_cmprg | function | ||
| 4250 | core::core_arch::s390x::vector | vec_cmprg_cc | function | ||
| 4251 | core::core_arch::s390x::vector | vec_cmprg_idx | function | ||
| 4252 | core::core_arch::s390x::vector | vec_cmprg_idx_cc | function | ||
| 4253 | core::core_arch::s390x::vector | vec_cmprg_or_0_idx | function | ||
| 4254 | core::core_arch::s390x::vector | vec_cmprg_or_0_idx_cc | function | ||
| 4255 | core::core_arch::s390x::vector | vec_cntlz | function | ||
| 4256 | core::core_arch::s390x::vector | vec_cnttz | function | ||
| 4257 | core::core_arch::s390x::vector | vec_convert_from_fp16 | function | ||
| 4258 | core::core_arch::s390x::vector | vec_convert_to_fp16 | function | ||
| 4259 | core::core_arch::s390x::vector | vec_cp_until_zero | function | ||
| 4260 | core::core_arch::s390x::vector | vec_cp_until_zero_cc | function | ||
| 4261 | core::core_arch::s390x::vector | vec_double | function | ||
| 4262 | core::core_arch::s390x::vector | vec_doublee | function | ||
| 4263 | core::core_arch::s390x::vector | vec_eqv | function | ||
| 4264 | core::core_arch::s390x::vector | vec_extend_s64 | function | ||
| 4265 | core::core_arch::s390x::vector | vec_extend_to_fp32_hi | function | ||
| 4266 | core::core_arch::s390x::vector | vec_extend_to_fp32_lo | function | ||
| 4267 | core::core_arch::s390x::vector | vec_extract | function | ||
| 4268 | core::core_arch::s390x::vector | vec_find_any_eq | function | ||
| 4269 | core::core_arch::s390x::vector | vec_find_any_eq_cc | function | ||
| 4270 | core::core_arch::s390x::vector | vec_find_any_eq_idx | function | ||
| 4271 | core::core_arch::s390x::vector | vec_find_any_eq_idx_cc | function | ||
| 4272 | core::core_arch::s390x::vector | vec_find_any_eq_or_0_idx | function | ||
| 4273 | core::core_arch::s390x::vector | vec_find_any_eq_or_0_idx_cc | function | ||
| 4274 | core::core_arch::s390x::vector | vec_find_any_ne | function | ||
| 4275 | core::core_arch::s390x::vector | vec_find_any_ne_cc | function | ||
| 4276 | core::core_arch::s390x::vector | vec_find_any_ne_idx | function | ||
| 4277 | core::core_arch::s390x::vector | vec_find_any_ne_idx_cc | function | ||
| 4278 | core::core_arch::s390x::vector | vec_find_any_ne_or_0_idx | function | ||
| 4279 | core::core_arch::s390x::vector | vec_find_any_ne_or_0_idx_cc | function | ||
| 4280 | core::core_arch::s390x::vector | vec_float | function | ||
| 4281 | core::core_arch::s390x::vector | vec_floate | function | ||
| 4282 | core::core_arch::s390x::vector | vec_floor | function | ||
| 4283 | core::core_arch::s390x::vector | vec_fp_test_data_class | function | ||
| 4284 | core::core_arch::s390x::vector | vec_gather_element | function | ||
| 4285 | core::core_arch::s390x::vector | vec_genmask | function | ||
| 4286 | core::core_arch::s390x::vector | vec_genmasks_16 | function | ||
| 4287 | core::core_arch::s390x::vector | vec_genmasks_32 | function | ||
| 4288 | core::core_arch::s390x::vector | vec_genmasks_64 | function | ||
| 4289 | core::core_arch::s390x::vector | vec_genmasks_8 | function | ||
| 4290 | core::core_arch::s390x::vector | vec_gfmsum | function | ||
| 4291 | core::core_arch::s390x::vector | vec_gfmsum_128 | function | ||
| 4292 | core::core_arch::s390x::vector | vec_gfmsum_accum | function | ||
| 4293 | core::core_arch::s390x::vector | vec_gfmsum_accum_128 | function | ||
| 4294 | core::core_arch::s390x::vector | vec_insert | function | ||
| 4295 | core::core_arch::s390x::vector | vec_insert_and_zero | function | ||
| 4296 | core::core_arch::s390x::vector | vec_load_bndry | function | ||
| 4297 | core::core_arch::s390x::vector | vec_load_len | function | ||
| 4298 | core::core_arch::s390x::vector | vec_load_len_r | function | ||
| 4299 | core::core_arch::s390x::vector | vec_load_pair | function | ||
| 4300 | core::core_arch::s390x::vector | vec_madd | function | ||
| 4301 | core::core_arch::s390x::vector | vec_max | function | ||
| 4302 | core::core_arch::s390x::vector | vec_meadd | function | ||
| 4303 | core::core_arch::s390x::vector | vec_mergeh | function | ||
| 4304 | core::core_arch::s390x::vector | vec_mergel | function | ||
| 4305 | core::core_arch::s390x::vector | vec_mhadd | function | ||
| 4306 | core::core_arch::s390x::vector | vec_min | function | ||
| 4307 | core::core_arch::s390x::vector | vec_mladd | function | ||
| 4308 | core::core_arch::s390x::vector | vec_moadd | function | ||
| 4309 | core::core_arch::s390x::vector | vec_msub | function | ||
| 4310 | core::core_arch::s390x::vector | vec_msum_u128 | function | ||
| 4311 | core::core_arch::s390x::vector | vec_mul | function | ||
| 4312 | core::core_arch::s390x::vector | vec_mule | function | ||
| 4313 | core::core_arch::s390x::vector | vec_mulh | function | ||
| 4314 | core::core_arch::s390x::vector | vec_mulo | function | ||
| 4315 | core::core_arch::s390x::vector | vec_nabs | function | ||
| 4316 | core::core_arch::s390x::vector | vec_nand | function | ||
| 4317 | core::core_arch::s390x::vector | vec_neg | function | ||
| 4318 | core::core_arch::s390x::vector | vec_nmadd | function | ||
| 4319 | core::core_arch::s390x::vector | vec_nmsub | function | ||
| 4320 | core::core_arch::s390x::vector | vec_nor | function | ||
| 4321 | core::core_arch::s390x::vector | vec_or | function | ||
| 4322 | core::core_arch::s390x::vector | vec_orc | function | ||
| 4323 | core::core_arch::s390x::vector | vec_pack | function | ||
| 4324 | core::core_arch::s390x::vector | vec_packs | function | ||
| 4325 | core::core_arch::s390x::vector | vec_packs_cc | function | ||
| 4326 | core::core_arch::s390x::vector | vec_packsu | function | ||
| 4327 | core::core_arch::s390x::vector | vec_packsu_cc | function | ||
| 4328 | core::core_arch::s390x::vector | vec_perm | function | ||
| 4329 | core::core_arch::s390x::vector | vec_popcnt | function | ||
| 4330 | core::core_arch::s390x::vector | vec_promote | function | ||
| 4331 | core::core_arch::s390x::vector | vec_revb | function | ||
| 4332 | core::core_arch::s390x::vector | vec_reve | function | ||
| 4333 | core::core_arch::s390x::vector | vec_rint | function | ||
| 4334 | core::core_arch::s390x::vector | vec_rl | function | ||
| 4335 | core::core_arch::s390x::vector | vec_rli | function | ||
| 4336 | core::core_arch::s390x::vector | vec_round | function | ||
| 4337 | core::core_arch::s390x::vector | vec_round_from_fp32 | function | ||
| 4338 | core::core_arch::s390x::vector | vec_roundc | function | ||
| 4339 | core::core_arch::s390x::vector | vec_roundm | function | ||
| 4340 | core::core_arch::s390x::vector | vec_roundp | function | ||
| 4341 | core::core_arch::s390x::vector | vec_roundz | function | ||
| 4342 | core::core_arch::s390x::vector | vec_search_string_cc | function | ||
| 4343 | core::core_arch::s390x::vector | vec_search_string_until_zero_cc | function | ||
| 4344 | core::core_arch::s390x::vector | vec_sel | function | ||
| 4345 | core::core_arch::s390x::vector | vec_signed | function | ||
| 4346 | core::core_arch::s390x::vector | vec_sl | function | ||
| 4347 | core::core_arch::s390x::vector | vec_slb | function | ||
| 4348 | core::core_arch::s390x::vector | vec_sld | function | ||
| 4349 | core::core_arch::s390x::vector | vec_sldb | function | ||
| 4350 | core::core_arch::s390x::vector | vec_sldw | function | ||
| 4351 | core::core_arch::s390x::vector | vec_sll | function | ||
| 4352 | core::core_arch::s390x::vector | vec_splat | function | ||
| 4353 | core::core_arch::s390x::vector | vec_splat_s16 | function | ||
| 4354 | core::core_arch::s390x::vector | vec_splat_s32 | function | ||
| 4355 | core::core_arch::s390x::vector | vec_splat_s64 | function | ||
| 4356 | core::core_arch::s390x::vector | vec_splat_s8 | function | ||
| 4357 | core::core_arch::s390x::vector | vec_splat_u16 | function | ||
| 4358 | core::core_arch::s390x::vector | vec_splat_u32 | function | ||
| 4359 | core::core_arch::s390x::vector | vec_splat_u64 | function | ||
| 4360 | core::core_arch::s390x::vector | vec_splat_u8 | function | ||
| 4361 | core::core_arch::s390x::vector | vec_splats | function | ||
| 4362 | core::core_arch::s390x::vector | vec_sqrt | function | ||
| 4363 | core::core_arch::s390x::vector | vec_sr | function | ||
| 4364 | core::core_arch::s390x::vector | vec_sra | function | ||
| 4365 | core::core_arch::s390x::vector | vec_srab | function | ||
| 4366 | core::core_arch::s390x::vector | vec_sral | function | ||
| 4367 | core::core_arch::s390x::vector | vec_srb | function | ||
| 4368 | core::core_arch::s390x::vector | vec_srdb | function | ||
| 4369 | core::core_arch::s390x::vector | vec_srl | function | ||
| 4370 | core::core_arch::s390x::vector | vec_store_len | function | ||
| 4371 | core::core_arch::s390x::vector | vec_store_len_r | function | ||
| 4372 | core::core_arch::s390x::vector | vec_sub | function | ||
| 4373 | core::core_arch::s390x::vector | vec_sub_u128 | function | ||
| 4374 | core::core_arch::s390x::vector | vec_subc | function | ||
| 4375 | core::core_arch::s390x::vector | vec_subc_u128 | function | ||
| 4376 | core::core_arch::s390x::vector | vec_sube_u128 | function | ||
| 4377 | core::core_arch::s390x::vector | vec_subec_u128 | function | ||
| 4378 | core::core_arch::s390x::vector | vec_sum2 | function | ||
| 4379 | core::core_arch::s390x::vector | vec_sum4 | function | ||
| 4380 | core::core_arch::s390x::vector | vec_sum_u128 | function | ||
| 4381 | core::core_arch::s390x::vector | vec_test_mask | function | ||
| 4382 | core::core_arch::s390x::vector | vec_trunc | function | ||
| 4383 | core::core_arch::s390x::vector | vec_unpackh | function | ||
| 4384 | core::core_arch::s390x::vector | vec_unpackl | function | ||
| 4385 | core::core_arch::s390x::vector | vec_unsigned | function | ||
| 4386 | core::core_arch::s390x::vector | vec_xl | function | ||
| 4387 | core::core_arch::s390x::vector | vec_xor | function | ||
| 4388 | core::core_arch::s390x::vector | vec_xst | function | ||
| 4389 | core::core_arch::wasm32::atomic | memory_atomic_notify | function | ||
| 4390 | core::core_arch::wasm32::atomic | memory_atomic_wait32 | function | ||
| 4391 | core::core_arch::wasm32::atomic | memory_atomic_wait64 | function | ||
| 4392 | core::core_arch::wasm32::simd128 | i16x8_load_extend_i8x8 | function | ||
| 4393 | core::core_arch::wasm32::simd128 | i16x8_load_extend_u8x8 | function | ||
| 4394 | core::core_arch::wasm32::simd128 | i32x4_load_extend_i16x4 | function | ||
| 4395 | core::core_arch::wasm32::simd128 | i32x4_load_extend_u16x4 | function | ||
| 4396 | core::core_arch::wasm32::simd128 | i64x2_load_extend_i32x2 | function | ||
| 4397 | core::core_arch::wasm32::simd128 | i64x2_load_extend_u32x2 | function | ||
| 4398 | core::core_arch::wasm32::simd128 | v128_load | function | ||
| 4399 | core::core_arch::wasm32::simd128 | v128_load16_lane | function | ||
| 4400 | core::core_arch::wasm32::simd128 | v128_load16_splat | function | ||
| 4401 | core::core_arch::wasm32::simd128 | v128_load32_lane | function | ||
| 4402 | core::core_arch::wasm32::simd128 | v128_load32_splat | function | ||
| 4403 | core::core_arch::wasm32::simd128 | v128_load32_zero | function | ||
| 4404 | core::core_arch::wasm32::simd128 | v128_load64_lane | function | ||
| 4405 | core::core_arch::wasm32::simd128 | v128_load64_splat | function | ||
| 4406 | core::core_arch::wasm32::simd128 | v128_load64_zero | function | ||
| 4407 | core::core_arch::wasm32::simd128 | v128_load8_lane | function | ||
| 4408 | core::core_arch::wasm32::simd128 | v128_load8_splat | function | ||
| 4409 | core::core_arch::wasm32::simd128 | v128_store | function | ||
| 4410 | core::core_arch::wasm32::simd128 | v128_store16_lane | function | ||
| 4411 | core::core_arch::wasm32::simd128 | v128_store32_lane | function | ||
| 4412 | core::core_arch::wasm32::simd128 | v128_store64_lane | function | ||
| 4413 | core::core_arch::wasm32::simd128 | v128_store8_lane | function | ||
| 4414 | core::core_arch::x86::avx | _mm256_lddqu_si256 | function | ||
| 4415 | core::core_arch::x86::avx | _mm256_load_pd | function | ||
| 4416 | core::core_arch::x86::avx | _mm256_load_ps | function | ||
| 4417 | core::core_arch::x86::avx | _mm256_load_si256 | function | ||
| 4418 | core::core_arch::x86::avx | _mm256_loadu2_m128 | function | ||
| 4419 | core::core_arch::x86::avx | _mm256_loadu2_m128d | function | ||
| 4420 | core::core_arch::x86::avx | _mm256_loadu2_m128i | function | ||
| 4421 | core::core_arch::x86::avx | _mm256_loadu_pd | function | ||
| 4422 | core::core_arch::x86::avx | _mm256_loadu_ps | function | ||
| 4423 | core::core_arch::x86::avx | _mm256_loadu_si256 | function | ||
| 4424 | core::core_arch::x86::avx | _mm256_maskload_pd | function | ||
| 4425 | core::core_arch::x86::avx | _mm256_maskload_ps | function | ||
| 4426 | core::core_arch::x86::avx | _mm256_maskstore_pd | function | ||
| 4427 | core::core_arch::x86::avx | _mm256_maskstore_ps | function | ||
| 4428 | core::core_arch::x86::avx | _mm256_store_pd | function | ||
| 4429 | core::core_arch::x86::avx | _mm256_store_ps | function | ||
| 4430 | core::core_arch::x86::avx | _mm256_store_si256 | function | ||
| 4431 | core::core_arch::x86::avx | _mm256_storeu2_m128 | function | ||
| 4432 | core::core_arch::x86::avx | _mm256_storeu2_m128d | function | ||
| 4433 | core::core_arch::x86::avx | _mm256_storeu2_m128i | function | ||
| 4434 | core::core_arch::x86::avx | _mm256_storeu_pd | function | ||
| 4435 | core::core_arch::x86::avx | _mm256_storeu_ps | function | ||
| 4436 | core::core_arch::x86::avx | _mm256_storeu_si256 | function | ||
| 4437 | core::core_arch::x86::avx | _mm256_stream_pd | function | After using this intrinsic, but before any other access to the memory that this intrinsic mutates, a call to [`_mm_sfence`] must be performed by the thread that used the intrinsic. In particular, functions that call this intrinsic should generally call `_mm_sfence` before they return. See [`_mm_sfence`] for details. | |
| 4438 | core::core_arch::x86::avx | _mm256_stream_ps | function | After using this intrinsic, but before any other access to the memory that this intrinsic mutates, a call to [`_mm_sfence`] must be performed by the thread that used the intrinsic. In particular, functions that call this intrinsic should generally call `_mm_sfence` before they return. See [`_mm_sfence`] for details. | |
| 4439 | core::core_arch::x86::avx | _mm256_stream_si256 | function | After using this intrinsic, but before any other access to the memory that this intrinsic mutates, a call to [`_mm_sfence`] must be performed by the thread that used the intrinsic. In particular, functions that call this intrinsic should generally call `_mm_sfence` before they return. See [`_mm_sfence`] for details. | |
| 4440 | core::core_arch::x86::avx | _mm_maskload_pd | function | ||
| 4441 | core::core_arch::x86::avx | _mm_maskload_ps | function | ||
| 4442 | core::core_arch::x86::avx | _mm_maskstore_pd | function | ||
| 4443 | core::core_arch::x86::avx | _mm_maskstore_ps | function | ||
| 4444 | core::core_arch::x86::avx2 | _mm256_i32gather_epi32 | function | ||
| 4445 | core::core_arch::x86::avx2 | _mm256_i32gather_epi64 | function | ||
| 4446 | core::core_arch::x86::avx2 | _mm256_i32gather_pd | function | ||
| 4447 | core::core_arch::x86::avx2 | _mm256_i32gather_ps | function | ||
| 4448 | core::core_arch::x86::avx2 | _mm256_i64gather_epi32 | function | ||
| 4449 | core::core_arch::x86::avx2 | _mm256_i64gather_epi64 | function | ||
| 4450 | core::core_arch::x86::avx2 | _mm256_i64gather_pd | function | ||
| 4451 | core::core_arch::x86::avx2 | _mm256_i64gather_ps | function | ||
| 4452 | core::core_arch::x86::avx2 | _mm256_mask_i32gather_epi32 | function | ||
| 4453 | core::core_arch::x86::avx2 | _mm256_mask_i32gather_epi64 | function | ||
| 4454 | core::core_arch::x86::avx2 | _mm256_mask_i32gather_pd | function | ||
| 4455 | core::core_arch::x86::avx2 | _mm256_mask_i32gather_ps | function | ||
| 4456 | core::core_arch::x86::avx2 | _mm256_mask_i64gather_epi32 | function | ||
| 4457 | core::core_arch::x86::avx2 | _mm256_mask_i64gather_epi64 | function | ||
| 4458 | core::core_arch::x86::avx2 | _mm256_mask_i64gather_pd | function | ||
| 4459 | core::core_arch::x86::avx2 | _mm256_mask_i64gather_ps | function | ||
| 4460 | core::core_arch::x86::avx2 | _mm256_maskload_epi32 | function | ||
| 4461 | core::core_arch::x86::avx2 | _mm256_maskload_epi64 | function | ||
| 4462 | core::core_arch::x86::avx2 | _mm256_maskstore_epi32 | function | ||
| 4463 | core::core_arch::x86::avx2 | _mm256_maskstore_epi64 | function | ||
| 4464 | core::core_arch::x86::avx2 | _mm256_stream_load_si256 | function | ||
| 4465 | core::core_arch::x86::avx2 | _mm_i32gather_epi32 | function | ||
| 4466 | core::core_arch::x86::avx2 | _mm_i32gather_epi64 | function | ||
| 4467 | core::core_arch::x86::avx2 | _mm_i32gather_pd | function | ||
| 4468 | core::core_arch::x86::avx2 | _mm_i32gather_ps | function | ||
| 4469 | core::core_arch::x86::avx2 | _mm_i64gather_epi32 | function | ||
| 4470 | core::core_arch::x86::avx2 | _mm_i64gather_epi64 | function | ||
| 4471 | core::core_arch::x86::avx2 | _mm_i64gather_pd | function | ||
| 4472 | core::core_arch::x86::avx2 | _mm_i64gather_ps | function | ||
| 4473 | core::core_arch::x86::avx2 | _mm_mask_i32gather_epi32 | function | ||
| 4474 | core::core_arch::x86::avx2 | _mm_mask_i32gather_epi64 | function | ||
| 4475 | core::core_arch::x86::avx2 | _mm_mask_i32gather_pd | function | ||
| 4476 | core::core_arch::x86::avx2 | _mm_mask_i32gather_ps | function | ||
| 4477 | core::core_arch::x86::avx2 | _mm_mask_i64gather_epi32 | function | ||
| 4478 | core::core_arch::x86::avx2 | _mm_mask_i64gather_epi64 | function | ||
| 4479 | core::core_arch::x86::avx2 | _mm_mask_i64gather_pd | function | ||
| 4480 | core::core_arch::x86::avx2 | _mm_mask_i64gather_ps | function | ||
| 4481 | core::core_arch::x86::avx2 | _mm_maskload_epi32 | function | ||
| 4482 | core::core_arch::x86::avx2 | _mm_maskload_epi64 | function | ||
| 4483 | core::core_arch::x86::avx2 | _mm_maskstore_epi32 | function | ||
| 4484 | core::core_arch::x86::avx2 | _mm_maskstore_epi64 | function | ||
| 4485 | core::core_arch::x86::avx512bw | _kortest_mask32_u8 | function | ||
| 4486 | core::core_arch::x86::avx512bw | _kortest_mask64_u8 | function | ||
| 4487 | core::core_arch::x86::avx512bw | _ktest_mask32_u8 | function | ||
| 4488 | core::core_arch::x86::avx512bw | _ktest_mask64_u8 | function | ||
| 4489 | core::core_arch::x86::avx512bw | _load_mask32 | function | ||
| 4490 | core::core_arch::x86::avx512bw | _load_mask64 | function | ||
| 4491 | core::core_arch::x86::avx512bw | _mm256_loadu_epi16 | function | ||
| 4492 | core::core_arch::x86::avx512bw | _mm256_loadu_epi8 | function | ||
| 4493 | core::core_arch::x86::avx512bw | _mm256_mask_cvtepi16_storeu_epi8 | function | ||
| 4494 | core::core_arch::x86::avx512bw | _mm256_mask_cvtsepi16_storeu_epi8 | function | ||
| 4495 | core::core_arch::x86::avx512bw | _mm256_mask_cvtusepi16_storeu_epi8 | function | ||
| 4496 | core::core_arch::x86::avx512bw | _mm256_mask_loadu_epi16 | function | ||
| 4497 | core::core_arch::x86::avx512bw | _mm256_mask_loadu_epi8 | function | ||
| 4498 | core::core_arch::x86::avx512bw | _mm256_mask_storeu_epi16 | function | ||
| 4499 | core::core_arch::x86::avx512bw | _mm256_mask_storeu_epi8 | function | ||
| 4500 | core::core_arch::x86::avx512bw | _mm256_maskz_loadu_epi16 | function | ||
| 4501 | core::core_arch::x86::avx512bw | _mm256_maskz_loadu_epi8 | function | ||
| 4502 | core::core_arch::x86::avx512bw | _mm256_storeu_epi16 | function | ||
| 4503 | core::core_arch::x86::avx512bw | _mm256_storeu_epi8 | function | ||
| 4504 | core::core_arch::x86::avx512bw | _mm512_loadu_epi16 | function | ||
| 4505 | core::core_arch::x86::avx512bw | _mm512_loadu_epi8 | function | ||
| 4506 | core::core_arch::x86::avx512bw | _mm512_mask_cvtepi16_storeu_epi8 | function | ||
| 4507 | core::core_arch::x86::avx512bw | _mm512_mask_cvtsepi16_storeu_epi8 | function | ||
| 4508 | core::core_arch::x86::avx512bw | _mm512_mask_cvtusepi16_storeu_epi8 | function | ||
| 4509 | core::core_arch::x86::avx512bw | _mm512_mask_loadu_epi16 | function | ||
| 4510 | core::core_arch::x86::avx512bw | _mm512_mask_loadu_epi8 | function | ||
| 4511 | core::core_arch::x86::avx512bw | _mm512_mask_storeu_epi16 | function | ||
| 4512 | core::core_arch::x86::avx512bw | _mm512_mask_storeu_epi8 | function | ||
| 4513 | core::core_arch::x86::avx512bw | _mm512_maskz_loadu_epi16 | function | ||
| 4514 | core::core_arch::x86::avx512bw | _mm512_maskz_loadu_epi8 | function | ||
| 4515 | core::core_arch::x86::avx512bw | _mm512_storeu_epi16 | function | ||
| 4516 | core::core_arch::x86::avx512bw | _mm512_storeu_epi8 | function | ||
| 4517 | core::core_arch::x86::avx512bw | _mm_loadu_epi16 | function | ||
| 4518 | core::core_arch::x86::avx512bw | _mm_loadu_epi8 | function | ||
| 4519 | core::core_arch::x86::avx512bw | _mm_mask_cvtepi16_storeu_epi8 | function | ||
| 4520 | core::core_arch::x86::avx512bw | _mm_mask_cvtsepi16_storeu_epi8 | function | ||
| 4521 | core::core_arch::x86::avx512bw | _mm_mask_cvtusepi16_storeu_epi8 | function | ||
| 4522 | core::core_arch::x86::avx512bw | _mm_mask_loadu_epi16 | function | ||
| 4523 | core::core_arch::x86::avx512bw | _mm_mask_loadu_epi8 | function | ||
| 4524 | core::core_arch::x86::avx512bw | _mm_mask_storeu_epi16 | function | ||
| 4525 | core::core_arch::x86::avx512bw | _mm_mask_storeu_epi8 | function | ||
| 4526 | core::core_arch::x86::avx512bw | _mm_maskz_loadu_epi16 | function | ||
| 4527 | core::core_arch::x86::avx512bw | _mm_maskz_loadu_epi8 | function | ||
| 4528 | core::core_arch::x86::avx512bw | _mm_storeu_epi16 | function | ||
| 4529 | core::core_arch::x86::avx512bw | _mm_storeu_epi8 | function | ||
| 4530 | core::core_arch::x86::avx512bw | _store_mask32 | function | ||
| 4531 | core::core_arch::x86::avx512bw | _store_mask64 | function | ||
| 4532 | core::core_arch::x86::avx512dq | _kortest_mask8_u8 | function | ||
| 4533 | core::core_arch::x86::avx512dq | _ktest_mask16_u8 | function | ||
| 4534 | core::core_arch::x86::avx512dq | _ktest_mask8_u8 | function | ||
| 4535 | core::core_arch::x86::avx512dq | _load_mask8 | function | ||
| 4536 | core::core_arch::x86::avx512dq | _store_mask8 | function | ||
| 4537 | core::core_arch::x86::avx512f | _kortest_mask16_u8 | function | ||
| 4538 | core::core_arch::x86::avx512f | _load_mask16 | function | ||
| 4539 | core::core_arch::x86::avx512f | _mm256_i32scatter_epi32 | function | ||
| 4540 | core::core_arch::x86::avx512f | _mm256_i32scatter_epi64 | function | ||
| 4541 | core::core_arch::x86::avx512f | _mm256_i32scatter_pd | function | ||
| 4542 | core::core_arch::x86::avx512f | _mm256_i32scatter_ps | function | ||
| 4543 | core::core_arch::x86::avx512f | _mm256_i64scatter_epi32 | function | ||
| 4544 | core::core_arch::x86::avx512f | _mm256_i64scatter_epi64 | function | ||
| 4545 | core::core_arch::x86::avx512f | _mm256_i64scatter_pd | function | ||
| 4546 | core::core_arch::x86::avx512f | _mm256_i64scatter_ps | function | ||
| 4547 | core::core_arch::x86::avx512f | _mm256_load_epi32 | function | ||
| 4548 | core::core_arch::x86::avx512f | _mm256_load_epi64 | function | ||
| 4549 | core::core_arch::x86::avx512f | _mm256_loadu_epi32 | function | ||
| 4550 | core::core_arch::x86::avx512f | _mm256_loadu_epi64 | function | ||
| 4551 | core::core_arch::x86::avx512f | _mm256_mask_compressstoreu_epi32 | function | ||
| 4552 | core::core_arch::x86::avx512f | _mm256_mask_compressstoreu_epi64 | function | ||
| 4553 | core::core_arch::x86::avx512f | _mm256_mask_compressstoreu_pd | function | ||
| 4554 | core::core_arch::x86::avx512f | _mm256_mask_compressstoreu_ps | function | ||
| 4555 | core::core_arch::x86::avx512f | _mm256_mask_cvtepi32_storeu_epi16 | function | ||
| 4556 | core::core_arch::x86::avx512f | _mm256_mask_cvtepi32_storeu_epi8 | function | ||
| 4557 | core::core_arch::x86::avx512f | _mm256_mask_cvtepi64_storeu_epi16 | function | ||
| 4558 | core::core_arch::x86::avx512f | _mm256_mask_cvtepi64_storeu_epi32 | function | ||
| 4559 | core::core_arch::x86::avx512f | _mm256_mask_cvtepi64_storeu_epi8 | function | ||
| 4560 | core::core_arch::x86::avx512f | _mm256_mask_cvtsepi32_storeu_epi16 | function | ||
| 4561 | core::core_arch::x86::avx512f | _mm256_mask_cvtsepi32_storeu_epi8 | function | ||
| 4562 | core::core_arch::x86::avx512f | _mm256_mask_cvtsepi64_storeu_epi16 | function | ||
| 4563 | core::core_arch::x86::avx512f | _mm256_mask_cvtsepi64_storeu_epi32 | function | ||
| 4564 | core::core_arch::x86::avx512f | _mm256_mask_cvtsepi64_storeu_epi8 | function | ||
| 4565 | core::core_arch::x86::avx512f | _mm256_mask_cvtusepi32_storeu_epi16 | function | ||
| 4566 | core::core_arch::x86::avx512f | _mm256_mask_cvtusepi32_storeu_epi8 | function | ||
| 4567 | core::core_arch::x86::avx512f | _mm256_mask_cvtusepi64_storeu_epi16 | function | ||
| 4568 | core::core_arch::x86::avx512f | _mm256_mask_cvtusepi64_storeu_epi32 | function | ||
| 4569 | core::core_arch::x86::avx512f | _mm256_mask_cvtusepi64_storeu_epi8 | function | ||
| 4570 | core::core_arch::x86::avx512f | _mm256_mask_expandloadu_epi32 | function | ||
| 4571 | core::core_arch::x86::avx512f | _mm256_mask_expandloadu_epi64 | function | ||
| 4572 | core::core_arch::x86::avx512f | _mm256_mask_expandloadu_pd | function | ||
| 4573 | core::core_arch::x86::avx512f | _mm256_mask_expandloadu_ps | function | ||
| 4574 | core::core_arch::x86::avx512f | _mm256_mask_i32scatter_epi32 | function | ||
| 4575 | core::core_arch::x86::avx512f | _mm256_mask_i32scatter_epi64 | function | ||
| 4576 | core::core_arch::x86::avx512f | _mm256_mask_i32scatter_pd | function | ||
| 4577 | core::core_arch::x86::avx512f | _mm256_mask_i32scatter_ps | function | ||
| 4578 | core::core_arch::x86::avx512f | _mm256_mask_i64scatter_epi32 | function | ||
| 4579 | core::core_arch::x86::avx512f | _mm256_mask_i64scatter_epi64 | function | ||
| 4580 | core::core_arch::x86::avx512f | _mm256_mask_i64scatter_pd | function | ||
| 4581 | core::core_arch::x86::avx512f | _mm256_mask_i64scatter_ps | function | ||
| 4582 | core::core_arch::x86::avx512f | _mm256_mask_load_epi32 | function | ||
| 4583 | core::core_arch::x86::avx512f | _mm256_mask_load_epi64 | function | ||
| 4584 | core::core_arch::x86::avx512f | _mm256_mask_load_pd | function | ||
| 4585 | core::core_arch::x86::avx512f | _mm256_mask_load_ps | function | ||
| 4586 | core::core_arch::x86::avx512f | _mm256_mask_loadu_epi32 | function | ||
| 4587 | core::core_arch::x86::avx512f | _mm256_mask_loadu_epi64 | function | ||
| 4588 | core::core_arch::x86::avx512f | _mm256_mask_loadu_pd | function | ||
| 4589 | core::core_arch::x86::avx512f | _mm256_mask_loadu_ps | function | ||
| 4590 | core::core_arch::x86::avx512f | _mm256_mask_store_epi32 | function | ||
| 4591 | core::core_arch::x86::avx512f | _mm256_mask_store_epi64 | function | ||
| 4592 | core::core_arch::x86::avx512f | _mm256_mask_store_pd | function | ||
| 4593 | core::core_arch::x86::avx512f | _mm256_mask_store_ps | function | ||
| 4594 | core::core_arch::x86::avx512f | _mm256_mask_storeu_epi32 | function | ||
| 4595 | core::core_arch::x86::avx512f | _mm256_mask_storeu_epi64 | function | ||
| 4596 | core::core_arch::x86::avx512f | _mm256_mask_storeu_pd | function | ||
| 4597 | core::core_arch::x86::avx512f | _mm256_mask_storeu_ps | function | ||
| 4598 | core::core_arch::x86::avx512f | _mm256_maskz_expandloadu_epi32 | function | ||
| 4599 | core::core_arch::x86::avx512f | _mm256_maskz_expandloadu_epi64 | function | ||
| 4600 | core::core_arch::x86::avx512f | _mm256_maskz_expandloadu_pd | function | ||
| 4601 | core::core_arch::x86::avx512f | _mm256_maskz_expandloadu_ps | function | ||
| 4602 | core::core_arch::x86::avx512f | _mm256_maskz_load_epi32 | function | ||
| 4603 | core::core_arch::x86::avx512f | _mm256_maskz_load_epi64 | function | ||
| 4604 | core::core_arch::x86::avx512f | _mm256_maskz_load_pd | function | ||
| 4605 | core::core_arch::x86::avx512f | _mm256_maskz_load_ps | function | ||
| 4606 | core::core_arch::x86::avx512f | _mm256_maskz_loadu_epi32 | function | ||
| 4607 | core::core_arch::x86::avx512f | _mm256_maskz_loadu_epi64 | function | ||
| 4608 | core::core_arch::x86::avx512f | _mm256_maskz_loadu_pd | function | ||
| 4609 | core::core_arch::x86::avx512f | _mm256_maskz_loadu_ps | function | ||
| 4610 | core::core_arch::x86::avx512f | _mm256_mmask_i32gather_epi32 | function | ||
| 4611 | core::core_arch::x86::avx512f | _mm256_mmask_i32gather_epi64 | function | ||
| 4612 | core::core_arch::x86::avx512f | _mm256_mmask_i32gather_pd | function | ||
| 4613 | core::core_arch::x86::avx512f | _mm256_mmask_i32gather_ps | function | ||
| 4614 | core::core_arch::x86::avx512f | _mm256_mmask_i64gather_epi32 | function | ||
| 4615 | core::core_arch::x86::avx512f | _mm256_mmask_i64gather_epi64 | function | ||
| 4616 | core::core_arch::x86::avx512f | _mm256_mmask_i64gather_pd | function | ||
| 4617 | core::core_arch::x86::avx512f | _mm256_mmask_i64gather_ps | function | ||
| 4618 | core::core_arch::x86::avx512f | _mm256_store_epi32 | function | ||
| 4619 | core::core_arch::x86::avx512f | _mm256_store_epi64 | function | ||
| 4620 | core::core_arch::x86::avx512f | _mm256_storeu_epi32 | function | ||
| 4621 | core::core_arch::x86::avx512f | _mm256_storeu_epi64 | function | ||
| 4622 | core::core_arch::x86::avx512f | _mm512_i32gather_epi32 | function | ||
| 4623 | core::core_arch::x86::avx512f | _mm512_i32gather_epi64 | function | ||
| 4624 | core::core_arch::x86::avx512f | _mm512_i32gather_pd | function | ||
| 4625 | core::core_arch::x86::avx512f | _mm512_i32gather_ps | function | ||
| 4626 | core::core_arch::x86::avx512f | _mm512_i32logather_epi64 | function | ||
| 4627 | core::core_arch::x86::avx512f | _mm512_i32logather_pd | function | ||
| 4628 | core::core_arch::x86::avx512f | _mm512_i32loscatter_epi64 | function | ||
| 4629 | core::core_arch::x86::avx512f | _mm512_i32loscatter_pd | function | ||
| 4630 | core::core_arch::x86::avx512f | _mm512_i32scatter_epi32 | function | ||
| 4631 | core::core_arch::x86::avx512f | _mm512_i32scatter_epi64 | function | ||
| 4632 | core::core_arch::x86::avx512f | _mm512_i32scatter_pd | function | ||
| 4633 | core::core_arch::x86::avx512f | _mm512_i32scatter_ps | function | ||
| 4634 | core::core_arch::x86::avx512f | _mm512_i64gather_epi32 | function | ||
| 4635 | core::core_arch::x86::avx512f | _mm512_i64gather_epi64 | function | ||
| 4636 | core::core_arch::x86::avx512f | _mm512_i64gather_pd | function | ||
| 4637 | core::core_arch::x86::avx512f | _mm512_i64gather_ps | function | ||
| 4638 | core::core_arch::x86::avx512f | _mm512_i64scatter_epi32 | function | ||
| 4639 | core::core_arch::x86::avx512f | _mm512_i64scatter_epi64 | function | ||
| 4640 | core::core_arch::x86::avx512f | _mm512_i64scatter_pd | function | ||
| 4641 | core::core_arch::x86::avx512f | _mm512_i64scatter_ps | function | ||
| 4642 | core::core_arch::x86::avx512f | _mm512_load_epi32 | function | ||
| 4643 | core::core_arch::x86::avx512f | _mm512_load_epi64 | function | ||
| 4644 | core::core_arch::x86::avx512f | _mm512_load_pd | function | ||
| 4645 | core::core_arch::x86::avx512f | _mm512_load_ps | function | ||
| 4646 | core::core_arch::x86::avx512f | _mm512_load_si512 | function | ||
| 4647 | core::core_arch::x86::avx512f | _mm512_loadu_epi32 | function | ||
| 4648 | core::core_arch::x86::avx512f | _mm512_loadu_epi64 | function | ||
| 4649 | core::core_arch::x86::avx512f | _mm512_loadu_pd | function | ||
| 4650 | core::core_arch::x86::avx512f | _mm512_loadu_ps | function | ||
| 4651 | core::core_arch::x86::avx512f | _mm512_loadu_si512 | function | ||
| 4652 | core::core_arch::x86::avx512f | _mm512_mask_compressstoreu_epi32 | function | ||
| 4653 | core::core_arch::x86::avx512f | _mm512_mask_compressstoreu_epi64 | function | ||
| 4654 | core::core_arch::x86::avx512f | _mm512_mask_compressstoreu_pd | function | ||
| 4655 | core::core_arch::x86::avx512f | _mm512_mask_compressstoreu_ps | function | ||
| 4656 | core::core_arch::x86::avx512f | _mm512_mask_cvtepi32_storeu_epi16 | function | ||
| 4657 | core::core_arch::x86::avx512f | _mm512_mask_cvtepi32_storeu_epi8 | function | ||
| 4658 | core::core_arch::x86::avx512f | _mm512_mask_cvtepi64_storeu_epi16 | function | ||
| 4659 | core::core_arch::x86::avx512f | _mm512_mask_cvtepi64_storeu_epi32 | function | ||
| 4660 | core::core_arch::x86::avx512f | _mm512_mask_cvtepi64_storeu_epi8 | function | ||
| 4661 | core::core_arch::x86::avx512f | _mm512_mask_cvtsepi32_storeu_epi16 | function | ||
| 4662 | core::core_arch::x86::avx512f | _mm512_mask_cvtsepi32_storeu_epi8 | function | ||
| 4663 | core::core_arch::x86::avx512f | _mm512_mask_cvtsepi64_storeu_epi16 | function | ||
| 4664 | core::core_arch::x86::avx512f | _mm512_mask_cvtsepi64_storeu_epi32 | function | ||
| 4665 | core::core_arch::x86::avx512f | _mm512_mask_cvtsepi64_storeu_epi8 | function | ||
| 4666 | core::core_arch::x86::avx512f | _mm512_mask_cvtusepi32_storeu_epi16 | function | ||
| 4667 | core::core_arch::x86::avx512f | _mm512_mask_cvtusepi32_storeu_epi8 | function | ||
| 4668 | core::core_arch::x86::avx512f | _mm512_mask_cvtusepi64_storeu_epi16 | function | ||
| 4669 | core::core_arch::x86::avx512f | _mm512_mask_cvtusepi64_storeu_epi32 | function | ||
| 4670 | core::core_arch::x86::avx512f | _mm512_mask_cvtusepi64_storeu_epi8 | function | ||
| 4671 | core::core_arch::x86::avx512f | _mm512_mask_expandloadu_epi32 | function | ||
| 4672 | core::core_arch::x86::avx512f | _mm512_mask_expandloadu_epi64 | function | ||
| 4673 | core::core_arch::x86::avx512f | _mm512_mask_expandloadu_pd | function | ||
| 4674 | core::core_arch::x86::avx512f | _mm512_mask_expandloadu_ps | function | ||
| 4675 | core::core_arch::x86::avx512f | _mm512_mask_i32gather_epi32 | function | ||
| 4676 | core::core_arch::x86::avx512f | _mm512_mask_i32gather_epi64 | function | ||
| 4677 | core::core_arch::x86::avx512f | _mm512_mask_i32gather_pd | function | ||
| 4678 | core::core_arch::x86::avx512f | _mm512_mask_i32gather_ps | function | ||
| 4679 | core::core_arch::x86::avx512f | _mm512_mask_i32logather_epi64 | function | ||
| 4680 | core::core_arch::x86::avx512f | _mm512_mask_i32logather_pd | function | ||
| 4681 | core::core_arch::x86::avx512f | _mm512_mask_i32loscatter_epi64 | function | ||
| 4682 | core::core_arch::x86::avx512f | _mm512_mask_i32loscatter_pd | function | ||
| 4683 | core::core_arch::x86::avx512f | _mm512_mask_i32scatter_epi32 | function | ||
| 4684 | core::core_arch::x86::avx512f | _mm512_mask_i32scatter_epi64 | function | ||
| 4685 | core::core_arch::x86::avx512f | _mm512_mask_i32scatter_pd | function | ||
| 4686 | core::core_arch::x86::avx512f | _mm512_mask_i32scatter_ps | function | ||
| 4687 | core::core_arch::x86::avx512f | _mm512_mask_i64gather_epi32 | function | ||
| 4688 | core::core_arch::x86::avx512f | _mm512_mask_i64gather_epi64 | function | ||
| 4689 | core::core_arch::x86::avx512f | _mm512_mask_i64gather_pd | function | ||
| 4690 | core::core_arch::x86::avx512f | _mm512_mask_i64gather_ps | function | ||
| 4691 | core::core_arch::x86::avx512f | _mm512_mask_i64scatter_epi32 | function | ||
| 4692 | core::core_arch::x86::avx512f | _mm512_mask_i64scatter_epi64 | function | ||
| 4693 | core::core_arch::x86::avx512f | _mm512_mask_i64scatter_pd | function | ||
| 4694 | core::core_arch::x86::avx512f | _mm512_mask_i64scatter_ps | function | ||
| 4695 | core::core_arch::x86::avx512f | _mm512_mask_load_epi32 | function | ||
| 4696 | core::core_arch::x86::avx512f | _mm512_mask_load_epi64 | function | ||
| 4697 | core::core_arch::x86::avx512f | _mm512_mask_load_pd | function | ||
| 4698 | core::core_arch::x86::avx512f | _mm512_mask_load_ps | function | ||
| 4699 | core::core_arch::x86::avx512f | _mm512_mask_loadu_epi32 | function | ||
| 4700 | core::core_arch::x86::avx512f | _mm512_mask_loadu_epi64 | function | ||
| 4701 | core::core_arch::x86::avx512f | _mm512_mask_loadu_pd | function | ||
| 4702 | core::core_arch::x86::avx512f | _mm512_mask_loadu_ps | function | ||
| 4703 | core::core_arch::x86::avx512f | _mm512_mask_store_epi32 | function | ||
| 4704 | core::core_arch::x86::avx512f | _mm512_mask_store_epi64 | function | ||
| 4705 | core::core_arch::x86::avx512f | _mm512_mask_store_pd | function | ||
| 4706 | core::core_arch::x86::avx512f | _mm512_mask_store_ps | function | ||
| 4707 | core::core_arch::x86::avx512f | _mm512_mask_storeu_epi32 | function | ||
| 4708 | core::core_arch::x86::avx512f | _mm512_mask_storeu_epi64 | function | ||
| 4709 | core::core_arch::x86::avx512f | _mm512_mask_storeu_pd | function | ||
| 4710 | core::core_arch::x86::avx512f | _mm512_mask_storeu_ps | function | ||
| 4711 | core::core_arch::x86::avx512f | _mm512_maskz_expandloadu_epi32 | function | ||
| 4712 | core::core_arch::x86::avx512f | _mm512_maskz_expandloadu_epi64 | function | ||
| 4713 | core::core_arch::x86::avx512f | _mm512_maskz_expandloadu_pd | function | ||
| 4714 | core::core_arch::x86::avx512f | _mm512_maskz_expandloadu_ps | function | ||
| 4715 | core::core_arch::x86::avx512f | _mm512_maskz_load_epi32 | function | ||
| 4716 | core::core_arch::x86::avx512f | _mm512_maskz_load_epi64 | function | ||
| 4717 | core::core_arch::x86::avx512f | _mm512_maskz_load_pd | function | ||
| 4718 | core::core_arch::x86::avx512f | _mm512_maskz_load_ps | function | ||
| 4719 | core::core_arch::x86::avx512f | _mm512_maskz_loadu_epi32 | function | ||
| 4720 | core::core_arch::x86::avx512f | _mm512_maskz_loadu_epi64 | function | ||
| 4721 | core::core_arch::x86::avx512f | _mm512_maskz_loadu_pd | function | ||
| 4722 | core::core_arch::x86::avx512f | _mm512_maskz_loadu_ps | function | ||
| 4723 | core::core_arch::x86::avx512f | _mm512_store_epi32 | function | ||
| 4724 | core::core_arch::x86::avx512f | _mm512_store_epi64 | function | ||
| 4725 | core::core_arch::x86::avx512f | _mm512_store_pd | function | ||
| 4726 | core::core_arch::x86::avx512f | _mm512_store_ps | function | ||
| 4727 | core::core_arch::x86::avx512f | _mm512_store_si512 | function | ||
| 4728 | core::core_arch::x86::avx512f | _mm512_storeu_epi32 | function | ||
| 4729 | core::core_arch::x86::avx512f | _mm512_storeu_epi64 | function | ||
| 4730 | core::core_arch::x86::avx512f | _mm512_storeu_pd | function | ||
| 4731 | core::core_arch::x86::avx512f | _mm512_storeu_ps | function | ||
| 4732 | core::core_arch::x86::avx512f | _mm512_storeu_si512 | function | ||
| 4733 | core::core_arch::x86::avx512f | _mm512_stream_load_si512 | function | ||
| 4734 | core::core_arch::x86::avx512f | _mm512_stream_pd | function | After using this intrinsic, but before any other access to the memory that this intrinsic mutates, a call to [`_mm_sfence`] must be performed by the thread that used the intrinsic. In particular, functions that call this intrinsic should generally call `_mm_sfence` before they return. See [`_mm_sfence`] for details. | |
| 4735 | core::core_arch::x86::avx512f | _mm512_stream_ps | function | After using this intrinsic, but before any other access to the memory that this intrinsic mutates, a call to [`_mm_sfence`] must be performed by the thread that used the intrinsic. In particular, functions that call this intrinsic should generally call `_mm_sfence` before they return. See [`_mm_sfence`] for details. | |
| 4736 | core::core_arch::x86::avx512f | _mm512_stream_si512 | function | After using this intrinsic, but before any other access to the memory that this intrinsic mutates, a call to [`_mm_sfence`] must be performed by the thread that used the intrinsic. In particular, functions that call this intrinsic should generally call `_mm_sfence` before they return. See [`_mm_sfence`] for details. | |
| 4737 | core::core_arch::x86::avx512f | _mm_i32scatter_epi32 | function | ||
| 4738 | core::core_arch::x86::avx512f | _mm_i32scatter_epi64 | function | ||
| 4739 | core::core_arch::x86::avx512f | _mm_i32scatter_pd | function | ||
| 4740 | core::core_arch::x86::avx512f | _mm_i32scatter_ps | function | ||
| 4741 | core::core_arch::x86::avx512f | _mm_i64scatter_epi32 | function | ||
| 4742 | core::core_arch::x86::avx512f | _mm_i64scatter_epi64 | function | ||
| 4743 | core::core_arch::x86::avx512f | _mm_i64scatter_pd | function | ||
| 4744 | core::core_arch::x86::avx512f | _mm_i64scatter_ps | function | ||
| 4745 | core::core_arch::x86::avx512f | _mm_load_epi32 | function | ||
| 4746 | core::core_arch::x86::avx512f | _mm_load_epi64 | function | ||
| 4747 | core::core_arch::x86::avx512f | _mm_loadu_epi32 | function | ||
| 4748 | core::core_arch::x86::avx512f | _mm_loadu_epi64 | function | ||
| 4749 | core::core_arch::x86::avx512f | _mm_mask_compressstoreu_epi32 | function | ||
| 4750 | core::core_arch::x86::avx512f | _mm_mask_compressstoreu_epi64 | function | ||
| 4751 | core::core_arch::x86::avx512f | _mm_mask_compressstoreu_pd | function | ||
| 4752 | core::core_arch::x86::avx512f | _mm_mask_compressstoreu_ps | function | ||
| 4753 | core::core_arch::x86::avx512f | _mm_mask_cvtepi32_storeu_epi16 | function | ||
| 4754 | core::core_arch::x86::avx512f | _mm_mask_cvtepi32_storeu_epi8 | function | ||
| 4755 | core::core_arch::x86::avx512f | _mm_mask_cvtepi64_storeu_epi16 | function | ||
| 4756 | core::core_arch::x86::avx512f | _mm_mask_cvtepi64_storeu_epi32 | function | ||
| 4757 | core::core_arch::x86::avx512f | _mm_mask_cvtepi64_storeu_epi8 | function | ||
| 4758 | core::core_arch::x86::avx512f | _mm_mask_cvtsepi32_storeu_epi16 | function | ||
| 4759 | core::core_arch::x86::avx512f | _mm_mask_cvtsepi32_storeu_epi8 | function | ||
| 4760 | core::core_arch::x86::avx512f | _mm_mask_cvtsepi64_storeu_epi16 | function | ||
| 4761 | core::core_arch::x86::avx512f | _mm_mask_cvtsepi64_storeu_epi32 | function | ||
| 4762 | core::core_arch::x86::avx512f | _mm_mask_cvtsepi64_storeu_epi8 | function | ||
| 4763 | core::core_arch::x86::avx512f | _mm_mask_cvtusepi32_storeu_epi16 | function | ||
| 4764 | core::core_arch::x86::avx512f | _mm_mask_cvtusepi32_storeu_epi8 | function | ||
| 4765 | core::core_arch::x86::avx512f | _mm_mask_cvtusepi64_storeu_epi16 | function | ||
| 4766 | core::core_arch::x86::avx512f | _mm_mask_cvtusepi64_storeu_epi32 | function | ||
| 4767 | core::core_arch::x86::avx512f | _mm_mask_cvtusepi64_storeu_epi8 | function | ||
| 4768 | core::core_arch::x86::avx512f | _mm_mask_expandloadu_epi32 | function | ||
| 4769 | core::core_arch::x86::avx512f | _mm_mask_expandloadu_epi64 | function | ||
| 4770 | core::core_arch::x86::avx512f | _mm_mask_expandloadu_pd | function | ||
| 4771 | core::core_arch::x86::avx512f | _mm_mask_expandloadu_ps | function | ||
| 4772 | core::core_arch::x86::avx512f | _mm_mask_i32scatter_epi32 | function | ||
| 4773 | core::core_arch::x86::avx512f | _mm_mask_i32scatter_epi64 | function | ||
| 4774 | core::core_arch::x86::avx512f | _mm_mask_i32scatter_pd | function | ||
| 4775 | core::core_arch::x86::avx512f | _mm_mask_i32scatter_ps | function | ||
| 4776 | core::core_arch::x86::avx512f | _mm_mask_i64scatter_epi32 | function | ||
| 4777 | core::core_arch::x86::avx512f | _mm_mask_i64scatter_epi64 | function | ||
| 4778 | core::core_arch::x86::avx512f | _mm_mask_i64scatter_pd | function | ||
| 4779 | core::core_arch::x86::avx512f | _mm_mask_i64scatter_ps | function | ||
| 4780 | core::core_arch::x86::avx512f | _mm_mask_load_epi32 | function | ||
| 4781 | core::core_arch::x86::avx512f | _mm_mask_load_epi64 | function | ||
| 4782 | core::core_arch::x86::avx512f | _mm_mask_load_pd | function | ||
| 4783 | core::core_arch::x86::avx512f | _mm_mask_load_ps | function | ||
| 4784 | core::core_arch::x86::avx512f | _mm_mask_load_sd | function | ||
| 4785 | core::core_arch::x86::avx512f | _mm_mask_load_ss | function | ||
| 4786 | core::core_arch::x86::avx512f | _mm_mask_loadu_epi32 | function | ||
| 4787 | core::core_arch::x86::avx512f | _mm_mask_loadu_epi64 | function | ||
| 4788 | core::core_arch::x86::avx512f | _mm_mask_loadu_pd | function | ||
| 4789 | core::core_arch::x86::avx512f | _mm_mask_loadu_ps | function | ||
| 4790 | core::core_arch::x86::avx512f | _mm_mask_store_epi32 | function | ||
| 4791 | core::core_arch::x86::avx512f | _mm_mask_store_epi64 | function | ||
| 4792 | core::core_arch::x86::avx512f | _mm_mask_store_pd | function | ||
| 4793 | core::core_arch::x86::avx512f | _mm_mask_store_ps | function | ||
| 4794 | core::core_arch::x86::avx512f | _mm_mask_store_sd | function | ||
| 4795 | core::core_arch::x86::avx512f | _mm_mask_store_ss | function | ||
| 4796 | core::core_arch::x86::avx512f | _mm_mask_storeu_epi32 | function | ||
| 4797 | core::core_arch::x86::avx512f | _mm_mask_storeu_epi64 | function | ||
| 4798 | core::core_arch::x86::avx512f | _mm_mask_storeu_pd | function | ||
| 4799 | core::core_arch::x86::avx512f | _mm_mask_storeu_ps | function | ||
| 4800 | core::core_arch::x86::avx512f | _mm_maskz_expandloadu_epi32 | function | ||
| 4801 | core::core_arch::x86::avx512f | _mm_maskz_expandloadu_epi64 | function | ||
| 4802 | core::core_arch::x86::avx512f | _mm_maskz_expandloadu_pd | function | ||
| 4803 | core::core_arch::x86::avx512f | _mm_maskz_expandloadu_ps | function | ||
| 4804 | core::core_arch::x86::avx512f | _mm_maskz_load_epi32 | function | ||
| 4805 | core::core_arch::x86::avx512f | _mm_maskz_load_epi64 | function | ||
| 4806 | core::core_arch::x86::avx512f | _mm_maskz_load_pd | function | ||
| 4807 | core::core_arch::x86::avx512f | _mm_maskz_load_ps | function | ||
| 4808 | core::core_arch::x86::avx512f | _mm_maskz_load_sd | function | ||
| 4809 | core::core_arch::x86::avx512f | _mm_maskz_load_ss | function | ||
| 4810 | core::core_arch::x86::avx512f | _mm_maskz_loadu_epi32 | function | ||
| 4811 | core::core_arch::x86::avx512f | _mm_maskz_loadu_epi64 | function | ||
| 4812 | core::core_arch::x86::avx512f | _mm_maskz_loadu_pd | function | ||
| 4813 | core::core_arch::x86::avx512f | _mm_maskz_loadu_ps | function | ||
| 4814 | core::core_arch::x86::avx512f | _mm_mmask_i32gather_epi32 | function | ||
| 4815 | core::core_arch::x86::avx512f | _mm_mmask_i32gather_epi64 | function | ||
| 4816 | core::core_arch::x86::avx512f | _mm_mmask_i32gather_pd | function | ||
| 4817 | core::core_arch::x86::avx512f | _mm_mmask_i32gather_ps | function | ||
| 4818 | core::core_arch::x86::avx512f | _mm_mmask_i64gather_epi32 | function | ||
| 4819 | core::core_arch::x86::avx512f | _mm_mmask_i64gather_epi64 | function | ||
| 4820 | core::core_arch::x86::avx512f | _mm_mmask_i64gather_pd | function | ||
| 4821 | core::core_arch::x86::avx512f | _mm_mmask_i64gather_ps | function | ||
| 4822 | core::core_arch::x86::avx512f | _mm_store_epi32 | function | ||
| 4823 | core::core_arch::x86::avx512f | _mm_store_epi64 | function | ||
| 4824 | core::core_arch::x86::avx512f | _mm_storeu_epi32 | function | ||
| 4825 | core::core_arch::x86::avx512f | _mm_storeu_epi64 | function | ||
| 4826 | core::core_arch::x86::avx512f | _store_mask16 | function | ||
| 4827 | core::core_arch::x86::avx512fp16 | _mm256_load_ph | function | ||
| 4828 | core::core_arch::x86::avx512fp16 | _mm256_loadu_ph | function | ||
| 4829 | core::core_arch::x86::avx512fp16 | _mm256_store_ph | function | ||
| 4830 | core::core_arch::x86::avx512fp16 | _mm256_storeu_ph | function | ||
| 4831 | core::core_arch::x86::avx512fp16 | _mm512_load_ph | function | ||
| 4832 | core::core_arch::x86::avx512fp16 | _mm512_loadu_ph | function | ||
| 4833 | core::core_arch::x86::avx512fp16 | _mm512_store_ph | function | ||
| 4834 | core::core_arch::x86::avx512fp16 | _mm512_storeu_ph | function | ||
| 4835 | core::core_arch::x86::avx512fp16 | _mm_load_ph | function | ||
| 4836 | core::core_arch::x86::avx512fp16 | _mm_load_sh | function | ||
| 4837 | core::core_arch::x86::avx512fp16 | _mm_loadu_ph | function | ||
| 4838 | core::core_arch::x86::avx512fp16 | _mm_mask_load_sh | function | ||
| 4839 | core::core_arch::x86::avx512fp16 | _mm_mask_store_sh | function | ||
| 4840 | core::core_arch::x86::avx512fp16 | _mm_maskz_load_sh | function | ||
| 4841 | core::core_arch::x86::avx512fp16 | _mm_store_ph | function | ||
| 4842 | core::core_arch::x86::avx512fp16 | _mm_store_sh | function | ||
| 4843 | core::core_arch::x86::avx512fp16 | _mm_storeu_ph | function | ||
| 4844 | core::core_arch::x86::avx512vbmi2 | _mm256_mask_compressstoreu_epi16 | function | ||
| 4845 | core::core_arch::x86::avx512vbmi2 | _mm256_mask_compressstoreu_epi8 | function | ||
| 4846 | core::core_arch::x86::avx512vbmi2 | _mm256_mask_expandloadu_epi16 | function | ||
| 4847 | core::core_arch::x86::avx512vbmi2 | _mm256_mask_expandloadu_epi8 | function | ||
| 4848 | core::core_arch::x86::avx512vbmi2 | _mm256_maskz_expandloadu_epi16 | function | ||
| 4849 | core::core_arch::x86::avx512vbmi2 | _mm256_maskz_expandloadu_epi8 | function | ||
| 4850 | core::core_arch::x86::avx512vbmi2 | _mm512_mask_compressstoreu_epi16 | function | ||
| 4851 | core::core_arch::x86::avx512vbmi2 | _mm512_mask_compressstoreu_epi8 | function | ||
| 4852 | core::core_arch::x86::avx512vbmi2 | _mm512_mask_expandloadu_epi16 | function | ||
| 4853 | core::core_arch::x86::avx512vbmi2 | _mm512_mask_expandloadu_epi8 | function | ||
| 4854 | core::core_arch::x86::avx512vbmi2 | _mm512_maskz_expandloadu_epi16 | function | ||
| 4855 | core::core_arch::x86::avx512vbmi2 | _mm512_maskz_expandloadu_epi8 | function | ||
| 4856 | core::core_arch::x86::avx512vbmi2 | _mm_mask_compressstoreu_epi16 | function | ||
| 4857 | core::core_arch::x86::avx512vbmi2 | _mm_mask_compressstoreu_epi8 | function | ||
| 4858 | core::core_arch::x86::avx512vbmi2 | _mm_mask_expandloadu_epi16 | function | ||
| 4859 | core::core_arch::x86::avx512vbmi2 | _mm_mask_expandloadu_epi8 | function | ||
| 4860 | core::core_arch::x86::avx512vbmi2 | _mm_maskz_expandloadu_epi16 | function | ||
| 4861 | core::core_arch::x86::avx512vbmi2 | _mm_maskz_expandloadu_epi8 | function | ||
| 4862 | core::core_arch::x86::avx512vp2intersect | _mm256_2intersect_epi32 | function | ||
| 4863 | core::core_arch::x86::avx512vp2intersect | _mm256_2intersect_epi64 | function | ||
| 4864 | core::core_arch::x86::avx512vp2intersect | _mm512_2intersect_epi32 | function | ||
| 4865 | core::core_arch::x86::avx512vp2intersect | _mm512_2intersect_epi64 | function | ||
| 4866 | core::core_arch::x86::avx512vp2intersect | _mm_2intersect_epi32 | function | ||
| 4867 | core::core_arch::x86::avx512vp2intersect | _mm_2intersect_epi64 | function | ||
| 4868 | core::core_arch::x86::avxneconvert | _mm256_bcstnebf16_ps | function | ||
| 4869 | core::core_arch::x86::avxneconvert | _mm256_bcstnesh_ps | function | ||
| 4870 | core::core_arch::x86::avxneconvert | _mm256_cvtneebf16_ps | function | ||
| 4871 | core::core_arch::x86::avxneconvert | _mm256_cvtneeph_ps | function | ||
| 4872 | core::core_arch::x86::avxneconvert | _mm256_cvtneobf16_ps | function | ||
| 4873 | core::core_arch::x86::avxneconvert | _mm256_cvtneoph_ps | function | ||
| 4874 | core::core_arch::x86::avxneconvert | _mm_bcstnebf16_ps | function | ||
| 4875 | core::core_arch::x86::avxneconvert | _mm_bcstnesh_ps | function | ||
| 4876 | core::core_arch::x86::avxneconvert | _mm_cvtneebf16_ps | function | ||
| 4877 | core::core_arch::x86::avxneconvert | _mm_cvtneeph_ps | function | ||
| 4878 | core::core_arch::x86::avxneconvert | _mm_cvtneobf16_ps | function | ||
| 4879 | core::core_arch::x86::avxneconvert | _mm_cvtneoph_ps | function | ||
| 4880 | core::core_arch::x86::bt | _bittest | function | ||
| 4881 | core::core_arch::x86::bt | _bittestandcomplement | function | ||
| 4882 | core::core_arch::x86::bt | _bittestandreset | function | ||
| 4883 | core::core_arch::x86::bt | _bittestandset | function | ||
| 4884 | core::core_arch::x86::clflushopt | _mm_clflushopt | function | Unlike the prefetch intrinsics, `CLFLUSHOPT` is subject to all the permission checking and faults associated with a byte load, so `p` must point to a byte that is valid for reads. [`_mm_clflush`]: crate::arch::x86::_mm_clflush [`_mm_sfence`]: crate::arch::x86::_mm_sfence [`_mm_mfence`]: crate::arch::x86::_mm_mfence | |
| 4885 | core::core_arch::x86::fxsr | _fxrstor | function | ||
| 4886 | core::core_arch::x86::fxsr | _fxsave | function | ||
| 4887 | core::core_arch::x86::kl | _mm_aesdec128kl_u8 | function | ||
| 4888 | core::core_arch::x86::kl | _mm_aesdec256kl_u8 | function | ||
| 4889 | core::core_arch::x86::kl | _mm_aesdecwide128kl_u8 | function | ||
| 4890 | core::core_arch::x86::kl | _mm_aesdecwide256kl_u8 | function | ||
| 4891 | core::core_arch::x86::kl | _mm_aesenc128kl_u8 | function | ||
| 4892 | core::core_arch::x86::kl | _mm_aesenc256kl_u8 | function | ||
| 4893 | core::core_arch::x86::kl | _mm_aesencwide128kl_u8 | function | ||
| 4894 | core::core_arch::x86::kl | _mm_aesencwide256kl_u8 | function | ||
| 4895 | core::core_arch::x86::kl | _mm_encodekey128_u32 | function | ||
| 4896 | core::core_arch::x86::kl | _mm_encodekey256_u32 | function | ||
| 4897 | core::core_arch::x86::kl | _mm_loadiwkey | function | ||
| 4898 | core::core_arch::x86::rdtsc | __rdtscp | function | ||
| 4899 | core::core_arch::x86::rdtsc | _rdtsc | function | ||
| 4900 | core::core_arch::x86::rtm | _xabort | function | ||
| 4901 | core::core_arch::x86::rtm | _xbegin | function | ||
| 4902 | core::core_arch::x86::rtm | _xend | function | ||
| 4903 | core::core_arch::x86::rtm | _xtest | function | ||
| 4904 | core::core_arch::x86::sse | _MM_GET_EXCEPTION_MASK | function | ||
| 4905 | core::core_arch::x86::sse | _MM_GET_EXCEPTION_STATE | function | ||
| 4906 | core::core_arch::x86::sse | _MM_GET_FLUSH_ZERO_MODE | function | ||
| 4907 | core::core_arch::x86::sse | _MM_GET_ROUNDING_MODE | function | ||
| 4908 | core::core_arch::x86::sse | _MM_SET_EXCEPTION_MASK | function | ||
| 4909 | core::core_arch::x86::sse | _MM_SET_EXCEPTION_STATE | function | ||
| 4910 | core::core_arch::x86::sse | _MM_SET_FLUSH_ZERO_MODE | function | ||
| 4911 | core::core_arch::x86::sse | _MM_SET_ROUNDING_MODE | function | ||
| 4912 | core::core_arch::x86::sse | _mm_getcsr | function | ||
| 4913 | core::core_arch::x86::sse | _mm_load1_ps | function | ||
| 4914 | core::core_arch::x86::sse | _mm_load_ps | function | ||
| 4915 | core::core_arch::x86::sse | _mm_load_ps1 | function | ||
| 4916 | core::core_arch::x86::sse | _mm_load_ss | function | ||
| 4917 | core::core_arch::x86::sse | _mm_loadr_ps | function | ||
| 4918 | core::core_arch::x86::sse | _mm_loadu_ps | function | ||
| 4919 | core::core_arch::x86::sse | _mm_setcsr | function | ||
| 4920 | core::core_arch::x86::sse | _mm_store1_ps | function | ||
| 4921 | core::core_arch::x86::sse | _mm_store_ps | function | ||
| 4922 | core::core_arch::x86::sse | _mm_store_ps1 | function | ||
| 4923 | core::core_arch::x86::sse | _mm_store_ss | function | ||
| 4924 | core::core_arch::x86::sse | _mm_storer_ps | function | ||
| 4925 | core::core_arch::x86::sse | _mm_storeu_ps | function | ||
| 4926 | core::core_arch::x86::sse | _mm_stream_ps | function | After using this intrinsic, but before any other access to the memory that this intrinsic mutates, a call to [`_mm_sfence`] must be performed by the thread that used the intrinsic. In particular, functions that call this intrinsic should generally call `_mm_sfence` before they return. See [`_mm_sfence`] for details. | |
| 4927 | core::core_arch::x86::sse2 | _mm_clflush | function | Unlike the prefetch intrinsics, `CLFLUSH` is subject to all the permission checking and faults associated with a byte load, so `p` must point to a byte that is valid for reads. | |
| 4928 | core::core_arch::x86::sse2 | _mm_load1_pd | function | ||
| 4929 | core::core_arch::x86::sse2 | _mm_load_pd | function | ||
| 4930 | core::core_arch::x86::sse2 | _mm_load_pd1 | function | ||
| 4931 | core::core_arch::x86::sse2 | _mm_load_sd | function | ||
| 4932 | core::core_arch::x86::sse2 | _mm_load_si128 | function | ||
| 4933 | core::core_arch::x86::sse2 | _mm_loadh_pd | function | ||
| 4934 | core::core_arch::x86::sse2 | _mm_loadl_epi64 | function | ||
| 4935 | core::core_arch::x86::sse2 | _mm_loadl_pd | function | ||
| 4936 | core::core_arch::x86::sse2 | _mm_loadr_pd | function | ||
| 4937 | core::core_arch::x86::sse2 | _mm_loadu_pd | function | ||
| 4938 | core::core_arch::x86::sse2 | _mm_loadu_si128 | function | ||
| 4939 | core::core_arch::x86::sse2 | _mm_loadu_si16 | function | ||
| 4940 | core::core_arch::x86::sse2 | _mm_loadu_si32 | function | ||
| 4941 | core::core_arch::x86::sse2 | _mm_loadu_si64 | function | ||
| 4942 | core::core_arch::x86::sse2 | _mm_maskmoveu_si128 | function | After using this intrinsic, but before any other access to the memory that this intrinsic mutates, a call to [`_mm_sfence`] must be performed by the thread that used the intrinsic. In particular, functions that call this intrinsic should generally call `_mm_sfence` before they return. See [`_mm_sfence`] for details. | |
| 4943 | core::core_arch::x86::sse2 | _mm_store1_pd | function | ||
| 4944 | core::core_arch::x86::sse2 | _mm_store_pd | function | ||
| 4945 | core::core_arch::x86::sse2 | _mm_store_pd1 | function | ||
| 4946 | core::core_arch::x86::sse2 | _mm_store_sd | function | ||
| 4947 | core::core_arch::x86::sse2 | _mm_store_si128 | function | ||
| 4948 | core::core_arch::x86::sse2 | _mm_storeh_pd | function | ||
| 4949 | core::core_arch::x86::sse2 | _mm_storel_epi64 | function | ||
| 4950 | core::core_arch::x86::sse2 | _mm_storel_pd | function | ||
| 4951 | core::core_arch::x86::sse2 | _mm_storer_pd | function | ||
| 4952 | core::core_arch::x86::sse2 | _mm_storeu_pd | function | ||
| 4953 | core::core_arch::x86::sse2 | _mm_storeu_si128 | function | ||
| 4954 | core::core_arch::x86::sse2 | _mm_storeu_si16 | function | ||
| 4955 | core::core_arch::x86::sse2 | _mm_storeu_si32 | function | ||
| 4956 | core::core_arch::x86::sse2 | _mm_storeu_si64 | function | ||
| 4957 | core::core_arch::x86::sse2 | _mm_stream_pd | function | After using this intrinsic, but before any other access to the memory that this intrinsic mutates, a call to [`_mm_sfence`] must be performed by the thread that used the intrinsic. In particular, functions that call this intrinsic should generally call `_mm_sfence` before they return. See [`_mm_sfence`] for details. | |
| 4958 | core::core_arch::x86::sse2 | _mm_stream_si128 | function | After using this intrinsic, but before any other access to the memory that this intrinsic mutates, a call to [`_mm_sfence`] must be performed by the thread that used the intrinsic. In particular, functions that call this intrinsic should generally call `_mm_sfence` before they return. See [`_mm_sfence`] for details. | |
| 4959 | core::core_arch::x86::sse2 | _mm_stream_si32 | function | After using this intrinsic, but before any other access to the memory that this intrinsic mutates, a call to [`_mm_sfence`] must be performed by the thread that used the intrinsic. In particular, functions that call this intrinsic should generally call `_mm_sfence` before they return. See [`_mm_sfence`] for details. | |
| 4960 | core::core_arch::x86::sse3 | _mm_lddqu_si128 | function | ||
| 4961 | core::core_arch::x86::sse3 | _mm_loaddup_pd | function | ||
| 4962 | core::core_arch::x86::sse41 | _mm_stream_load_si128 | function | ||
| 4963 | core::core_arch::x86::sse4a | _mm_stream_sd | function | After using this intrinsic, but before any other access to the memory that this intrinsic mutates, a call to [`_mm_sfence`] must be performed by the thread that used the intrinsic. In particular, functions that call this intrinsic should generally call `_mm_sfence` before they return. See [`_mm_sfence`] for details. | |
| 4964 | core::core_arch::x86::sse4a | _mm_stream_ss | function | After using this intrinsic, but before any other access to the memory that this intrinsic mutates, a call to [`_mm_sfence`] must be performed by the thread that used the intrinsic. In particular, functions that call this intrinsic should generally call `_mm_sfence` before they return. See [`_mm_sfence`] for details. | |
| 4965 | core::core_arch::x86::xsave | _xgetbv | function | ||
| 4966 | core::core_arch::x86::xsave | _xrstor | function | ||
| 4967 | core::core_arch::x86::xsave | _xrstors | function | ||
| 4968 | core::core_arch::x86::xsave | _xsave | function | ||
| 4969 | core::core_arch::x86::xsave | _xsavec | function | ||
| 4970 | core::core_arch::x86::xsave | _xsaveopt | function | ||
| 4971 | core::core_arch::x86::xsave | _xsaves | function | ||
| 4972 | core::core_arch::x86::xsave | _xsetbv | function | ||
| 4973 | core::core_arch::x86_64::amx | __tile_cmmimfp16ps | function | ||
| 4974 | core::core_arch::x86_64::amx | __tile_cmmrlfp16ps | function | ||
| 4975 | core::core_arch::x86_64::amx | __tile_cvtrowd2ps | function | ||
| 4976 | core::core_arch::x86_64::amx | __tile_cvtrowps2bf16h | function | ||
| 4977 | core::core_arch::x86_64::amx | __tile_cvtrowps2bf16l | function | ||
| 4978 | core::core_arch::x86_64::amx | __tile_cvtrowps2phh | function | ||
| 4979 | core::core_arch::x86_64::amx | __tile_cvtrowps2phl | function | ||
| 4980 | core::core_arch::x86_64::amx | __tile_dpbf16ps | function | ||
| 4981 | core::core_arch::x86_64::amx | __tile_dpbf8ps | function | ||
| 4982 | core::core_arch::x86_64::amx | __tile_dpbhf8ps | function | ||
| 4983 | core::core_arch::x86_64::amx | __tile_dpbssd | function | ||
| 4984 | core::core_arch::x86_64::amx | __tile_dpbsud | function | ||
| 4985 | core::core_arch::x86_64::amx | __tile_dpbusd | function | ||
| 4986 | core::core_arch::x86_64::amx | __tile_dpbuud | function | ||
| 4987 | core::core_arch::x86_64::amx | __tile_dpfp16ps | function | ||
| 4988 | core::core_arch::x86_64::amx | __tile_dphbf8ps | function | ||
| 4989 | core::core_arch::x86_64::amx | __tile_dphf8ps | function | ||
| 4990 | core::core_arch::x86_64::amx | __tile_loadd | function | ||
| 4991 | core::core_arch::x86_64::amx | __tile_loaddrs | function | ||
| 4992 | core::core_arch::x86_64::amx | __tile_mmultf32ps | function | ||
| 4993 | core::core_arch::x86_64::amx | __tile_movrow | function | ||
| 4994 | core::core_arch::x86_64::amx | __tile_stored | function | ||
| 4995 | core::core_arch::x86_64::amx | __tile_stream_loadd | function | ||
| 4996 | core::core_arch::x86_64::amx | __tile_stream_loaddrs | function | ||
| 4997 | core::core_arch::x86_64::amx | __tile_zero | function | ||
| 4998 | core::core_arch::x86_64::amx | _tile_cmmimfp16ps | function | ||
| 4999 | core::core_arch::x86_64::amx | _tile_cmmrlfp16ps | function | ||
| 5000 | core::core_arch::x86_64::amx | _tile_cvtrowd2ps | function | ||
| 5001 | core::core_arch::x86_64::amx | _tile_cvtrowd2psi | function | ||
| 5002 | core::core_arch::x86_64::amx | _tile_cvtrowps2bf16h | function | ||
| 5003 | core::core_arch::x86_64::amx | _tile_cvtrowps2bf16hi | function | ||
| 5004 | core::core_arch::x86_64::amx | _tile_cvtrowps2bf16l | function | ||
| 5005 | core::core_arch::x86_64::amx | _tile_cvtrowps2bf16li | function | ||
| 5006 | core::core_arch::x86_64::amx | _tile_cvtrowps2phh | function | ||
| 5007 | core::core_arch::x86_64::amx | _tile_cvtrowps2phhi | function | ||
| 5008 | core::core_arch::x86_64::amx | _tile_cvtrowps2phl | function | ||
| 5009 | core::core_arch::x86_64::amx | _tile_cvtrowps2phli | function | ||
| 5010 | core::core_arch::x86_64::amx | _tile_dpbf16ps | function | ||
| 5011 | core::core_arch::x86_64::amx | _tile_dpbf8ps | function | ||
| 5012 | core::core_arch::x86_64::amx | _tile_dpbhf8ps | function | ||
| 5013 | core::core_arch::x86_64::amx | _tile_dpbssd | function | ||
| 5014 | core::core_arch::x86_64::amx | _tile_dpbsud | function | ||
| 5015 | core::core_arch::x86_64::amx | _tile_dpbusd | function | ||
| 5016 | core::core_arch::x86_64::amx | _tile_dpbuud | function | ||
| 5017 | core::core_arch::x86_64::amx | _tile_dpfp16ps | function | ||
| 5018 | core::core_arch::x86_64::amx | _tile_dphbf8ps | function | ||
| 5019 | core::core_arch::x86_64::amx | _tile_dphf8ps | function | ||
| 5020 | core::core_arch::x86_64::amx | _tile_loadconfig | function | ||
| 5021 | core::core_arch::x86_64::amx | _tile_loadd | function | ||
| 5022 | core::core_arch::x86_64::amx | _tile_loaddrs | function | ||
| 5023 | core::core_arch::x86_64::amx | _tile_mmultf32ps | function | ||
| 5024 | core::core_arch::x86_64::amx | _tile_movrow | function | ||
| 5025 | core::core_arch::x86_64::amx | _tile_movrowi | function | ||
| 5026 | core::core_arch::x86_64::amx | _tile_release | function | ||
| 5027 | core::core_arch::x86_64::amx | _tile_storeconfig | function | ||
| 5028 | core::core_arch::x86_64::amx | _tile_stored | function | ||
| 5029 | core::core_arch::x86_64::amx | _tile_stream_loadd | function | ||
| 5030 | core::core_arch::x86_64::amx | _tile_stream_loaddrs | function | ||
| 5031 | core::core_arch::x86_64::amx | _tile_zero | function | ||
| 5032 | core::core_arch::x86_64::bt | _bittest64 | function | ||
| 5033 | core::core_arch::x86_64::bt | _bittestandcomplement64 | function | ||
| 5034 | core::core_arch::x86_64::bt | _bittestandreset64 | function | ||
| 5035 | core::core_arch::x86_64::bt | _bittestandset64 | function | ||
| 5036 | core::core_arch::x86_64::cmpxchg16b | cmpxchg16b | function | ||
| 5037 | core::core_arch::x86_64::fxsr | _fxrstor64 | function | ||
| 5038 | core::core_arch::x86_64::fxsr | _fxsave64 | function | ||
| 5039 | core::core_arch::x86_64::movrs | _movrs_i16 | function | ||
| 5040 | core::core_arch::x86_64::movrs | _movrs_i32 | function | ||
| 5041 | core::core_arch::x86_64::movrs | _movrs_i64 | function | ||
| 5042 | core::core_arch::x86_64::movrs | _movrs_i8 | function | ||
| 5043 | core::core_arch::x86_64::sse2 | _mm_stream_si64 | function | After using this intrinsic, but before any other access to the memory that this intrinsic mutates, a call to [`_mm_sfence`] must be performed by the thread that used the intrinsic. In particular, functions that call this intrinsic should generally call `_mm_sfence` before they return. See [`_mm_sfence`] for details. | |
| 5044 | core::core_arch::x86_64::xsave | _xrstor64 | function | ||
| 5045 | core::core_arch::x86_64::xsave | _xrstors64 | function | ||
| 5046 | core::core_arch::x86_64::xsave | _xsave64 | function | ||
| 5047 | core::core_arch::x86_64::xsave | _xsavec64 | function | ||
| 5048 | core::core_arch::x86_64::xsave | _xsaveopt64 | function | ||
| 5049 | core::core_arch::x86_64::xsave | _xsaves64 | function | ||
| 5050 | core::core_simd::cast::sealed | Sealed | trait | Implementing this trait asserts that the type is a valid vector element for the `simd_cast` or `simd_as` intrinsics. | |
| 5051 | core::core_simd::masks | MaskElement | trait | Type must be a signed integer. | |
| 5052 | core::core_simd::masks::Mask | from_simd_unchecked | function | All elements must be either 0 or -1. | |
| 5053 | core::core_simd::masks::Mask | set_unchecked | function | `index` must be less than `self.len()`. | |
| 5054 | core::core_simd::masks::Mask | test_unchecked | function | `index` must be less than `self.len()`. | |
| 5055 | core::core_simd::vector | SimdElement | trait | This trait, when implemented, asserts the compiler can monomorphize `#[repr(simd)]` structs with the marked type as an element. Strictly, it is valid to impl if the vector will not be miscompiled. Practically, it is user-unfriendly to impl it if the vector won't compile, even when no soundness guarantees are broken by allowing the user to try. | |
| 5056 | core::core_simd::vector::Simd | gather_ptr | function | Each read must satisfy the same conditions as [`core::ptr::read`]. | |
| 5057 | core::core_simd::vector::Simd | gather_select_ptr | function | Enabled elements must satisfy the same conditions as [`core::ptr::read`]. | |
| 5058 | core::core_simd::vector::Simd | gather_select_unchecked | function | Calling this function with an `enable`d out-of-bounds index is *[undefined behavior]* even if the resulting value is not used. | |
| 5059 | core::core_simd::vector::Simd | load_select_ptr | function | Enabled `ptr` elements must be safe to read as if by `core::ptr::read`. | |
| 5060 | core::core_simd::vector::Simd | load_select_unchecked | function | Enabled loads must not exceed the length of `slice`. | |
| 5061 | core::core_simd::vector::Simd | scatter_ptr | function | Each write must satisfy the same conditions as [`core::ptr::write`]. | |
| 5062 | core::core_simd::vector::Simd | scatter_select_ptr | function | Enabled pointers must satisfy the same conditions as [`core::ptr::write`]. | |
| 5063 | core::core_simd::vector::Simd | scatter_select_unchecked | function | Calling this function with an enabled out-of-bounds index is *[undefined behavior]*, and may lead to memory corruption. | |
| 5064 | core::core_simd::vector::Simd | store_select_ptr | function | Memory addresses for element are calculated [`pointer::wrapping_offset`] and each enabled element must satisfy the same conditions as [`core::ptr::write`]. | |
| 5065 | core::core_simd::vector::Simd | store_select_unchecked | function | Every enabled element must be in bounds for the `slice`. | |
| 5066 | core::f128 | to_int_unchecked | function | The value must: * Not be `NaN` * Not be infinite * Be representable in the return type `Int`, after truncating off its fractional part | |
| 5067 | core::f16 | to_int_unchecked | function | The value must: * Not be `NaN` * Not be infinite * Be representable in the return type `Int`, after truncating off its fractional part | |
| 5068 | core::f32 | to_int_unchecked | function | The value must: * Not be `NaN` * Not be infinite * Be representable in the return type `Int`, after truncating off its fractional part | |
| 5069 | core::f64 | to_int_unchecked | function | The value must: * Not be `NaN` * Not be infinite * Be representable in the return type `Int`, after truncating off its fractional part | |
| 5070 | core::ffi | VaArgSafe | trait | When C passes variable arguments, signed integers smaller than [`c_int`] are promoted to [`c_int`], unsigned integers smaller than [`c_uint`] are promoted to [`c_uint`], and [`c_float`] is promoted to [`c_double`]. Implementing this trait for types that are subject to this promotion rule is invalid. [`c_int`]: core::ffi::c_int [`c_long`]: core::ffi::c_long [`c_longlong`]: core::ffi::c_longlong [`c_uint`]: core::ffi::c_uint [`c_ulong`]: core::ffi::c_ulong [`c_ulonglong`]: core::ffi::c_ulonglong [`c_float`]: core::ffi::c_float [`c_double`]: core::ffi::c_double | |
| 5071 | core::ffi::c_str::CStr | from_bytes_with_nul_unchecked | function | The provided slice **must** be nul-terminated and not contain any interior nul bytes. | |
| 5072 | core::ffi::c_str::CStr | from_ptr | function | * The memory pointed to by `ptr` must contain a valid nul terminator at the end of the string. * `ptr` must be [valid] for reads of bytes up to and including the nul terminator. This means in particular: * The entire memory range of this `CStr` must be contained within a single allocation! * `ptr` must be non-null even for a zero-length cstr. * The memory referenced by the returned `CStr` must not be mutated for the duration of lifetime `'a`. * The nul terminator must be within `isize::MAX` from `ptr` > **Note**: This operation is intended to be a 0-cost cast but it is > currently implemented with an up-front calculation of the length of > the string. This is not guaranteed to always be the case. | |
| 5073 | core::ffi::va_list::VaList | next_arg | function | This function is safe to call only if all of the following conditions are satisfied: - There is another c-variadic argument to read. - The actual type of the argument `U` is compatible with `T` (as defined below). - If `U` and `T` are both integer types, then the value passed by the caller must be representable in both types. Types `T` and `U` are compatible when: - `T` and `U` are the same type. - `T` and `U` are integer types of the same size. - `T` and `U` are both pointers, and their target types are compatible. - `T` is a pointer to [`c_void`] and `U` is a pointer to [`i8`] or [`u8`], or vice versa. [`c_void`]: core::ffi::c_void | |
| 5074 | core::field | Field | trait | Given a valid value of type `Self::Base`, there exists a valid value of type `Self::Type` at byte offset `OFFSET` | |
| 5075 | core::future | async_drop_in_place | function | The pointer `_to_drop` must be valid for both reads and writes, not only for the duration of this function call, but also until the returned future has completed. See [ptr::drop_in_place] for additional safety concerns. [ptr::drop_in_place]: crate::ptr::drop_in_place() | |
| 5076 | core::hint | assert_unchecked | function | `cond` must be `true`. It is immediate UB to call this with `false`. | |
| 5077 | core::hint | unreachable_unchecked | function | Reaching this function is *Undefined Behavior*. As the compiler assumes that all forms of Undefined Behavior can never happen, it will eliminate all branches in the surrounding code that it can determine will invariably lead to a call to `unreachable_unchecked()`. If the assumptions embedded in using this function turn out to be wrong - that is, if the site which is calling `unreachable_unchecked()` is actually reachable at runtime - the compiler may have generated nonsensical machine instructions for this situation, including in seemingly unrelated code, causing difficult-to-debug problems. Use this function sparingly. Consider using the [`unreachable!`] macro, which may prevent some optimizations but will safely panic in case it is actually reached at runtime. Benchmark your code to find out if using `unreachable_unchecked()` comes with a performance benefit. | |
| 5078 | core::i128 | unchecked_add | function | This results in undefined behavior when `self + rhs > i128::MAX` or `self + rhs < i128::MIN`, i.e. when [`checked_add`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_add`]: i128::checked_add [`wrapping_add`]: i128::wrapping_add | |
| 5079 | core::i128 | unchecked_cast | function | This results in undefined behavior if the integer value of `self` is bigger than `T::MAX`, or smaller than `T::MIN`, where `T` is the target type. | |
| 5080 | core::i128 | unchecked_div_exact | function | This results in undefined behavior when `rhs == 0`, `self % rhs != 0`, or `self == i128::MIN && rhs == -1`, i.e. when [`checked_div_exact`](Self::checked_div_exact) would return `None`. | |
| 5081 | core::i128 | unchecked_mul | function | This results in undefined behavior when `self * rhs > i128::MAX` or `self * rhs < i128::MIN`, i.e. when [`checked_mul`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_mul`]: i128::checked_mul [`wrapping_mul`]: i128::wrapping_mul | |
| 5082 | core::i128 | unchecked_neg | function | This results in undefined behavior when `self == i128::MIN`, i.e. when [`checked_neg`] would return `None`. [`checked_neg`]: i128::checked_neg | |
| 5083 | core::i128 | unchecked_shl | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shl`] would return `None`. [`checked_shl`]: i128::checked_shl | |
| 5084 | core::i128 | unchecked_shl_exact | function | This results in undefined behavior when `rhs >= self.leading_zeros() && rhs >= self.leading_ones()` i.e. when [`i128::shl_exact`] would return `None`. | |
| 5085 | core::i128 | unchecked_shr | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shr`] would return `None`. [`checked_shr`]: i128::checked_shr | |
| 5086 | core::i128 | unchecked_shr_exact | function | This results in undefined behavior when `rhs > self.trailing_zeros() || rhs >= i128::BITS` i.e. when [`i128::shr_exact`] would return `None`. | |
| 5087 | core::i128 | unchecked_sub | function | This results in undefined behavior when `self - rhs > i128::MAX` or `self - rhs < i128::MIN`, i.e. when [`checked_sub`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_sub`]: i128::checked_sub [`wrapping_sub`]: i128::wrapping_sub | |
| 5088 | core::i16 | unchecked_add | function | This results in undefined behavior when `self + rhs > i16::MAX` or `self + rhs < i16::MIN`, i.e. when [`checked_add`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_add`]: i16::checked_add [`wrapping_add`]: i16::wrapping_add | |
| 5089 | core::i16 | unchecked_cast | function | This results in undefined behavior if the integer value of `self` is bigger than `T::MAX`, or smaller than `T::MIN`, where `T` is the target type. | |
| 5090 | core::i16 | unchecked_div_exact | function | This results in undefined behavior when `rhs == 0`, `self % rhs != 0`, or `self == i16::MIN && rhs == -1`, i.e. when [`checked_div_exact`](Self::checked_div_exact) would return `None`. | |
| 5091 | core::i16 | unchecked_mul | function | This results in undefined behavior when `self * rhs > i16::MAX` or `self * rhs < i16::MIN`, i.e. when [`checked_mul`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_mul`]: i16::checked_mul [`wrapping_mul`]: i16::wrapping_mul | |
| 5092 | core::i16 | unchecked_neg | function | This results in undefined behavior when `self == i16::MIN`, i.e. when [`checked_neg`] would return `None`. [`checked_neg`]: i16::checked_neg | |
| 5093 | core::i16 | unchecked_shl | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shl`] would return `None`. [`checked_shl`]: i16::checked_shl | |
| 5094 | core::i16 | unchecked_shl_exact | function | This results in undefined behavior when `rhs >= self.leading_zeros() && rhs >= self.leading_ones()` i.e. when [`i16::shl_exact`] would return `None`. | |
| 5095 | core::i16 | unchecked_shr | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shr`] would return `None`. [`checked_shr`]: i16::checked_shr | |
| 5096 | core::i16 | unchecked_shr_exact | function | This results in undefined behavior when `rhs > self.trailing_zeros() || rhs >= i16::BITS` i.e. when [`i16::shr_exact`] would return `None`. | |
| 5097 | core::i16 | unchecked_sub | function | This results in undefined behavior when `self - rhs > i16::MAX` or `self - rhs < i16::MIN`, i.e. when [`checked_sub`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_sub`]: i16::checked_sub [`wrapping_sub`]: i16::wrapping_sub | |
| 5098 | core::i32 | unchecked_add | function | This results in undefined behavior when `self + rhs > i32::MAX` or `self + rhs < i32::MIN`, i.e. when [`checked_add`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_add`]: i32::checked_add [`wrapping_add`]: i32::wrapping_add | |
| 5099 | core::i32 | unchecked_cast | function | This results in undefined behavior if the integer value of `self` is bigger than `T::MAX`, or smaller than `T::MIN`, where `T` is the target type. | |
| 5100 | core::i32 | unchecked_div_exact | function | This results in undefined behavior when `rhs == 0`, `self % rhs != 0`, or `self == i32::MIN && rhs == -1`, i.e. when [`checked_div_exact`](Self::checked_div_exact) would return `None`. | |
| 5101 | core::i32 | unchecked_mul | function | This results in undefined behavior when `self * rhs > i32::MAX` or `self * rhs < i32::MIN`, i.e. when [`checked_mul`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_mul`]: i32::checked_mul [`wrapping_mul`]: i32::wrapping_mul | |
| 5102 | core::i32 | unchecked_neg | function | This results in undefined behavior when `self == i32::MIN`, i.e. when [`checked_neg`] would return `None`. [`checked_neg`]: i32::checked_neg | |
| 5103 | core::i32 | unchecked_shl | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shl`] would return `None`. [`checked_shl`]: i32::checked_shl | |
| 5104 | core::i32 | unchecked_shl_exact | function | This results in undefined behavior when `rhs >= self.leading_zeros() && rhs >= self.leading_ones()` i.e. when [`i32::shl_exact`] would return `None`. | |
| 5105 | core::i32 | unchecked_shr | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shr`] would return `None`. [`checked_shr`]: i32::checked_shr | |
| 5106 | core::i32 | unchecked_shr_exact | function | This results in undefined behavior when `rhs > self.trailing_zeros() || rhs >= i32::BITS` i.e. when [`i32::shr_exact`] would return `None`. | |
| 5107 | core::i32 | unchecked_sub | function | This results in undefined behavior when `self - rhs > i32::MAX` or `self - rhs < i32::MIN`, i.e. when [`checked_sub`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_sub`]: i32::checked_sub [`wrapping_sub`]: i32::wrapping_sub | |
| 5108 | core::i64 | unchecked_add | function | This results in undefined behavior when `self + rhs > i64::MAX` or `self + rhs < i64::MIN`, i.e. when [`checked_add`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_add`]: i64::checked_add [`wrapping_add`]: i64::wrapping_add | |
| 5109 | core::i64 | unchecked_cast | function | This results in undefined behavior if the integer value of `self` is bigger than `T::MAX`, or smaller than `T::MIN`, where `T` is the target type. | |
| 5110 | core::i64 | unchecked_div_exact | function | This results in undefined behavior when `rhs == 0`, `self % rhs != 0`, or `self == i64::MIN && rhs == -1`, i.e. when [`checked_div_exact`](Self::checked_div_exact) would return `None`. | |
| 5111 | core::i64 | unchecked_mul | function | This results in undefined behavior when `self * rhs > i64::MAX` or `self * rhs < i64::MIN`, i.e. when [`checked_mul`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_mul`]: i64::checked_mul [`wrapping_mul`]: i64::wrapping_mul | |
| 5112 | core::i64 | unchecked_neg | function | This results in undefined behavior when `self == i64::MIN`, i.e. when [`checked_neg`] would return `None`. [`checked_neg`]: i64::checked_neg | |
| 5113 | core::i64 | unchecked_shl | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shl`] would return `None`. [`checked_shl`]: i64::checked_shl | |
| 5114 | core::i64 | unchecked_shl_exact | function | This results in undefined behavior when `rhs >= self.leading_zeros() && rhs >= self.leading_ones()` i.e. when [`i64::shl_exact`] would return `None`. | |
| 5115 | core::i64 | unchecked_shr | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shr`] would return `None`. [`checked_shr`]: i64::checked_shr | |
| 5116 | core::i64 | unchecked_shr_exact | function | This results in undefined behavior when `rhs > self.trailing_zeros() || rhs >= i64::BITS` i.e. when [`i64::shr_exact`] would return `None`. | |
| 5117 | core::i64 | unchecked_sub | function | This results in undefined behavior when `self - rhs > i64::MAX` or `self - rhs < i64::MIN`, i.e. when [`checked_sub`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_sub`]: i64::checked_sub [`wrapping_sub`]: i64::wrapping_sub | |
| 5118 | core::i8 | unchecked_add | function | This results in undefined behavior when `self + rhs > i8::MAX` or `self + rhs < i8::MIN`, i.e. when [`checked_add`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_add`]: i8::checked_add [`wrapping_add`]: i8::wrapping_add | |
| 5119 | core::i8 | unchecked_cast | function | This results in undefined behavior if the integer value of `self` is bigger than `T::MAX`, or smaller than `T::MIN`, where `T` is the target type. | |
| 5120 | core::i8 | unchecked_div_exact | function | This results in undefined behavior when `rhs == 0`, `self % rhs != 0`, or `self == i8::MIN && rhs == -1`, i.e. when [`checked_div_exact`](Self::checked_div_exact) would return `None`. | |
| 5121 | core::i8 | unchecked_mul | function | This results in undefined behavior when `self * rhs > i8::MAX` or `self * rhs < i8::MIN`, i.e. when [`checked_mul`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_mul`]: i8::checked_mul [`wrapping_mul`]: i8::wrapping_mul | |
| 5122 | core::i8 | unchecked_neg | function | This results in undefined behavior when `self == i8::MIN`, i.e. when [`checked_neg`] would return `None`. [`checked_neg`]: i8::checked_neg | |
| 5123 | core::i8 | unchecked_shl | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shl`] would return `None`. [`checked_shl`]: i8::checked_shl | |
| 5124 | core::i8 | unchecked_shl_exact | function | This results in undefined behavior when `rhs >= self.leading_zeros() && rhs >= self.leading_ones()` i.e. when [`i8::shl_exact`] would return `None`. | |
| 5125 | core::i8 | unchecked_shr | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shr`] would return `None`. [`checked_shr`]: i8::checked_shr | |
| 5126 | core::i8 | unchecked_shr_exact | function | This results in undefined behavior when `rhs > self.trailing_zeros() || rhs >= i8::BITS` i.e. when [`i8::shr_exact`] would return `None`. | |
| 5127 | core::i8 | unchecked_sub | function | This results in undefined behavior when `self - rhs > i8::MAX` or `self - rhs < i8::MIN`, i.e. when [`checked_sub`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_sub`]: i8::checked_sub [`wrapping_sub`]: i8::wrapping_sub | |
| 5128 | core::intrinsics | align_of_val | function | See [`crate::mem::align_of_val_raw`] for safety conditions. | |
| 5129 | core::intrinsics | arith_offset | function | Unlike the `offset` intrinsic, this intrinsic does not restrict the resulting pointer to point into or at the end of an allocated object, and it wraps with two's complement arithmetic. The resulting value is not necessarily valid to be used to actually access memory. The stabilized version of this intrinsic is [`pointer::wrapping_offset`]. | |
| 5130 | core::intrinsics | assume | function | ||
| 5131 | core::intrinsics | atomic_and | function | ||
| 5132 | core::intrinsics | atomic_cxchg | function | ||
| 5133 | core::intrinsics | atomic_cxchgweak | function | ||
| 5134 | core::intrinsics | atomic_fence | function | ||
| 5135 | core::intrinsics | atomic_load | function | ||
| 5136 | core::intrinsics | atomic_max | function | ||
| 5137 | core::intrinsics | atomic_min | function | ||
| 5138 | core::intrinsics | atomic_nand | function | ||
| 5139 | core::intrinsics | atomic_or | function | ||
| 5140 | core::intrinsics | atomic_singlethreadfence | function | ||
| 5141 | core::intrinsics | atomic_store | function | ||
| 5142 | core::intrinsics | atomic_umax | function | ||
| 5143 | core::intrinsics | atomic_umin | function | ||
| 5144 | core::intrinsics | atomic_xadd | function | ||
| 5145 | core::intrinsics | atomic_xchg | function | ||
| 5146 | core::intrinsics | atomic_xor | function | ||
| 5147 | core::intrinsics | atomic_xsub | function | ||
| 5148 | core::intrinsics | catch_unwind | function | ||
| 5149 | core::intrinsics | compare_bytes | function | `left` and `right` must each be [valid] for reads of `bytes` bytes. Note that this applies to the whole range, not just until the first byte that differs. That allows optimizations that can read in large chunks. [valid]: crate::ptr#safety | |
| 5150 | core::intrinsics | const_allocate | function | - The `align` argument must be a power of two. - At compile time, a compile error occurs if this constraint is violated. - At runtime, it is not checked. | |
| 5151 | core::intrinsics | const_deallocate | function | - The `align` argument must be a power of two. - At compile time, a compile error occurs if this constraint is violated. - At runtime, it is not checked. - If the `ptr` is created in an another const, this intrinsic doesn't deallocate it. - If the `ptr` is pointing to a local variable, this intrinsic doesn't deallocate it. | |
| 5152 | core::intrinsics | const_make_global | function | ||
| 5153 | core::intrinsics | copy | function | ||
| 5154 | core::intrinsics | copy_nonoverlapping | function | ||
| 5155 | core::intrinsics | ctlz_nonzero | function | ||
| 5156 | core::intrinsics | cttz_nonzero | function | ||
| 5157 | core::intrinsics | disjoint_bitor | function | Requires that `(a & b) == 0`, or equivalently that `(a | b) == (a + b)`. Otherwise it's immediate UB. | |
| 5158 | core::intrinsics | exact_div | function | ||
| 5159 | core::intrinsics | fadd_fast | function | ||
| 5160 | core::intrinsics | fdiv_fast | function | ||
| 5161 | core::intrinsics | float_to_int_unchecked | function | ||
| 5162 | core::intrinsics | fmul_fast | function | ||
| 5163 | core::intrinsics | frem_fast | function | ||
| 5164 | core::intrinsics | fsub_fast | function | ||
| 5165 | core::intrinsics | nontemporal_store | function | ||
| 5166 | core::intrinsics | offset | function | If the computed offset is non-zero, then both the starting and resulting pointer must be either in bounds or at the end of an allocation. If either pointer is out of bounds or arithmetic overflow occurs then this operation is undefined behavior. The stabilized version of this intrinsic is [`pointer::offset`]. | |
| 5167 | core::intrinsics | ptr_offset_from | function | ||
| 5168 | core::intrinsics | ptr_offset_from_unsigned | function | ||
| 5169 | core::intrinsics | raw_eq | function | It's UB to call this if any of the *bytes* in `*a` or `*b` are uninitialized. Note that this is a stricter criterion than just the *values* being fully-initialized: if `T` has padding, it's UB to call this intrinsic. At compile-time, it is furthermore UB to call this if any of the bytes in `*a` or `*b` have provenance. (The implementation is allowed to branch on the results of comparisons, which is UB if any of their inputs are `undef`.) | |
| 5170 | core::intrinsics | read_via_copy | function | ||
| 5171 | core::intrinsics | size_of_val | function | See [`crate::mem::size_of_val_raw`] for safety conditions. | |
| 5172 | core::intrinsics | slice_get_unchecked | function | - `index < PtrMetadata(slice_ptr)`, so the indexing is in-bounds for the slice - the resulting offsetting is in-bounds of the allocation, which is always the case for references, but needs to be upheld manually for pointers | |
| 5173 | core::intrinsics | transmute_unchecked | function | ||
| 5174 | core::intrinsics | typed_swap_nonoverlapping | function | Behavior is undefined if any of the following conditions are violated: * Both `x` and `y` must be [valid] for both reads and writes. * Both `x` and `y` must be properly aligned. * The region of memory beginning at `x` must *not* overlap with the region of memory beginning at `y`. * The memory pointed by `x` and `y` must both contain values of type `T`. [valid]: crate::ptr#safety | |
| 5175 | core::intrinsics | unaligned_volatile_load | function | ||
| 5176 | core::intrinsics | unaligned_volatile_store | function | ||
| 5177 | core::intrinsics | unchecked_add | function | ||
| 5178 | core::intrinsics | unchecked_div | function | ||
| 5179 | core::intrinsics | unchecked_funnel_shl | function | ||
| 5180 | core::intrinsics | unchecked_funnel_shr | function | ||
| 5181 | core::intrinsics | unchecked_mul | function | ||
| 5182 | core::intrinsics | unchecked_rem | function | ||
| 5183 | core::intrinsics | unchecked_shl | function | ||
| 5184 | core::intrinsics | unchecked_shr | function | ||
| 5185 | core::intrinsics | unchecked_sub | function | ||
| 5186 | core::intrinsics | unreachable | function | ||
| 5187 | core::intrinsics | va_arg | function | This function is only sound to call when: - there is a next variable argument available. - the next argument's type must be ABI-compatible with the type `T`. - the next argument must have a properly initialized value of type `T`. Calling this function with an incompatible type, an invalid value, or when there are no more variable arguments, is unsound. | |
| 5188 | core::intrinsics | va_end | function | `ap` must not be used to access variable arguments after this call. | |
| 5189 | core::intrinsics | volatile_copy_memory | function | ||
| 5190 | core::intrinsics | volatile_copy_nonoverlapping_memory | function | The safety requirements are consistent with [`copy_nonoverlapping`] while the read and write behaviors are volatile, which means it will not be optimized out unless `_count` or `size_of::<T>()` is equal to zero. [`copy_nonoverlapping`]: ptr::copy_nonoverlapping | |
| 5191 | core::intrinsics | volatile_load | function | ||
| 5192 | core::intrinsics | volatile_set_memory | function | The safety requirements are consistent with [`write_bytes`] while the write behavior is volatile, which means it will not be optimized out unless `_count` or `size_of::<T>()` is equal to zero. [`write_bytes`]: ptr::write_bytes | |
| 5193 | core::intrinsics | volatile_store | function | ||
| 5194 | core::intrinsics | vtable_align | function | `ptr` must point to a vtable. | |
| 5195 | core::intrinsics | vtable_size | function | `ptr` must point to a vtable. | |
| 5196 | core::intrinsics | write_bytes | function | ||
| 5197 | core::intrinsics | write_via_move | function | ||
| 5198 | core::intrinsics::bounds | BuiltinDeref | trait | Must actually *be* such a type. | |
| 5199 | core::intrinsics::bounds | FloatPrimitive | trait | Must actually *be* such a type. | |
| 5200 | core::intrinsics::simd | simd_add | function | ||
| 5201 | core::intrinsics::simd | simd_and | function | ||
| 5202 | core::intrinsics::simd | simd_arith_offset | function | ||
| 5203 | core::intrinsics::simd | simd_as | function | ||
| 5204 | core::intrinsics::simd | simd_bitmask | function | `x` must contain only `0` and `!0`. | |
| 5205 | core::intrinsics::simd | simd_bitreverse | function | ||
| 5206 | core::intrinsics::simd | simd_bswap | function | ||
| 5207 | core::intrinsics::simd | simd_carryless_mul | function | ||
| 5208 | core::intrinsics::simd | simd_cast | function | Casting from integer types is always safe. Casting between two float types is also always safe. Casting floats to integers truncates, following the same rules as `to_int_unchecked`. Specifically, each element must: * Not be `NaN` * Not be infinite * Be representable in the return type, after truncating off its fractional part | |
| 5209 | core::intrinsics::simd | simd_cast_ptr | function | ||
| 5210 | core::intrinsics::simd | simd_ceil | function | ||
| 5211 | core::intrinsics::simd | simd_ctlz | function | ||
| 5212 | core::intrinsics::simd | simd_ctpop | function | ||
| 5213 | core::intrinsics::simd | simd_cttz | function | ||
| 5214 | core::intrinsics::simd | simd_div | function | For integers, `rhs` must not contain any zero elements. Additionally for signed integers, `<int>::MIN / -1` is undefined behavior. | |
| 5215 | core::intrinsics::simd | simd_eq | function | ||
| 5216 | core::intrinsics::simd | simd_expose_provenance | function | ||
| 5217 | core::intrinsics::simd | simd_extract | function | `idx` must be const and in-bounds of the vector. | |
| 5218 | core::intrinsics::simd | simd_extract_dyn | function | `idx` must be in-bounds of the vector. | |
| 5219 | core::intrinsics::simd | simd_fabs | function | ||
| 5220 | core::intrinsics::simd | simd_fcos | function | ||
| 5221 | core::intrinsics::simd | simd_fexp | function | ||
| 5222 | core::intrinsics::simd | simd_fexp2 | function | ||
| 5223 | core::intrinsics::simd | simd_flog | function | ||
| 5224 | core::intrinsics::simd | simd_flog10 | function | ||
| 5225 | core::intrinsics::simd | simd_flog2 | function | ||
| 5226 | core::intrinsics::simd | simd_floor | function | ||
| 5227 | core::intrinsics::simd | simd_fma | function | ||
| 5228 | core::intrinsics::simd | simd_fsin | function | ||
| 5229 | core::intrinsics::simd | simd_fsqrt | function | ||
| 5230 | core::intrinsics::simd | simd_funnel_shl | function | Each element of `shift` must be less than `<int>::BITS`. | |
| 5231 | core::intrinsics::simd | simd_funnel_shr | function | Each element of `shift` must be less than `<int>::BITS`. | |
| 5232 | core::intrinsics::simd | simd_gather | function | Unmasked values in `T` must be readable as if by `<ptr>::read` (e.g. aligned to the element type). `mask` must only contain `0` or `!0` values. | |
| 5233 | core::intrinsics::simd | simd_ge | function | ||
| 5234 | core::intrinsics::simd | simd_gt | function | ||
| 5235 | core::intrinsics::simd | simd_insert | function | `idx` must be in-bounds of the vector. | |
| 5236 | core::intrinsics::simd | simd_insert_dyn | function | `idx` must be in-bounds of the vector. | |
| 5237 | core::intrinsics::simd | simd_le | function | ||
| 5238 | core::intrinsics::simd | simd_lt | function | ||
| 5239 | core::intrinsics::simd | simd_masked_load | function | `ptr` must be aligned according to the `ALIGN` parameter, see [`SimdAlign`] for details. `mask` must only contain `0` or `!0` values. | |
| 5240 | core::intrinsics::simd | simd_masked_store | function | `ptr` must be aligned according to the `ALIGN` parameter, see [`SimdAlign`] for details. `mask` must only contain `0` or `!0` values. | |
| 5241 | core::intrinsics::simd | simd_maximum_number_nsz | function | ||
| 5242 | core::intrinsics::simd | simd_minimum_number_nsz | function | ||
| 5243 | core::intrinsics::simd | simd_mul | function | ||
| 5244 | core::intrinsics::simd | simd_ne | function | ||
| 5245 | core::intrinsics::simd | simd_neg | function | ||
| 5246 | core::intrinsics::simd | simd_or | function | ||
| 5247 | core::intrinsics::simd | simd_reduce_add_ordered | function | ||
| 5248 | core::intrinsics::simd | simd_reduce_add_unordered | function | ||
| 5249 | core::intrinsics::simd | simd_reduce_all | function | `x` must contain only `0` or `!0`. | |
| 5250 | core::intrinsics::simd | simd_reduce_and | function | ||
| 5251 | core::intrinsics::simd | simd_reduce_any | function | `x` must contain only `0` or `!0`. | |
| 5252 | core::intrinsics::simd | simd_reduce_max | function | ||
| 5253 | core::intrinsics::simd | simd_reduce_min | function | ||
| 5254 | core::intrinsics::simd | simd_reduce_mul_ordered | function | ||
| 5255 | core::intrinsics::simd | simd_reduce_mul_unordered | function | ||
| 5256 | core::intrinsics::simd | simd_reduce_or | function | ||
| 5257 | core::intrinsics::simd | simd_reduce_xor | function | ||
| 5258 | core::intrinsics::simd | simd_relaxed_fma | function | ||
| 5259 | core::intrinsics::simd | simd_rem | function | For integers, `rhs` must not contain any zero elements. Additionally for signed integers, `<int>::MIN / -1` is undefined behavior. | |
| 5260 | core::intrinsics::simd | simd_round | function | ||
| 5261 | core::intrinsics::simd | simd_round_ties_even | function | ||
| 5262 | core::intrinsics::simd | simd_saturating_add | function | ||
| 5263 | core::intrinsics::simd | simd_saturating_sub | function | ||
| 5264 | core::intrinsics::simd | simd_scatter | function | Unmasked values in `T` must be writeable as if by `<ptr>::write` (e.g. aligned to the element type). `mask` must only contain `0` or `!0` values. | |
| 5265 | core::intrinsics::simd | simd_select | function | `mask` must only contain `0` and `!0`. | |
| 5266 | core::intrinsics::simd | simd_select_bitmask | function | ||
| 5267 | core::intrinsics::simd | simd_shl | function | Each element of `rhs` must be less than `<int>::BITS`. | |
| 5268 | core::intrinsics::simd | simd_shr | function | Each element of `rhs` must be less than `<int>::BITS`. | |
| 5269 | core::intrinsics::simd | simd_shuffle | function | ||
| 5270 | core::intrinsics::simd | simd_splat | function | ||
| 5271 | core::intrinsics::simd | simd_sub | function | ||
| 5272 | core::intrinsics::simd | simd_trunc | function | ||
| 5273 | core::intrinsics::simd | simd_with_exposed_provenance | function | ||
| 5274 | core::intrinsics::simd | simd_xor | function | ||
| 5275 | core::intrinsics::simd::scalable | sve_tuple_create2 | function | ||
| 5276 | core::intrinsics::simd::scalable | sve_tuple_create3 | function | ||
| 5277 | core::intrinsics::simd::scalable | sve_tuple_create4 | function | ||
| 5278 | core::intrinsics::simd::scalable | sve_tuple_get | function | `IDX` must be in-bounds of the tuple. | |
| 5279 | core::intrinsics::simd::scalable | sve_tuple_set | function | `IDX` must be in-bounds of the tuple. | |
| 5280 | core::io::borrowed_buf::BorrowedBuf | set_init | function | All the bytes of the buffer must be initialized. | |
| 5281 | core::io::borrowed_buf::BorrowedCursor | advance | function | The caller must ensure that the first `n` bytes of the cursor have been properly initialised. | |
| 5282 | core::io::borrowed_buf::BorrowedCursor | as_mut | function | The caller must not uninitialize any bytes of the cursor if it is initialized. | |
| 5283 | core::io::borrowed_buf::BorrowedCursor | set_init | function | All the bytes of the cursor must be initialized. | |
| 5284 | core::isize | unchecked_add | function | This results in undefined behavior when `self + rhs > isize::MAX` or `self + rhs < isize::MIN`, i.e. when [`checked_add`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_add`]: isize::checked_add [`wrapping_add`]: isize::wrapping_add | |
| 5285 | core::isize | unchecked_cast | function | This results in undefined behavior if the integer value of `self` is bigger than `T::MAX`, or smaller than `T::MIN`, where `T` is the target type. | |
| 5286 | core::isize | unchecked_div_exact | function | This results in undefined behavior when `rhs == 0`, `self % rhs != 0`, or `self == isize::MIN && rhs == -1`, i.e. when [`checked_div_exact`](Self::checked_div_exact) would return `None`. | |
| 5287 | core::isize | unchecked_mul | function | This results in undefined behavior when `self * rhs > isize::MAX` or `self * rhs < isize::MIN`, i.e. when [`checked_mul`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_mul`]: isize::checked_mul [`wrapping_mul`]: isize::wrapping_mul | |
| 5288 | core::isize | unchecked_neg | function | This results in undefined behavior when `self == isize::MIN`, i.e. when [`checked_neg`] would return `None`. [`checked_neg`]: isize::checked_neg | |
| 5289 | core::isize | unchecked_shl | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shl`] would return `None`. [`checked_shl`]: isize::checked_shl | |
| 5290 | core::isize | unchecked_shl_exact | function | This results in undefined behavior when `rhs >= self.leading_zeros() && rhs >= self.leading_ones()` i.e. when [`isize::shl_exact`] would return `None`. | |
| 5291 | core::isize | unchecked_shr | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shr`] would return `None`. [`checked_shr`]: isize::checked_shr | |
| 5292 | core::isize | unchecked_shr_exact | function | This results in undefined behavior when `rhs > self.trailing_zeros() || rhs >= isize::BITS` i.e. when [`isize::shr_exact`] would return `None`. | |
| 5293 | core::isize | unchecked_sub | function | This results in undefined behavior when `self - rhs > isize::MAX` or `self - rhs < isize::MIN`, i.e. when [`checked_sub`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_sub`]: isize::checked_sub [`wrapping_sub`]: isize::wrapping_sub | |
| 5294 | core::iter | TrustedLen | trait | This trait must only be implemented when the contract is upheld. Consumers of this trait must inspect [`Iterator::size_hint()`]’s upper bound. | |
| 5295 | core::iter | TrustedStep | trait | The implementation of [`Step`] for the given type must guarantee all invariants of all methods are upheld. See the [`Step`] trait's documentation for details. Consumers are free to rely on the invariants in unsafe code. | |
| 5296 | core::marker | Freeze | trait | This trait is a core part of the language, it is just expressed as a trait in libcore for convenience. Do *not* implement it for other types. | |
| 5297 | core::marker | UnsafeUnpin | trait | ||
| 5298 | core::mem | TransmuteFrom | trait | If `Dst: TransmuteFrom<Src, ASSUMPTIONS>`, the compiler guarantees that `Src` is soundly *union-transmutable* into a value of type `Dst`, provided that the programmer has guaranteed that the given [`ASSUMPTIONS`](Assume) are satisfied. A union-transmute is any bit-reinterpretation conversion in the form of: ```rust pub unsafe fn transmute_via_union<Src, Dst>(src: Src) -> Dst { use core::mem::ManuallyDrop; #[repr(C)] union Transmute<Src, Dst> { src: ManuallyDrop<Src>, dst: ManuallyDrop<Dst>, } let transmute = Transmute { src: ManuallyDrop::new(src), }; let dst = unsafe { transmute.dst }; ManuallyDrop::into_inner(dst) } ``` Note that this construction is more permissive than [`mem::transmute_copy`](super::transmute_copy); union-transmutes permit conversions that extend the bits of `Src` with trailing padding to fill trailing uninitialized bytes of `Self`; e.g.: ```rust #![feature(transmutability)] use core::mem::{Assume, TransmuteFrom}; let src = 42u8; // size = 1 #[repr(C, align(2))] struct Dst(u8); // size = 2 let _ = unsafe { <Dst as TransmuteFrom<u8, { Assume::SAFETY }>>::transmute(src) }; ``` | |
| 5299 | core::mem | align_of_val_raw | function | This function is only safe to call if the following conditions hold: - If `T` is `Sized`, this function is always safe to call. - If the unsized tail of `T` is: - a [slice], then the length of the slice tail must be an initialized integer, and the size of the *entire value* (dynamic tail length + statically sized prefix) must fit in `isize`. For the special case where the dynamic tail length is 0, this function is safe to call. - a [trait object], then the vtable part of the pointer must point to a valid vtable acquired by an unsizing coercion, and the size of the *entire value* (dynamic tail length + statically sized prefix) must fit in `isize`. - an (unstable) [extern type], then this function is always safe to call, but may panic or otherwise return the wrong value, as the extern type's layout is not known. This is the same behavior as [`align_of_val`] on a reference to a type with an extern type tail. - otherwise, it is conservatively not allowed to call this function. [trait object]: ../../book/ch17-02-trait-objects.html [extern type]: ../../unstable-book/language-features/extern-types.html | |
| 5300 | core::mem | conjure_zst | function | - `T` must be *[inhabited]*, i.e. possible to construct. This means that types like zero-variant enums and [`!`] are unsound to conjure. - You must use the value only in ways which do not violate any *safety* invariants of the type. While it's easy to create a *valid* instance of an inhabited ZST, since having no bits in its representation means there's only one possible value, that doesn't mean that it's always *sound* to do so. For example, a library could design zero-sized tokens that are `!Default + !Clone`, limiting their creation to functions that initialize some state or establish a scope. Conjuring such a token could break invariants and lead to unsoundness. | |
| 5301 | core::mem | size_of_val_raw | function | This function is only safe to call if the following conditions hold: - If `T` is `Sized`, this function is always safe to call. - If the unsized tail of `T` is: - a [slice], then the length of the slice tail must be an initialized integer, and the size of the *entire value* (dynamic tail length + statically sized prefix) must fit in `isize`. For the special case where the dynamic tail length is 0, this function is safe to call. - a [trait object], then the vtable part of the pointer must point to a valid vtable acquired by an unsizing coercion, and the size of the *entire value* (dynamic tail length + statically sized prefix) must fit in `isize`. - an (unstable) [extern type], then this function is always safe to call, but may panic or otherwise return the wrong value, as the extern type's layout is not known. This is the same behavior as [`size_of_val`] on a reference to a type with an extern type tail. - otherwise, it is conservatively not allowed to call this function. [`size_of::<T>()`]: size_of [trait object]: ../../book/ch17-02-trait-objects.html [extern type]: ../../unstable-book/language-features/extern-types.html | |
| 5302 | core::mem | transmute | function | ||
| 5303 | core::mem | transmute_copy | function | ||
| 5304 | core::mem | transmute_neo | function | ||
| 5305 | core::mem | transmute_prefix | function | If `size_of::<Src>() >= size_of::<Dst>()`, the first `size_of::<Dst>()` bytes of `src` must be be *valid* when interpreted as a `Dst`. (In this case, the preconditions are the same as for `transmute_copy(&ManuallyDrop::new(src))`.) If `size_of::<Src>() <= size_of::<Dst>()`, the bytes of `src` padded with uninitialized bytes afterwards up to a total size of `size_of::<Dst>()` must be *valid* when interpreted as a `Dst`. In both cases, any safety preconditions of the `Dst` type must also be upheld. | |
| 5306 | core::mem | uninitialized | function | ||
| 5307 | core::mem | zeroed | function | ||
| 5308 | core::mem::alignment::Alignment | new_unchecked | function | `align` must be a power of two. Equivalently, it must be `1 << exp` for some `exp` in `0..usize::BITS`. It must *not* be zero. | |
| 5309 | core::mem::alignment::Alignment | of_val_raw | function | This function is only safe to call if the following conditions hold: - If `T` is `Sized`, this function is always safe to call. - If the unsized tail of `T` is: - a [slice], then the length of the slice tail must be an initialized integer, and the size of the *entire value* (dynamic tail length + statically sized prefix) must fit in `isize`. For the special case where the dynamic tail length is 0, this function is safe to call. - a [trait object], then the vtable part of the pointer must point to a valid vtable acquired by an unsizing coercion, and the size of the *entire value* (dynamic tail length + statically sized prefix) must fit in `isize`. - an (unstable) [extern type], then this function is always safe to call, but may panic or otherwise return the wrong value, as the extern type's layout is not known. This is the same behavior as [`Alignment::of_val`] on a reference to a type with an extern type tail. - otherwise, it is conservatively not allowed to call this function. [trait object]: ../../book/ch17-02-trait-objects.html [extern type]: ../../unstable-book/language-features/extern-types.html | |
| 5310 | core::mem::manually_drop::ManuallyDrop | drop | function | This function runs the destructor of the contained value. Other than changes made by the destructor itself, the memory is left unchanged, and so as far as the compiler is concerned still holds a bit-pattern which is valid for the type `T`. However, this "zombie" value should not be exposed to safe code, and this function should not be called more than once. To use a value after it's been dropped, or drop a value multiple times, can cause Undefined Behavior (depending on what `drop` does). This is normally prevented by the type system, but users of `ManuallyDrop` must uphold those guarantees without assistance from the compiler. [pinned]: crate::pin | |
| 5311 | core::mem::manually_drop::ManuallyDrop | take | function | This function semantically moves out the contained value without preventing further usage, leaving the state of this container unchanged. It is your responsibility to ensure that this `ManuallyDrop` is not used again. | |
| 5312 | core::mem::maybe_uninit::MaybeUninit | array_assume_init | function | It is up to the caller to guarantee that all elements of the array are in an initialized state. | |
| 5313 | core::mem::maybe_uninit::MaybeUninit | assume_init | function | It is up to the caller to guarantee that the `MaybeUninit<T>` really is in an initialized state, i.e., a state that is considered ["valid" for type `T`][validity]. Calling this when the content is not yet fully initialized causes immediate undefined behavior. The [type-level documentation][inv] contains more information about this initialization invariant. It is a common mistake to assume that this function is safe to call on integers because they can hold all bit patterns. It is also a common mistake to think that calling this function is UB if any byte is uninitialized. Both of these assumptions are wrong. If that is surprising to you, please read the [type-level documentation][inv]. [inv]: #initialization-invariant [validity]: ../../reference/behavior-considered-undefined.html#r-undefined.validity On top of that, remember that most types have additional invariants beyond merely being considered initialized at the type level. For example, a `1`-initialized [`Vec<T>`] is considered initialized (under the current implementation; this does not constitute a stable guarantee) because the only requirement the compiler knows about it is that the data pointer must be non-null. Creating such a `Vec<T>` does not cause *immediate* undefined behavior, but will cause undefined behavior with most safe operations (including dropping it). [`Vec<T>`]: ../../std/vec/struct.Vec.html | |
| 5314 | core::mem::maybe_uninit::MaybeUninit | assume_init_drop | function | It is up to the caller to guarantee that the `MaybeUninit<T>` really is in an initialized state. Calling this when the content is not yet fully initialized causes undefined behavior. On top of that, all additional invariants of the type `T` must be satisfied, as the `Drop` implementation of `T` (or its members) may rely on this. For example, setting a `Vec<T>` to an invalid but non-null address makes it initialized (under the current implementation; this does not constitute a stable guarantee), because the only requirement the compiler knows about it is that the data pointer must be non-null. Dropping such a `Vec<T>` however will cause undefined behavior. [`assume_init`]: MaybeUninit::assume_init | |
| 5315 | core::mem::maybe_uninit::MaybeUninit | assume_init_mut | function | Calling this when the content is not yet fully initialized causes undefined behavior: it is up to the caller to guarantee that the `MaybeUninit<T>` really is in an initialized state. For instance, `.assume_init_mut()` cannot be used to initialize a `MaybeUninit`. | |
| 5316 | core::mem::maybe_uninit::MaybeUninit | assume_init_read | function | It is up to the caller to guarantee that the `MaybeUninit<T>` really is in an initialized state. Calling this when the content is not yet fully initialized causes undefined behavior. The [type-level documentation][inv] contains more information about this initialization invariant. Moreover, similar to the [`ptr::read`] function, this function creates a bitwise copy of the contents, regardless whether the contained type implements the [`Copy`] trait or not. When using multiple copies of the data (by calling `assume_init_read` multiple times, or first calling `assume_init_read` and then [`assume_init`]), it is your responsibility to ensure that data may indeed be duplicated. [inv]: #initialization-invariant [`assume_init`]: MaybeUninit::assume_init | |
| 5317 | core::mem::maybe_uninit::MaybeUninit | assume_init_ref | function | Calling this when the content is not yet fully initialized causes undefined behavior: it is up to the caller to guarantee that the `MaybeUninit<T>` really is in an initialized state. | |
| 5318 | core::num | ZeroablePrimitive | trait | Types implementing this trait must be primitives that are valid when zeroed. The associated `Self::NonZeroInner` type must have the same size+align as `Self`, but with a niche and bit validity making it so the following `transmutes` are sound: - `Self::NonZeroInner` to `Option<Self::NonZeroInner>` - `Option<Self::NonZeroInner>` to `Self` (And, consequently, `Self::NonZeroInner` to `Self`.) | |
| 5319 | core::num::nonzero::NonZero | from_mut_unchecked | function | The referenced value must not be zero. | |
| 5320 | core::num::nonzero::NonZero | new_unchecked | function | The value must not be zero. | |
| 5321 | core::num::nonzero::NonZero | unchecked_add | function | This results in undefined behavior when `self + rhs > usize::MAX`. This results in undefined behavior when `self + rhs > u128::MAX`. This results in undefined behavior when `self + rhs > u64::MAX`. This results in undefined behavior when `self + rhs > u32::MAX`. This results in undefined behavior when `self + rhs > u16::MAX`. This results in undefined behavior when `self + rhs > u8::MAX`. | |
| 5322 | core::num::nonzero::NonZero | unchecked_mul | function | This results in undefined behavior when `self * rhs > i64::MAX`, or `self * rhs < i64::MIN`. This results in undefined behavior when `self * rhs > i8::MAX`, or `self * rhs < i8::MIN`. This results in undefined behavior when `self * rhs > isize::MAX`, or `self * rhs < isize::MIN`. This results in undefined behavior when `self * rhs > i32::MAX`, or `self * rhs < i32::MIN`. This results in undefined behavior when `self * rhs > usize::MAX`. This results in undefined behavior when `self * rhs > i128::MAX`, or `self * rhs < i128::MIN`. This results in undefined behavior when `self * rhs > u128::MAX`. This results in undefined behavior when `self * rhs > u64::MAX`. This results in undefined behavior when `self * rhs > u32::MAX`. This results in undefined behavior when `self * rhs > i16::MAX`, or `self * rhs < i16::MIN`. This results in undefined behavior when `self * rhs > u16::MAX`. This results in undefined behavior when `self * rhs > u8::MAX`. | |
| 5323 | core::ops | DerefPure | trait | ||
| 5324 | core::option::Option | unwrap_unchecked | function | Calling this method on [`None`] is *[undefined behavior]*. [undefined behavior]: https://doc.rust-lang.org/reference/behavior-considered-undefined.html | |
| 5325 | core::pin | PinCoerceUnsized | trait | Given a pointer of this type, the concrete type returned by its `deref` method and (if it implements `DerefMut`) its `deref_mut` method must be the same type and must not change without a modification. The following operations are not considered modifications: * Moving the pointer. * Performing unsizing coercions on the pointer. * Performing dynamic dispatch with the pointer. * Calling `deref` or `deref_mut` on the pointer. The concrete type of a trait object is the type that the vtable corresponds to. The concrete type of a slice is an array of the same element type and the length specified in the metadata. The concrete type of a sized type is the type itself. | |
| 5326 | core::pin::Pin | get_unchecked_mut | function | This function is unsafe. You must guarantee that you will never move the data out of the mutable reference you receive when you call this function, so that the invariants on the `Pin` type can be upheld. If the underlying data is `Unpin`, `Pin::get_mut` should be used instead. | |
| 5327 | core::pin::Pin | into_inner_unchecked | function | This function is unsafe. You must guarantee that you will continue to treat the pointer `Ptr` as pinned after you call this function, so that the invariants on the `Pin` type can be upheld. If the code using the resulting `Ptr` does not continue to maintain the pinning invariants that is a violation of the API contract and may lead to undefined behavior in later (safe) operations. Note that you must be able to guarantee that the data pointed to by `Ptr` will be treated as pinned all the way until its `drop` handler is complete! *For more information, see the [`pin` module docs][self]* If the underlying data is [`Unpin`], [`Pin::into_inner`] should be used instead. | |
| 5328 | core::pin::Pin | map_unchecked | function | This function is unsafe. You must guarantee that the data you return will not move so long as the argument value does not move (for example, because it is one of the fields of that value), and also that you do not move out of the argument you receive to the interior function. [`pin` module]: self#projections-and-structural-pinning | |
| 5329 | core::pin::Pin | map_unchecked_mut | function | This function is unsafe. You must guarantee that the data you return will not move so long as the argument value does not move (for example, because it is one of the fields of that value), and also that you do not move out of the argument you receive to the interior function. [`pin` module]: self#projections-and-structural-pinning | |
| 5330 | core::pin::Pin | new_unchecked | function | This constructor is unsafe because we cannot guarantee that the data pointed to by `pointer` is pinned. At its core, pinning a value means making the guarantee that the value's data will not be moved nor have its storage invalidated until it gets dropped. For a more thorough explanation of pinning, see the [`pin` module docs]. If the caller that is constructing this `Pin<Ptr>` does not ensure that the data `Ptr` points to is pinned, that is a violation of the API contract and may lead to undefined behavior in later (even safe) operations. By using this method, you are also making a promise about the [`Deref`], [`DerefMut`], and [`Drop`] implementations of `Ptr`, if they exist. Most importantly, they must not move out of their `self` arguments: `Pin::as_mut` and `Pin::as_ref` will call `DerefMut::deref_mut` and `Deref::deref` *on the pointer type `Ptr`* and expect these methods to uphold the pinning invariants. Moreover, by calling this method you promise that the reference `Ptr` dereferences to will not be moved out of again; in particular, it must not be possible to obtain a `&mut Ptr::Target` and then move out of that reference (using, for example [`mem::swap`]). For example, calling `Pin::new_unchecked` on an `&'a mut T` is unsafe because while you are able to pin it for the given lifetime `'a`, you have no control over whether it is kept pinned once `'a` ends, and therefore cannot uphold the guarantee that a value, once pinned, remains pinned until it is dropped: ``` use std::mem; use std::pin::Pin; fn move_pinned_ref<T>(mut a: T, mut b: T) { unsafe { let p: Pin<&mut T> = Pin::new_unchecked(&mut a); // This should mean the pointee `a` can never move again. } mem::swap(&mut a, &mut b); // Potential UB down the road ⚠️ // The address of `a` changed to `b`'s stack slot, so `a` got moved even // though we have previously pinned it! We have violated the pinning API contract. } ``` A value, once pinned, must remain pinned until it is dropped (unless its type implements `Unpin`). Because `Pin<&mut T>` does not own the value, dropping the `Pin` will not drop the value and will not end the pinning contract. So moving the value after dropping the `Pin<&mut T>` is still a violation of the API contract. Similarly, calling `Pin::new_unchecked` on an `Rc<T>` is unsafe because there could be aliases to the same data that are not subject to the pinning restrictions: ``` use std::rc::Rc; use std::pin::Pin; fn move_pinned_rc<T>(mut x: Rc<T>) { // This should mean the pointee can never move again. let pin = unsafe { Pin::new_unchecked(Rc::clone(&x)) }; { let p: Pin<&T> = pin.as_ref(); // ... } drop(pin); let content = Rc::get_mut(&mut x).unwrap(); // Potential UB down the road ⚠️ // Now, if `x` was the only reference, we have a mutable reference to // data that we pinned above, which we could use to move it as we have // seen in the previous example. We have violated the pinning API contract. } ``` | |
| 5331 | core::pointer | add | function | If any of the following conditions are violated, the result is Undefined Behavior: * The offset in bytes, `count * size_of::<T>()`, computed on mathematical integers (without "wrapping around"), must fit in an `isize`. * Let `result` be `self.addr() + count * size_of::<T>()`, computed on mathematical integers. This must fit in a `usize`. * If the computed offset is non-zero, then `self` must be [derived from][crate::ptr#provenance] a pointer to some [allocation], and the entire memory range between `self` and `result` (i.e., `self.addr()..result`) must be in bounds of that allocation. Allocations can never be larger than `isize::MAX` bytes and they can only contain addresses representable by `usize`, so technically the last condition implies the first two. This implies, for instance, that `vec.as_ptr().add(vec.len())` (for `vec: Vec<T>`) is always safe. [allocation]: crate::ptr#allocation Consider using [`wrapping_add`](#method.wrapping_add) instead if these constraints are difficult to satisfy. The only advantage of this method is that it enables more aggressive compiler optimizations. | |
| 5332 | core::pointer | as_mut | function | When calling this method, you have to ensure that *either* the pointer is null *or* the pointer is [convertible to a reference](crate::ptr#pointer-to-reference-conversion). | |
| 5333 | core::pointer | as_mut_unchecked | function | When calling this method, you have to ensure that the pointer is [convertible to a reference](crate::ptr#pointer-to-reference-conversion). | |
| 5334 | core::pointer | as_ref | function | When calling this method, you have to ensure that *either* the pointer is null *or* the pointer is [convertible to a reference](crate::ptr#pointer-to-reference-conversion). | |
| 5335 | core::pointer | as_ref_unchecked | function | When calling this method, you have to ensure that the pointer is [convertible to a reference](crate::ptr#pointer-to-reference-conversion). | |
| 5336 | core::pointer | as_uninit_mut | function | When calling this method, you have to ensure that *either* the pointer is null *or* the pointer is [convertible to a reference](crate::ptr#pointer-to-reference-conversion). | |
| 5337 | core::pointer | as_uninit_ref | function | When calling this method, you have to ensure that *either* the pointer is null *or* the pointer is [convertible to a reference](crate::ptr#pointer-to-reference-conversion). Note that because the created reference is to `MaybeUninit<T>`, the source pointer can point to uninitialized memory. | |
| 5338 | core::pointer | as_uninit_slice | function | When calling this method, you have to ensure that *either* the pointer is null *or* all of the following is true: * The pointer must be [valid] for reads for `ptr.len() * size_of::<T>()` many bytes, and it must be properly aligned. This means in particular: * The entire memory range of this slice must be contained within a single [allocation]! Slices can never span across multiple allocations. * The pointer must be aligned even for zero-length slices. One reason for this is that enum layout optimizations may rely on references (including slices of any length) being aligned and non-null to distinguish them from other data. You can obtain a pointer that is usable as `data` for zero-length slices using [`NonNull::dangling()`]. * The total size `ptr.len() * size_of::<T>()` of the slice must be no larger than `isize::MAX`. See the safety documentation of [`pointer::offset`]. * You must enforce Rust's aliasing rules, since the returned lifetime `'a` is arbitrarily chosen and does not necessarily reflect the actual lifetime of the data. In particular, while this reference exists, the memory the pointer points to must not get mutated (except inside `UnsafeCell`). This applies even if the result of this method is unused! See also [`slice::from_raw_parts`][]. [valid]: crate::ptr#safety [allocation]: crate::ptr#allocation | |
| 5339 | core::pointer | as_uninit_slice_mut | function | When calling this method, you have to ensure that *either* the pointer is null *or* all of the following is true: * The pointer must be [valid] for reads and writes for `ptr.len() * size_of::<T>()` many bytes, and it must be properly aligned. This means in particular: * The entire memory range of this slice must be contained within a single [allocation]! Slices can never span across multiple allocations. * The pointer must be aligned even for zero-length slices. One reason for this is that enum layout optimizations may rely on references (including slices of any length) being aligned and non-null to distinguish them from other data. You can obtain a pointer that is usable as `data` for zero-length slices using [`NonNull::dangling()`]. * The total size `ptr.len() * size_of::<T>()` of the slice must be no larger than `isize::MAX`. See the safety documentation of [`pointer::offset`]. * You must enforce Rust's aliasing rules, since the returned lifetime `'a` is arbitrarily chosen and does not necessarily reflect the actual lifetime of the data. In particular, while this reference exists, the memory the pointer points to must not get accessed (read or written) through any other pointer. This applies even if the result of this method is unused! See also [`slice::from_raw_parts_mut`][]. [valid]: crate::ptr#safety [allocation]: crate::ptr#allocation | |
| 5340 | core::pointer | byte_add | function | ||
| 5341 | core::pointer | byte_offset | function | ||
| 5342 | core::pointer | byte_offset_from | function | ||
| 5343 | core::pointer | byte_offset_from_unsigned | function | ||
| 5344 | core::pointer | byte_sub | function | ||
| 5345 | core::pointer | copy_from | function | ||
| 5346 | core::pointer | copy_from_nonoverlapping | function | ||
| 5347 | core::pointer | copy_to | function | ||
| 5348 | core::pointer | copy_to_nonoverlapping | function | ||
| 5349 | core::pointer | drop_in_place | function | ||
| 5350 | core::pointer | get_unchecked | function | ||
| 5351 | core::pointer | get_unchecked_mut | function | ||
| 5352 | core::pointer | offset | function | If any of the following conditions are violated, the result is Undefined Behavior: * The offset in bytes, `count * size_of::<T>()`, computed on mathematical integers (without "wrapping around"), must fit in an `isize`. * Let `result` be `self.addr() + count * size_of::<T>()`, computed on mathematical integers. This must fit in a `usize`. * If the computed offset is non-zero, then `self` must be [derived from][crate::ptr#provenance] a pointer to some [allocation], and the entire memory range between `self` and `result` (i.e., `min(self.addr(), result)..max(self.addr(), result)`) must be in bounds of that allocation. Allocations can never be larger than `isize::MAX` bytes and they can only contain addresses representable by `usize`, so technically the last condition implies the first two. This implies, for instance, that `vec.as_ptr().offset(vec.len() as isize)` (for `vec: Vec<T>`) is always safe. [allocation]: crate::ptr#allocation Consider using [`wrapping_offset`](#method.wrapping_offset) instead if these constraints are difficult to satisfy. The only advantage of this method is that it enables more aggressive compiler optimizations. | |
| 5353 | core::pointer | offset_from | function | If any of the following conditions are violated, the result is Undefined Behavior: * `self` and `origin` must either * point to the same address, or * both be [derived from][crate::ptr#provenance] a pointer to the same [allocation], and the memory range between the two pointers must be in bounds of that object. (See below for an example.) * The distance between the pointers, in bytes, must be an exact multiple of the size of `T`. As a consequence, the absolute distance between the pointers, in bytes, computed on mathematical integers (without "wrapping around"), cannot overflow an `isize`. This is implied by the in-bounds requirement, and the fact that no allocation can be larger than `isize::MAX` bytes. The requirement for pointers to be derived from the same allocation is primarily needed for `const`-compatibility: the distance between pointers into *different* allocated objects is not known at compile-time. However, the requirement also exists at runtime and may be exploited by optimizations. If you wish to compute the difference between pointers that are not guaranteed to be from the same allocation, use `(self as isize - origin as isize) / size_of::<T>()`. [`add`]: #method.add [allocation]: crate::ptr#allocation | |
| 5354 | core::pointer | offset_from_unsigned | function | - The distance between the pointers must be non-negative (`self >= origin`) - *All* the safety conditions of [`offset_from`](#method.offset_from) apply to this method as well; see it for the full details. Importantly, despite the return type of this method being able to represent a larger offset, it's still *not permitted* to pass pointers which differ by more than `isize::MAX` *bytes*. As such, the result of this method will always be less than or equal to `isize::MAX as usize`. | |
| 5355 | core::pointer | read | function | ||
| 5356 | core::pointer | read_unaligned | function | ||
| 5357 | core::pointer | read_volatile | function | ||
| 5358 | core::pointer | replace | function | ||
| 5359 | core::pointer | split_at_mut | function | `mid` must be [in-bounds] of the underlying [allocation]. Which means `self` must be dereferenceable and span a single allocation that is at least `mid * size_of::<T>()` bytes long. Not upholding these requirements is *[undefined behavior]* even if the resulting pointers are not used. Since `len` being in-bounds is not a safety invariant of `*mut [T]` the safety requirements of this method are the same as for [`split_at_mut_unchecked`]. The explicit bounds check is only as useful as `len` is correct. [`split_at_mut_unchecked`]: #method.split_at_mut_unchecked [in-bounds]: #method.add [allocation]: crate::ptr#allocation [undefined behavior]: https://doc.rust-lang.org/reference/behavior-considered-undefined.html | |
| 5360 | core::pointer | split_at_mut_unchecked | function | `mid` must be [in-bounds] of the underlying [allocation]. Which means `self` must be dereferenceable and span a single allocation that is at least `mid * size_of::<T>()` bytes long. Not upholding these requirements is *[undefined behavior]* even if the resulting pointers are not used. [in-bounds]: #method.add [out-of-bounds index]: #method.add [allocation]: crate::ptr#allocation [undefined behavior]: https://doc.rust-lang.org/reference/behavior-considered-undefined.html | |
| 5361 | core::pointer | sub | function | If any of the following conditions are violated, the result is Undefined Behavior: * The offset in bytes, `count * size_of::<T>()`, computed on mathematical integers (without "wrapping around"), must fit in an `isize`. * Let `result` be `self.addr() - count * size_of::<T>()`, computed on mathematical integers. This must fit in a `usize`. * If the computed offset is non-zero, then `self` must be [derived from][crate::ptr#provenance] a pointer to some [allocation], and the entire memory range between `self` and `result` (i.e., `result..self.addr()`) must be in bounds of that allocation. Allocations can never be larger than `isize::MAX` bytes and they can only contain addresses representable by `usize`, so technically the last condition implies the first two. [allocation]: crate::ptr#allocation Consider using [`wrapping_sub`](#method.wrapping_sub) instead if these constraints are difficult to satisfy. The only advantage of this method is that it enables more aggressive compiler optimizations. | |
| 5362 | core::pointer | swap | function | ||
| 5363 | core::pointer | write | function | ||
| 5364 | core::pointer | write_bytes | function | ||
| 5365 | core::pointer | write_unaligned | function | ||
| 5366 | core::pointer | write_volatile | function | ||
| 5367 | core::prelude::v1 | Send | trait | ||
| 5368 | core::prelude::v1 | Sync | trait | ||
| 5369 | core::ptr | copy | function | Behavior is undefined if any of the following conditions are violated: * `src` must be [valid] for reads of `count * size_of::<T>()` bytes or that number must be 0. * `dst` must be [valid] for writes of `count * size_of::<T>()` bytes or that number must be 0, and `dst` must remain valid even when `src` is read for `count * size_of::<T>()` bytes. (This means if the memory ranges overlap, the `dst` pointer must not be invalidated by `src` reads.) * Both `src` and `dst` must be properly aligned. Like [`read`], `copy` creates a bitwise copy of `T`, regardless of whether `T` is [`Copy`]. If `T` is not [`Copy`], using both the values in the region beginning at `*src` and the region beginning at `*dst` can [violate memory safety][read-ownership]. Note that even if the effectively copied size (`count * size_of::<T>()`) is `0`, the pointers must be properly aligned. [`read`]: crate::ptr::read [read-ownership]: crate::ptr::read#ownership-of-the-returned-value [valid]: crate::ptr#safety | |
| 5370 | core::ptr | copy_nonoverlapping | function | Behavior is undefined if any of the following conditions are violated: * `src` must be [valid] for reads of `count * size_of::<T>()` bytes or that number must be 0. * `dst` must be [valid] for writes of `count * size_of::<T>()` bytes or that number must be 0. * Both `src` and `dst` must be properly aligned. * The region of memory beginning at `src` with a size of `count * size_of::<T>()` bytes must *not* overlap with the region of memory beginning at `dst` with the same size. Like [`read`], `copy_nonoverlapping` creates a bitwise copy of `T`, regardless of whether `T` is [`Copy`]. If `T` is not [`Copy`], using *both* the values in the region beginning at `*src` and the region beginning at `*dst` can [violate memory safety][read-ownership]. Note that even if the effectively copied size (`count * size_of::<T>()`) is `0`, the pointers must be properly aligned. [`read`]: crate::ptr::read [read-ownership]: crate::ptr::read#ownership-of-the-returned-value [valid]: crate::ptr#safety | |
| 5371 | core::ptr | drop_in_place | function | Behavior is undefined if any of the following conditions are violated: * `to_drop` must be [valid] for both reads and writes. * `to_drop` must be properly aligned, even if `T` has size 0. * `to_drop` must be nonnull, even if `T` has size 0. * The value `to_drop` points to must be valid for dropping, which may mean it must uphold additional invariants. These invariants depend on the type of the value being dropped. For instance, when dropping a Box, the box's pointer to the heap must be valid. * While `drop_in_place` is executing, the only way to access parts of `to_drop` is through the `&mut self` references supplied to the `Drop::drop` methods that `drop_in_place` invokes. Additionally, if `T` is not [`Copy`], using the pointed-to value after calling `drop_in_place` can cause undefined behavior. Note that `*to_drop = foo` counts as a use because it will cause the value to be dropped again. [`write()`] can be used to overwrite data without causing it to be dropped. [valid]: self#safety | |
| 5372 | core::ptr | read | function | Behavior is undefined if any of the following conditions are violated: * `src` must be [valid] for reads or `T` must be a ZST. * `src` must be properly aligned. Use [`read_unaligned`] if this is not the case. * `src` must point to a properly initialized value of type `T`. Note that even if `T` has size `0`, the pointer must be properly aligned. | |
| 5373 | core::ptr | read_unaligned | function | Behavior is undefined if any of the following conditions are violated: * `src` must be [valid] for reads. * `src` must point to a properly initialized value of type `T`. Like [`read`], `read_unaligned` creates a bitwise copy of `T`, regardless of whether `T` is [`Copy`]. If `T` is not [`Copy`], using both the returned value and the value at `*src` can [violate memory safety][read-ownership]. [read-ownership]: read#ownership-of-the-returned-value [valid]: self#safety | |
| 5374 | core::ptr | read_volatile | function | Like [`read`], `read_volatile` creates a bitwise copy of `T`, regardless of whether `T` is [`Copy`]. If `T` is not [`Copy`], using both the returned value and the value at `*src` can [violate memory safety][read-ownership]. However, storing non-[`Copy`] types in volatile memory is almost certainly incorrect. Behavior is undefined if any of the following conditions are violated: * `src` must be either [valid] for reads, or `T` must be a ZST, or `src` must point to memory outside of all Rust allocations and reading from that memory must: - not trap, and - not cause any memory inside a Rust allocation to be modified. * `src` must be properly aligned. * Reading from `src` must produce a properly initialized value of type `T`. Note that even if `T` has size `0`, the pointer must be properly aligned. [valid]: self#safety [read-ownership]: read#ownership-of-the-returned-value | |
| 5375 | core::ptr | replace | function | Behavior is undefined if any of the following conditions are violated: * `dst` must be [valid] for both reads and writes or `T` must be a ZST. * `dst` must be properly aligned. * `dst` must point to a properly initialized value of type `T`. Note that even if `T` has size `0`, the pointer must be properly aligned. [valid]: self#safety | |
| 5376 | core::ptr | swap | function | Behavior is undefined if any of the following conditions are violated: * Both `x` and `y` must be [valid] for both reads and writes. They must remain valid even when the other pointer is written. (This means if the memory ranges overlap, the two pointers must not be subject to aliasing restrictions relative to each other.) * Both `x` and `y` must be properly aligned. Note that even if `T` has size `0`, the pointers must be properly aligned. [valid]: self#safety | |
| 5377 | core::ptr | swap_nonoverlapping | function | Behavior is undefined if any of the following conditions are violated: * Both `x` and `y` must be [valid] for both reads and writes of `count * size_of::<T>()` bytes. * Both `x` and `y` must be properly aligned. * The region of memory beginning at `x` with a size of `count * size_of::<T>()` bytes must *not* overlap with the region of memory beginning at `y` with the same size. Note that even if the effectively copied size (`count * size_of::<T>()`) is `0`, the pointers must be properly aligned. [valid]: self#safety | |
| 5378 | core::ptr | write | function | Behavior is undefined if any of the following conditions are violated: * `dst` must be [valid] for writes or `T` must be a ZST. * `dst` must be properly aligned. Use [`write_unaligned`] if this is not the case. Note that even if `T` has size `0`, the pointer must be properly aligned. [valid]: self#safety | |
| 5379 | core::ptr | write_bytes | function | Behavior is undefined if any of the following conditions are violated: * `dst` must be [valid] for writes of `count * size_of::<T>()` bytes. * `dst` must be properly aligned. Note that even if the effectively copied size (`count * size_of::<T>()`) is `0`, the pointer must be properly aligned. Additionally, note that changing `*dst` in this way can easily lead to undefined behavior (UB) later if the written bytes are not a valid representation of some `T`. For instance, the following is an **incorrect** use of this function: ```rust,no_run unsafe { let mut value: u8 = 0; let ptr: *mut bool = &mut value as *mut u8 as *mut bool; let _bool = ptr.read(); // This is fine, `ptr` points to a valid `bool`. ptr.write_bytes(42u8, 1); // This function itself does not cause UB... let _bool = ptr.read(); // ...but it makes this operation UB! ⚠️ } ``` [valid]: crate::ptr#safety | |
| 5380 | core::ptr | write_unaligned | function | Behavior is undefined if any of the following conditions are violated: * `dst` must be [valid] for writes. [valid]: self#safety | |
| 5381 | core::ptr | write_volatile | function | Behavior is undefined if any of the following conditions are violated: * `dst` must be either [valid] for writes, or `T` must be a ZST, or `dst` must point to memory outside of all Rust allocations and writing to that memory must: - not trap, and - not cause any memory inside a Rust allocation to be modified. * `dst` must be properly aligned. Note that even if `T` has size `0`, the pointer must be properly aligned. [valid]: self#safety | |
| 5382 | core::ptr::non_null::NonNull | add | function | If any of the following conditions are violated, the result is Undefined Behavior: * The offset in bytes, `count * size_of::<T>()`, computed on mathematical integers (without "wrapping around"), must fit in an `isize`. * Let `result` be `self.addr() + count * size_of::<T>()`, computed on mathematical integers. This must fit in a `usize`. * If the computed offset is non-zero, then `self` must be [derived from][crate::ptr#provenance] a pointer to some [allocation], and the entire memory range between `self` and `result` (i.e., `self.addr()..result`) must be in bounds of that allocation. Allocations can never be larger than `isize::MAX` bytes and they can only contain addresses representable by `usize`, so technically the last condition implies the first two. This implies, for instance, that `vec.as_ptr().add(vec.len())` (for `vec: Vec<T>`) is always safe. [allocation]: crate::ptr#allocation | |
| 5383 | core::ptr::non_null::NonNull | as_mut | function | When calling this method, you have to ensure that the pointer is [convertible to a reference](crate::ptr#pointer-to-reference-conversion). | |
| 5384 | core::ptr::non_null::NonNull | as_ref | function | When calling this method, you have to ensure that the pointer is [convertible to a reference](crate::ptr#pointer-to-reference-conversion). | |
| 5385 | core::ptr::non_null::NonNull | as_uninit_mut | function | When calling this method, you have to ensure that the pointer is [convertible to a reference](crate::ptr#pointer-to-reference-conversion). Note that because the created reference is to `MaybeUninit<T>`, the source pointer can point to uninitialized memory. | |
| 5386 | core::ptr::non_null::NonNull | as_uninit_ref | function | When calling this method, you have to ensure that the pointer is [convertible to a reference](crate::ptr#pointer-to-reference-conversion). Note that because the created reference is to `MaybeUninit<T>`, the source pointer can point to uninitialized memory. | |
| 5387 | core::ptr::non_null::NonNull | as_uninit_slice | function | When calling this method, you have to ensure that all of the following is true: * The pointer must be [valid] for reads for `ptr.len() * size_of::<T>()` many bytes, and it must be properly aligned. This means in particular: * The entire memory range of this slice must be contained within a single allocation! Slices can never span across multiple allocations. * The pointer must be aligned even for zero-length slices. One reason for this is that enum layout optimizations may rely on references (including slices of any length) being aligned and non-null to distinguish them from other data. You can obtain a pointer that is usable as `data` for zero-length slices using [`NonNull::dangling()`]. * The total size `ptr.len() * size_of::<T>()` of the slice must be no larger than `isize::MAX`. See the safety documentation of [`pointer::offset`]. * You must enforce Rust's aliasing rules, since the returned lifetime `'a` is arbitrarily chosen and does not necessarily reflect the actual lifetime of the data. In particular, while this reference exists, the memory the pointer points to must not get mutated (except inside `UnsafeCell`). This applies even if the result of this method is unused! See also [`slice::from_raw_parts`]. [valid]: crate::ptr#safety | |
| 5388 | core::ptr::non_null::NonNull | as_uninit_slice_mut | function | When calling this method, you have to ensure that all of the following is true: * The pointer must be [valid] for reads and writes for `ptr.len() * size_of::<T>()` many bytes, and it must be properly aligned. This means in particular: * The entire memory range of this slice must be contained within a single allocation! Slices can never span across multiple allocations. * The pointer must be aligned even for zero-length slices. One reason for this is that enum layout optimizations may rely on references (including slices of any length) being aligned and non-null to distinguish them from other data. You can obtain a pointer that is usable as `data` for zero-length slices using [`NonNull::dangling()`]. * The total size `ptr.len() * size_of::<T>()` of the slice must be no larger than `isize::MAX`. See the safety documentation of [`pointer::offset`]. * You must enforce Rust's aliasing rules, since the returned lifetime `'a` is arbitrarily chosen and does not necessarily reflect the actual lifetime of the data. In particular, while this reference exists, the memory the pointer points to must not get accessed (read or written) through any other pointer. This applies even if the result of this method is unused! See also [`slice::from_raw_parts_mut`]. [valid]: crate::ptr#safety | |
| 5389 | core::ptr::non_null::NonNull | byte_add | function | ||
| 5390 | core::ptr::non_null::NonNull | byte_offset | function | ||
| 5391 | core::ptr::non_null::NonNull | byte_offset_from | function | ||
| 5392 | core::ptr::non_null::NonNull | byte_offset_from_unsigned | function | ||
| 5393 | core::ptr::non_null::NonNull | byte_sub | function | ||
| 5394 | core::ptr::non_null::NonNull | copy_from | function | ||
| 5395 | core::ptr::non_null::NonNull | copy_from_nonoverlapping | function | ||
| 5396 | core::ptr::non_null::NonNull | copy_to | function | ||
| 5397 | core::ptr::non_null::NonNull | copy_to_nonoverlapping | function | ||
| 5398 | core::ptr::non_null::NonNull | drop_in_place | function | ||
| 5399 | core::ptr::non_null::NonNull | get_unchecked_mut | function | ||
| 5400 | core::ptr::non_null::NonNull | new_unchecked | function | `ptr` must be non-null. | |
| 5401 | core::ptr::non_null::NonNull | offset | function | If any of the following conditions are violated, the result is Undefined Behavior: * The offset in bytes, `count * size_of::<T>()`, computed on mathematical integers (without "wrapping around"), must fit in an `isize`. * Let `result` be `self.addr() + count * size_of::<T>()`, computed on mathematical integers. This must fit in a `usize`. * If the computed offset is non-zero, then `self` must be [derived from][crate::ptr#provenance] a pointer to some [allocation], and the entire memory range between `self` and `result` (i.e., `min(self.addr(), result)..max(self.addr(), result)`) must be in bounds of that allocation. Allocations can never be larger than `isize::MAX` bytes and they can only contain addresses representable by `usize`, so technically the last condition implies the first two. This implies, for instance, that `vec.as_ptr().offset(vec.len() as isize)` (for `vec: Vec<T>`) is always safe. [allocation]: crate::ptr#allocation | |
| 5402 | core::ptr::non_null::NonNull | offset_from | function | If any of the following conditions are violated, the result is Undefined Behavior: * `self` and `origin` must either * point to the same address, or * both be *derived from* a pointer to the same [allocation], and the memory range between the two pointers must be in bounds of that object. (See below for an example.) * The distance between the pointers, in bytes, must be an exact multiple of the size of `T`. As a consequence, the absolute distance between the pointers, in bytes, computed on mathematical integers (without "wrapping around"), cannot overflow an `isize`. This is implied by the in-bounds requirement, and the fact that no allocation can be larger than `isize::MAX` bytes. The requirement for pointers to be derived from the same allocation is primarily needed for `const`-compatibility: the distance between pointers into *different* allocated objects is not known at compile-time. However, the requirement also exists at runtime and may be exploited by optimizations. If you wish to compute the difference between pointers that are not guaranteed to be from the same allocation, use `(self as isize - origin as isize) / size_of::<T>()`. [`add`]: #method.add [allocation]: crate::ptr#allocation | |
| 5403 | core::ptr::non_null::NonNull | offset_from_unsigned | function | - The distance between the pointers must be non-negative (`self >= origin`) - *All* the safety conditions of [`offset_from`](#method.offset_from) apply to this method as well; see it for the full details. Importantly, despite the return type of this method being able to represent a larger offset, it's still *not permitted* to pass pointers which differ by more than `isize::MAX` *bytes*. As such, the result of this method will always be less than or equal to `isize::MAX as usize`. | |
| 5404 | core::ptr::non_null::NonNull | read | function | ||
| 5405 | core::ptr::non_null::NonNull | read_unaligned | function | ||
| 5406 | core::ptr::non_null::NonNull | read_volatile | function | ||
| 5407 | core::ptr::non_null::NonNull | replace | function | ||
| 5408 | core::ptr::non_null::NonNull | sub | function | If any of the following conditions are violated, the result is Undefined Behavior: * The offset in bytes, `count * size_of::<T>()`, computed on mathematical integers (without "wrapping around"), must fit in an `isize`. * Let `result` be `self.addr() - count * size_of::<T>()`, computed on mathematical integers. This must fit in a `usize`. * If the computed offset is non-zero, then `self` must be [derived from][crate::ptr#provenance] a pointer to some [allocation], and the entire memory range between `self` and `result` (i.e., `result..self.addr()`) must be in bounds of that allocation. Allocations can never be larger than `isize::MAX` bytes and they can only contain addresses representable by `usize`, so technically the last condition implies the first two. [allocation]: crate::ptr#allocation | |
| 5409 | core::ptr::non_null::NonNull | swap | function | ||
| 5410 | core::ptr::non_null::NonNull | write | function | ||
| 5411 | core::ptr::non_null::NonNull | write_bytes | function | ||
| 5412 | core::ptr::non_null::NonNull | write_unaligned | function | ||
| 5413 | core::ptr::non_null::NonNull | write_volatile | function | ||
| 5414 | core::result::Result | unwrap_err_unchecked | function | Calling this method on an [`Ok`] is *[undefined behavior]*. [undefined behavior]: https://doc.rust-lang.org/reference/behavior-considered-undefined.html | |
| 5415 | core::result::Result | unwrap_unchecked | function | Calling this method on an [`Err`] is *[undefined behavior]*. [undefined behavior]: https://doc.rust-lang.org/reference/behavior-considered-undefined.html | |
| 5416 | core::slice | GetDisjointMutIndex | trait | If `is_in_bounds()` returns `true` and `is_overlapping()` returns `false`, it must be safe to index the slice with the indices. | |
| 5417 | core::slice | SliceIndex | trait | ||
| 5418 | core::slice | align_to | function | This method is essentially a `transmute` with respect to the elements in the returned middle slice, so all the usual caveats pertaining to `transmute::<T, U>` also apply here. | |
| 5419 | core::slice | align_to_mut | function | This method is essentially a `transmute` with respect to the elements in the returned middle slice, so all the usual caveats pertaining to `transmute::<T, U>` also apply here. | |
| 5420 | core::slice | as_ascii_unchecked | function | Every byte in the slice must be in `0..=127`, or else this is UB. | |
| 5421 | core::slice | as_chunks_unchecked | function | This may only be called when - The slice splits exactly into `N`-element chunks (aka `self.len() % N == 0`). - `N != 0`. | |
| 5422 | core::slice | as_chunks_unchecked_mut | function | This may only be called when - The slice splits exactly into `N`-element chunks (aka `self.len() % N == 0`). - `N != 0`. | |
| 5423 | core::slice | assume_init_drop | function | It is up to the caller to guarantee that every `MaybeUninit<T>` in the slice really is in an initialized state. Calling this when the content is not yet fully initialized causes undefined behavior. On top of that, all additional invariants of the type `T` must be satisfied, as the `Drop` implementation of `T` (or its members) may rely on this. For example, setting a `Vec<T>` to an invalid but non-null address makes it initialized (under the current implementation; this does not constitute a stable guarantee), because the only requirement the compiler knows about it is that the data pointer must be non-null. Dropping such a `Vec<T>` however will cause undefined behaviour. | |
| 5424 | core::slice | assume_init_mut | function | Calling this when the content is not yet fully initialized causes undefined behavior: it is up to the caller to guarantee that every `MaybeUninit<T>` in the slice really is in an initialized state. For instance, `.assume_init_mut()` cannot be used to initialize a `MaybeUninit` slice. | |
| 5425 | core::slice | assume_init_ref | function | Calling this when the content is not yet fully initialized causes undefined behavior: it is up to the caller to guarantee that every `MaybeUninit<T>` in the slice really is in an initialized state. | |
| 5426 | core::slice | from_mut_ptr_range | function | Behavior is undefined if any of the following conditions are violated: * The `start` pointer of the range must be a non-null, [valid] and properly aligned pointer to the first element of a slice. * The `end` pointer must be a [valid] and properly aligned pointer to *one past* the last element, such that the offset from the end to the start pointer is the length of the slice. * The entire memory range of this slice must be contained within a single allocation! Slices can never span across multiple allocations. * The range must contain `N` consecutive properly initialized values of type `T`. * The memory referenced by the returned slice must not be accessed through any other pointer (not derived from the return value) for the duration of lifetime `'a`. Both read and write accesses are forbidden. * The total length of the range must be no larger than `isize::MAX`, and adding that size to `start` must not "wrap around" the address space. See the safety documentation of [`pointer::offset`]. Note that a range created from [`slice::as_mut_ptr_range`] fulfills these requirements. | |
| 5427 | core::slice | from_ptr_range | function | Behavior is undefined if any of the following conditions are violated: * The `start` pointer of the range must be a non-null, [valid] and properly aligned pointer to the first element of a slice. * The `end` pointer must be a [valid] and properly aligned pointer to *one past* the last element, such that the offset from the end to the start pointer is the length of the slice. * The entire memory range of this slice must be contained within a single allocation! Slices can never span across multiple allocations. * The range must contain `N` consecutive properly initialized values of type `T`. * The memory referenced by the returned slice must not be mutated for the duration of lifetime `'a`, except inside an `UnsafeCell`. * The total length of the range must be no larger than `isize::MAX`, and adding that size to `start` must not "wrap around" the address space. See the safety documentation of [`pointer::offset`]. Note that a range created from [`slice::as_ptr_range`] fulfills these requirements. | |
| 5428 | core::slice | from_raw_parts | function | Behavior is undefined if any of the following conditions are violated: * `data` must be non-null, [valid] for reads for `len * size_of::<T>()` many bytes, and it must be properly aligned. This means in particular: * The entire memory range of this slice must be contained within a single allocation! Slices can never span across multiple allocations. See [below](#incorrect-usage) for an example incorrectly not taking this into account. * `data` must be non-null and aligned even for zero-length slices or slices of ZSTs. One reason for this is that enum layout optimizations may rely on references (including slices of any length) being aligned and non-null to distinguish them from other data. You can obtain a pointer that is usable as `data` for zero-length slices using [`NonNull::dangling()`]. * `data` must point to `len` consecutive properly initialized values of type `T`. * The memory referenced by the returned slice must not be mutated for the duration of lifetime `'a`, except inside an `UnsafeCell`. * The total size `len * size_of::<T>()` of the slice must be no larger than `isize::MAX`, and adding that size to `data` must not "wrap around" the address space. See the safety documentation of [`pointer::offset`]. | |
| 5429 | core::slice | from_raw_parts_mut | function | Behavior is undefined if any of the following conditions are violated: * `data` must be non-null, [valid] for both reads and writes for `len * size_of::<T>()` many bytes, and it must be properly aligned. This means in particular: * The entire memory range of this slice must be contained within a single allocation! Slices can never span across multiple allocations. * `data` must be non-null and aligned even for zero-length slices or slices of ZSTs. One reason for this is that enum layout optimizations may rely on references (including slices of any length) being aligned and non-null to distinguish them from other data. You can obtain a pointer that is usable as `data` for zero-length slices using [`NonNull::dangling()`]. * `data` must point to `len` consecutive properly initialized values of type `T`. * The memory referenced by the returned slice must not be accessed through any other pointer (not derived from the return value) for the duration of lifetime `'a`. Both read and write accesses are forbidden. * The total size `len * size_of::<T>()` of the slice must be no larger than `isize::MAX`, and adding that size to `data` must not "wrap around" the address space. See the safety documentation of [`pointer::offset`]. [valid]: ptr#safety [`NonNull::dangling()`]: ptr::NonNull::dangling | |
| 5430 | core::slice | get_disjoint_unchecked_mut | function | Calling this method with overlapping or out-of-bounds indices is *[undefined behavior]* even if the resulting references are not used. | |
| 5431 | core::slice | get_unchecked | function | Calling this method with an out-of-bounds index is *[undefined behavior]* even if the resulting reference is not used. You can think of this like `.get(index).unwrap_unchecked()`. It's UB to call `.get_unchecked(len)`, even if you immediately convert to a pointer. And it's UB to call `.get_unchecked(..len + 1)`, `.get_unchecked(..=len)`, or similar. [`get`]: slice::get [undefined behavior]: https://doc.rust-lang.org/reference/behavior-considered-undefined.html | |
| 5432 | core::slice | get_unchecked_mut | function | Calling this method with an out-of-bounds index is *[undefined behavior]* even if the resulting reference is not used. You can think of this like `.get_mut(index).unwrap_unchecked()`. It's UB to call `.get_unchecked_mut(len)`, even if you immediately convert to a pointer. And it's UB to call `.get_unchecked_mut(..len + 1)`, `.get_unchecked_mut(..=len)`, or similar. [`get_mut`]: slice::get_mut [undefined behavior]: https://doc.rust-lang.org/reference/behavior-considered-undefined.html | |
| 5433 | core::slice | split_at_mut_unchecked | function | Calling this method with an out-of-bounds index is *[undefined behavior]* even if the resulting reference is not used. The caller has to ensure that `0 <= mid <= self.len()`. [`split_at_mut`]: slice::split_at_mut [undefined behavior]: https://doc.rust-lang.org/reference/behavior-considered-undefined.html | |
| 5434 | core::slice | split_at_unchecked | function | Calling this method with an out-of-bounds index is *[undefined behavior]* even if the resulting reference is not used. The caller has to ensure that `0 <= mid <= self.len()`. [`split_at`]: slice::split_at [undefined behavior]: https://doc.rust-lang.org/reference/behavior-considered-undefined.html | |
| 5435 | core::slice | swap_unchecked | function | Calling this method with an out-of-bounds index is *[undefined behavior]*. The caller has to ensure that `a < self.len()` and `b < self.len()`. | |
| 5436 | core::str | as_ascii_unchecked | function | Every character in this string must be ASCII, or else this is UB. | |
| 5437 | core::str | as_bytes_mut | function | The caller must ensure that the content of the slice is valid UTF-8 before the borrow ends and the underlying `str` is used. Use of a `str` whose contents are not valid UTF-8 is undefined behavior. | |
| 5438 | core::str | from_raw_parts | function | ||
| 5439 | core::str | from_raw_parts_mut | function | ||
| 5440 | core::str | from_utf8_unchecked | function | The bytes passed in must be valid UTF-8. | |
| 5441 | core::str | from_utf8_unchecked_mut | function | ||
| 5442 | core::str | get_unchecked | function | Callers of this function are responsible that these preconditions are satisfied: * The starting index must not exceed the ending index; * Indexes must be within bounds of the original slice; * Indexes must lie on UTF-8 sequence boundaries. Failing that, the returned string slice may reference invalid memory or violate the invariants communicated by the `str` type. | |
| 5443 | core::str | get_unchecked_mut | function | Callers of this function are responsible that these preconditions are satisfied: * The starting index must not exceed the ending index; * Indexes must be within bounds of the original slice; * Indexes must lie on UTF-8 sequence boundaries. Failing that, the returned string slice may reference invalid memory or violate the invariants communicated by the `str` type. | |
| 5444 | core::str | next_code_point | function | `bytes` must produce a valid UTF-8-like (UTF-8 or WTF-8) string | |
| 5445 | core::str | slice_mut_unchecked | function | Callers of this function are responsible that three preconditions are satisfied: * `begin` must not exceed `end`. * `begin` and `end` must be byte positions within the string slice. * `begin` and `end` must lie on UTF-8 sequence boundaries. | |
| 5446 | core::str | slice_unchecked | function | Callers of this function are responsible that three preconditions are satisfied: * `begin` must not exceed `end`. * `begin` and `end` must be byte positions within the string slice. * `begin` and `end` must lie on UTF-8 sequence boundaries. | |
| 5447 | core::str::pattern | ReverseSearcher | trait | ||
| 5448 | core::str::pattern | Searcher | trait | ||
| 5449 | core::sync::atomic | AtomicPrimitive | trait | ||
| 5450 | core::sync::atomic::Atomic | from_ptr | function | * `ptr` must be aligned to `align_of::<AtomicU16>()` (note that on some platforms this can be bigger than `align_of::<u16>()`). * `ptr` must be [valid] for both reads and writes for the whole lifetime `'a`. * You must adhere to the [Memory model for atomic accesses]. In particular, it is not allowed to mix conflicting atomic and non-atomic accesses, or atomic accesses of different sizes, without synchronization. [valid]: crate::ptr#safety [Memory model for atomic accesses]: self#memory-model-for-atomic-accesses * `ptr` must be aligned to `align_of::<AtomicI8>()` (note that this is always true, since `align_of::<AtomicI8>() == 1`). * `ptr` must be [valid] for both reads and writes for the whole lifetime `'a`. * You must adhere to the [Memory model for atomic accesses]. In particular, it is not allowed to mix conflicting atomic and non-atomic accesses, or atomic accesses of different sizes, without synchronization. [valid]: crate::ptr#safety [Memory model for atomic accesses]: self#memory-model-for-atomic-accesses * `ptr` must be aligned to `align_of::<AtomicI16>()` (note that on some platforms this can be bigger than `align_of::<i16>()`). * `ptr` must be [valid] for both reads and writes for the whole lifetime `'a`. * You must adhere to the [Memory model for atomic accesses]. In particular, it is not allowed to mix conflicting atomic and non-atomic accesses, or atomic accesses of different sizes, without synchronization. [valid]: crate::ptr#safety [Memory model for atomic accesses]: self#memory-model-for-atomic-accesses * `ptr` must be aligned to `align_of::<AtomicUsize>()` (note that on some platforms this can be bigger than `align_of::<usize>()`). * `ptr` must be [valid] for both reads and writes for the whole lifetime `'a`. * You must adhere to the [Memory model for atomic accesses]. In particular, it is not allowed to mix conflicting atomic and non-atomic accesses, or atomic accesses of different sizes, without synchronization. [valid]: crate::ptr#safety [Memory model for atomic accesses]: self#memory-model-for-atomic-accesses * `ptr` must be aligned to `align_of::<AtomicU8>()` (note that this is always true, since `align_of::<AtomicU8>() == 1`). * `ptr` must be [valid] for both reads and writes for the whole lifetime `'a`. * You must adhere to the [Memory model for atomic accesses]. In particular, it is not allowed to mix conflicting atomic and non-atomic accesses, or atomic accesses of different sizes, without synchronization. [valid]: crate::ptr#safety [Memory model for atomic accesses]: self#memory-model-for-atomic-accesses * `ptr` must be aligned to `align_of::<AtomicIsize>()` (note that on some platforms this can be bigger than `align_of::<isize>()`). * `ptr` must be [valid] for both reads and writes for the whole lifetime `'a`. * You must adhere to the [Memory model for atomic accesses]. In particular, it is not allowed to mix conflicting atomic and non-atomic accesses, or atomic accesses of different sizes, without synchronization. [valid]: crate::ptr#safety [Memory model for atomic accesses]: self#memory-model-for-atomic-accesses * `ptr` must be aligned to `align_of::<AtomicU64>()` (note that on some platforms this can be bigger than `align_of::<u64>()`). * `ptr` must be [valid] for both reads and writes for the whole lifetime `'a`. * You must adhere to the [Memory model for atomic accesses]. In particular, it is not allowed to mix conflicting atomic and non-atomic accesses, or atomic accesses of different sizes, without synchronization. [valid]: crate::ptr#safety [Memory model for atomic accesses]: self#memory-model-for-atomic-accesses * `ptr` must be aligned to `align_of::<AtomicPtr<T>>()` (note that on some platforms this can be bigger than `align_of::<*mut T>()`). * `ptr` must be [valid] for both reads and writes for the whole lifetime `'a`. * You must adhere to the [Memory model for atomic accesses]. In particular, it is not allowed to mix conflicting atomic and non-atomic accesses, or atomic accesses of different sizes, without synchronization. [valid]: crate::ptr#safety [Memory model for atomic accesses]: self#memory-model-for-atomic-accesses * `ptr` must be aligned to `align_of::<AtomicI64>()` (note that on some platforms this can be bigger than `align_of::<i64>()`). * `ptr` must be [valid] for both reads and writes for the whole lifetime `'a`. * You must adhere to the [Memory model for atomic accesses]. In particular, it is not allowed to mix conflicting atomic and non-atomic accesses, or atomic accesses of different sizes, without synchronization. [valid]: crate::ptr#safety [Memory model for atomic accesses]: self#memory-model-for-atomic-accesses * `ptr` must be aligned to `align_of::<AtomicBool>()` (note that this is always true, since `align_of::<AtomicBool>() == 1`). * `ptr` must be [valid] for both reads and writes for the whole lifetime `'a`. * You must adhere to the [Memory model for atomic accesses]. In particular, it is not allowed to mix conflicting atomic and non-atomic accesses, or atomic accesses of different sizes, without synchronization. [valid]: crate::ptr#safety [Memory model for atomic accesses]: self#memory-model-for-atomic-accesses * `ptr` must be aligned to `align_of::<AtomicU32>()` (note that on some platforms this can be bigger than `align_of::<u32>()`). * `ptr` must be [valid] for both reads and writes for the whole lifetime `'a`. * You must adhere to the [Memory model for atomic accesses]. In particular, it is not allowed to mix conflicting atomic and non-atomic accesses, or atomic accesses of different sizes, without synchronization. [valid]: crate::ptr#safety [Memory model for atomic accesses]: self#memory-model-for-atomic-accesses * `ptr` must be aligned to `align_of::<AtomicI32>()` (note that on some platforms this can be bigger than `align_of::<i32>()`). * `ptr` must be [valid] for both reads and writes for the whole lifetime `'a`. * You must adhere to the [Memory model for atomic accesses]. In particular, it is not allowed to mix conflicting atomic and non-atomic accesses, or atomic accesses of different sizes, without synchronization. [valid]: crate::ptr#safety [Memory model for atomic accesses]: self#memory-model-for-atomic-accesses | |
| 5451 | core::task::wake::LocalWaker | from_raw | function | ||
| 5452 | core::task::wake::LocalWaker | new | function | The behavior of the returned `Waker` is undefined if the contract defined in [`RawWakerVTable`]'s documentation is not upheld. | |
| 5453 | core::task::wake::Waker | from_raw | function | The behavior of the returned `Waker` is undefined if the contract defined in [`RawWaker`]'s and [`RawWakerVTable`]'s documentation is not upheld. (Authors wishing to avoid unsafe code may implement the [`Wake`] trait instead, at the cost of a required heap allocation.) [`Wake`]: ../../alloc/task/trait.Wake.html | |
| 5454 | core::task::wake::Waker | new | function | The behavior of the returned `Waker` is undefined if the contract defined in [`RawWakerVTable`]'s documentation is not upheld. (Authors wishing to avoid unsafe code may implement the [`Wake`] trait instead, at the cost of a required heap allocation.) [`Wake`]: ../../alloc/task/trait.Wake.html | |
| 5455 | core::u128 | unchecked_add | function | This results in undefined behavior when `self + rhs > u128::MAX`, i.e. when [`checked_add`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_add`]: u128::checked_add [`wrapping_add`]: u128::wrapping_add | |
| 5456 | core::u128 | unchecked_cast | function | This results in undefined behavior if the integer value of `self` is bigger than `T::MAX`, or smaller than `T::MIN`, where `T` is the target type. | |
| 5457 | core::u128 | unchecked_disjoint_bitor | function | Requires that `(self & other) == 0`, otherwise it's immediate UB. Equivalently, requires that `(self | other) == (self + other)`. | |
| 5458 | core::u128 | unchecked_div_exact | function | This results in undefined behavior when `rhs == 0` or `self % rhs != 0`, i.e. when [`checked_div_exact`](Self::checked_div_exact) would return `None`. | |
| 5459 | core::u128 | unchecked_funnel_shl | function | This results in undefined behavior if `n` is greater than or equal to `u128::BITS`, i.e. when [`funnel_shl`](Self::funnel_shl) would panic. | |
| 5460 | core::u128 | unchecked_funnel_shr | function | This results in undefined behavior if `n` is greater than or equal to `u128::BITS`, i.e. when [`funnel_shr`](Self::funnel_shr) would panic. | |
| 5461 | core::u128 | unchecked_mul | function | This results in undefined behavior when `self * rhs > u128::MAX`, i.e. when [`checked_mul`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_mul`]: u128::checked_mul [`wrapping_mul`]: u128::wrapping_mul | |
| 5462 | core::u128 | unchecked_shl | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shl`] would return `None`. [`checked_shl`]: u128::checked_shl | |
| 5463 | core::u128 | unchecked_shl_exact | function | This results in undefined behavior when `rhs > self.leading_zeros() || rhs >= u128::BITS` i.e. when [`u128::shl_exact`] would return `None`. | |
| 5464 | core::u128 | unchecked_shr | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shr`] would return `None`. [`checked_shr`]: u128::checked_shr | |
| 5465 | core::u128 | unchecked_shr_exact | function | This results in undefined behavior when `rhs > self.trailing_zeros() || rhs >= u128::BITS` i.e. when [`u128::shr_exact`] would return `None`. | |
| 5466 | core::u128 | unchecked_sub | function | This results in undefined behavior when `self - rhs < u128::MIN`, i.e. when [`checked_sub`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_sub`]: u128::checked_sub [`wrapping_sub`]: u128::wrapping_sub | |
| 5467 | core::u16 | unchecked_add | function | This results in undefined behavior when `self + rhs > u16::MAX`, i.e. when [`checked_add`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_add`]: u16::checked_add [`wrapping_add`]: u16::wrapping_add | |
| 5468 | core::u16 | unchecked_cast | function | This results in undefined behavior if the integer value of `self` is bigger than `T::MAX`, or smaller than `T::MIN`, where `T` is the target type. | |
| 5469 | core::u16 | unchecked_disjoint_bitor | function | Requires that `(self & other) == 0`, otherwise it's immediate UB. Equivalently, requires that `(self | other) == (self + other)`. | |
| 5470 | core::u16 | unchecked_div_exact | function | This results in undefined behavior when `rhs == 0` or `self % rhs != 0`, i.e. when [`checked_div_exact`](Self::checked_div_exact) would return `None`. | |
| 5471 | core::u16 | unchecked_funnel_shl | function | This results in undefined behavior if `n` is greater than or equal to `u16::BITS`, i.e. when [`funnel_shl`](Self::funnel_shl) would panic. | |
| 5472 | core::u16 | unchecked_funnel_shr | function | This results in undefined behavior if `n` is greater than or equal to `u16::BITS`, i.e. when [`funnel_shr`](Self::funnel_shr) would panic. | |
| 5473 | core::u16 | unchecked_mul | function | This results in undefined behavior when `self * rhs > u16::MAX`, i.e. when [`checked_mul`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_mul`]: u16::checked_mul [`wrapping_mul`]: u16::wrapping_mul | |
| 5474 | core::u16 | unchecked_shl | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shl`] would return `None`. [`checked_shl`]: u16::checked_shl | |
| 5475 | core::u16 | unchecked_shl_exact | function | This results in undefined behavior when `rhs > self.leading_zeros() || rhs >= u16::BITS` i.e. when [`u16::shl_exact`] would return `None`. | |
| 5476 | core::u16 | unchecked_shr | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shr`] would return `None`. [`checked_shr`]: u16::checked_shr | |
| 5477 | core::u16 | unchecked_shr_exact | function | This results in undefined behavior when `rhs > self.trailing_zeros() || rhs >= u16::BITS` i.e. when [`u16::shr_exact`] would return `None`. | |
| 5478 | core::u16 | unchecked_sub | function | This results in undefined behavior when `self - rhs < u16::MIN`, i.e. when [`checked_sub`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_sub`]: u16::checked_sub [`wrapping_sub`]: u16::wrapping_sub | |
| 5479 | core::u32 | unchecked_add | function | This results in undefined behavior when `self + rhs > u32::MAX`, i.e. when [`checked_add`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_add`]: u32::checked_add [`wrapping_add`]: u32::wrapping_add | |
| 5480 | core::u32 | unchecked_cast | function | This results in undefined behavior if the integer value of `self` is bigger than `T::MAX`, or smaller than `T::MIN`, where `T` is the target type. | |
| 5481 | core::u32 | unchecked_disjoint_bitor | function | Requires that `(self & other) == 0`, otherwise it's immediate UB. Equivalently, requires that `(self | other) == (self + other)`. | |
| 5482 | core::u32 | unchecked_div_exact | function | This results in undefined behavior when `rhs == 0` or `self % rhs != 0`, i.e. when [`checked_div_exact`](Self::checked_div_exact) would return `None`. | |
| 5483 | core::u32 | unchecked_funnel_shl | function | This results in undefined behavior if `n` is greater than or equal to `u32::BITS`, i.e. when [`funnel_shl`](Self::funnel_shl) would panic. | |
| 5484 | core::u32 | unchecked_funnel_shr | function | This results in undefined behavior if `n` is greater than or equal to `u32::BITS`, i.e. when [`funnel_shr`](Self::funnel_shr) would panic. | |
| 5485 | core::u32 | unchecked_mul | function | This results in undefined behavior when `self * rhs > u32::MAX`, i.e. when [`checked_mul`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_mul`]: u32::checked_mul [`wrapping_mul`]: u32::wrapping_mul | |
| 5486 | core::u32 | unchecked_shl | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shl`] would return `None`. [`checked_shl`]: u32::checked_shl | |
| 5487 | core::u32 | unchecked_shl_exact | function | This results in undefined behavior when `rhs > self.leading_zeros() || rhs >= u32::BITS` i.e. when [`u32::shl_exact`] would return `None`. | |
| 5488 | core::u32 | unchecked_shr | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shr`] would return `None`. [`checked_shr`]: u32::checked_shr | |
| 5489 | core::u32 | unchecked_shr_exact | function | This results in undefined behavior when `rhs > self.trailing_zeros() || rhs >= u32::BITS` i.e. when [`u32::shr_exact`] would return `None`. | |
| 5490 | core::u32 | unchecked_sub | function | This results in undefined behavior when `self - rhs < u32::MIN`, i.e. when [`checked_sub`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_sub`]: u32::checked_sub [`wrapping_sub`]: u32::wrapping_sub | |
| 5491 | core::u64 | unchecked_add | function | This results in undefined behavior when `self + rhs > u64::MAX`, i.e. when [`checked_add`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_add`]: u64::checked_add [`wrapping_add`]: u64::wrapping_add | |
| 5492 | core::u64 | unchecked_cast | function | This results in undefined behavior if the integer value of `self` is bigger than `T::MAX`, or smaller than `T::MIN`, where `T` is the target type. | |
| 5493 | core::u64 | unchecked_disjoint_bitor | function | Requires that `(self & other) == 0`, otherwise it's immediate UB. Equivalently, requires that `(self | other) == (self + other)`. | |
| 5494 | core::u64 | unchecked_div_exact | function | This results in undefined behavior when `rhs == 0` or `self % rhs != 0`, i.e. when [`checked_div_exact`](Self::checked_div_exact) would return `None`. | |
| 5495 | core::u64 | unchecked_funnel_shl | function | This results in undefined behavior if `n` is greater than or equal to `u64::BITS`, i.e. when [`funnel_shl`](Self::funnel_shl) would panic. | |
| 5496 | core::u64 | unchecked_funnel_shr | function | This results in undefined behavior if `n` is greater than or equal to `u64::BITS`, i.e. when [`funnel_shr`](Self::funnel_shr) would panic. | |
| 5497 | core::u64 | unchecked_mul | function | This results in undefined behavior when `self * rhs > u64::MAX`, i.e. when [`checked_mul`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_mul`]: u64::checked_mul [`wrapping_mul`]: u64::wrapping_mul | |
| 5498 | core::u64 | unchecked_shl | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shl`] would return `None`. [`checked_shl`]: u64::checked_shl | |
| 5499 | core::u64 | unchecked_shl_exact | function | This results in undefined behavior when `rhs > self.leading_zeros() || rhs >= u64::BITS` i.e. when [`u64::shl_exact`] would return `None`. | |
| 5500 | core::u64 | unchecked_shr | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shr`] would return `None`. [`checked_shr`]: u64::checked_shr | |
| 5501 | core::u64 | unchecked_shr_exact | function | This results in undefined behavior when `rhs > self.trailing_zeros() || rhs >= u64::BITS` i.e. when [`u64::shr_exact`] would return `None`. | |
| 5502 | core::u64 | unchecked_sub | function | This results in undefined behavior when `self - rhs < u64::MIN`, i.e. when [`checked_sub`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_sub`]: u64::checked_sub [`wrapping_sub`]: u64::wrapping_sub | |
| 5503 | core::u8 | as_ascii_unchecked | function | This byte must be valid ASCII, or else this is UB. | |
| 5504 | core::u8 | unchecked_add | function | This results in undefined behavior when `self + rhs > u8::MAX`, i.e. when [`checked_add`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_add`]: u8::checked_add [`wrapping_add`]: u8::wrapping_add | |
| 5505 | core::u8 | unchecked_cast | function | This results in undefined behavior if the integer value of `self` is bigger than `T::MAX`, or smaller than `T::MIN`, where `T` is the target type. | |
| 5506 | core::u8 | unchecked_disjoint_bitor | function | Requires that `(self & other) == 0`, otherwise it's immediate UB. Equivalently, requires that `(self | other) == (self + other)`. | |
| 5507 | core::u8 | unchecked_div_exact | function | This results in undefined behavior when `rhs == 0` or `self % rhs != 0`, i.e. when [`checked_div_exact`](Self::checked_div_exact) would return `None`. | |
| 5508 | core::u8 | unchecked_funnel_shl | function | This results in undefined behavior if `n` is greater than or equal to `u8::BITS`, i.e. when [`funnel_shl`](Self::funnel_shl) would panic. | |
| 5509 | core::u8 | unchecked_funnel_shr | function | This results in undefined behavior if `n` is greater than or equal to `u8::BITS`, i.e. when [`funnel_shr`](Self::funnel_shr) would panic. | |
| 5510 | core::u8 | unchecked_mul | function | This results in undefined behavior when `self * rhs > u8::MAX`, i.e. when [`checked_mul`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_mul`]: u8::checked_mul [`wrapping_mul`]: u8::wrapping_mul | |
| 5511 | core::u8 | unchecked_shl | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shl`] would return `None`. [`checked_shl`]: u8::checked_shl | |
| 5512 | core::u8 | unchecked_shl_exact | function | This results in undefined behavior when `rhs > self.leading_zeros() || rhs >= u8::BITS` i.e. when [`u8::shl_exact`] would return `None`. | |
| 5513 | core::u8 | unchecked_shr | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shr`] would return `None`. [`checked_shr`]: u8::checked_shr | |
| 5514 | core::u8 | unchecked_shr_exact | function | This results in undefined behavior when `rhs > self.trailing_zeros() || rhs >= u8::BITS` i.e. when [`u8::shr_exact`] would return `None`. | |
| 5515 | core::u8 | unchecked_sub | function | This results in undefined behavior when `self - rhs < u8::MIN`, i.e. when [`checked_sub`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_sub`]: u8::checked_sub [`wrapping_sub`]: u8::wrapping_sub | |
| 5516 | core::usize | unchecked_add | function | This results in undefined behavior when `self + rhs > usize::MAX`, i.e. when [`checked_add`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_add`]: usize::checked_add [`wrapping_add`]: usize::wrapping_add | |
| 5517 | core::usize | unchecked_cast | function | This results in undefined behavior if the integer value of `self` is bigger than `T::MAX`, or smaller than `T::MIN`, where `T` is the target type. | |
| 5518 | core::usize | unchecked_disjoint_bitor | function | Requires that `(self & other) == 0`, otherwise it's immediate UB. Equivalently, requires that `(self | other) == (self + other)`. | |
| 5519 | core::usize | unchecked_div_exact | function | This results in undefined behavior when `rhs == 0` or `self % rhs != 0`, i.e. when [`checked_div_exact`](Self::checked_div_exact) would return `None`. | |
| 5520 | core::usize | unchecked_funnel_shl | function | This results in undefined behavior if `n` is greater than or equal to `usize::BITS`, i.e. when [`funnel_shl`](Self::funnel_shl) would panic. | |
| 5521 | core::usize | unchecked_funnel_shr | function | This results in undefined behavior if `n` is greater than or equal to `usize::BITS`, i.e. when [`funnel_shr`](Self::funnel_shr) would panic. | |
| 5522 | core::usize | unchecked_mul | function | This results in undefined behavior when `self * rhs > usize::MAX`, i.e. when [`checked_mul`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_mul`]: usize::checked_mul [`wrapping_mul`]: usize::wrapping_mul | |
| 5523 | core::usize | unchecked_shl | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shl`] would return `None`. [`checked_shl`]: usize::checked_shl | |
| 5524 | core::usize | unchecked_shl_exact | function | This results in undefined behavior when `rhs > self.leading_zeros() || rhs >= usize::BITS` i.e. when [`usize::shl_exact`] would return `None`. | |
| 5525 | core::usize | unchecked_shr | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shr`] would return `None`. [`checked_shr`]: usize::checked_shr | |
| 5526 | core::usize | unchecked_shr_exact | function | This results in undefined behavior when `rhs > self.trailing_zeros() || rhs >= usize::BITS` i.e. when [`usize::shr_exact`] would return `None`. | |
| 5527 | core::usize | unchecked_sub | function | This results in undefined behavior when `self - rhs < usize::MIN`, i.e. when [`checked_sub`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_sub`]: usize::checked_sub [`wrapping_sub`]: usize::wrapping_sub | |
| 5528 | std::char | as_ascii_unchecked | function | This char must be within the ASCII range, or else this is UB. | |
| 5529 | std::char | from_u32_unchecked | function | This function is unsafe, as it may construct invalid `char` values. For a safe version of this function, see the [`from_u32`] function. [`from_u32`]: #method.from_u32 | |
| 5530 | std::collections::hash::map::HashMap | get_disjoint_unchecked_mut | function | Calling this method with overlapping keys is *[undefined behavior]* even if the resulting references are not used. [undefined behavior]: https://doc.rust-lang.org/reference/behavior-considered-undefined.html | |
| 5531 | std::env | remove_var | function | This function is sound to call in a single-threaded program. This function is also always sound to call on Windows, in single-threaded and multi-threaded programs. In multi-threaded programs on other operating systems, the only sound option is to not use `set_var` or `remove_var` at all. The exact requirement is: you must ensure that there are no other threads concurrently writing or *reading*(!) the environment through functions or global variables other than the ones in this module. The problem is that these operating systems do not provide a thread-safe way to read the environment, and most C libraries, including libc itself, do not advertise which functions read from the environment. Even functions from the Rust standard library may read the environment without going through this module, e.g. for DNS lookups from [`std::net::ToSocketAddrs`]. No stable guarantee is made about which functions may read from the environment in future versions of a library. All this makes it not practically possible for you to guarantee that no other thread will read the environment, so the only sound option is to not use `set_var` or `remove_var` in multi-threaded programs at all. Discussion of this unsafety on Unix may be found in: - [Austin Group Bugzilla](https://austingroupbugs.net/view.php?id=188) - [GNU C library Bugzilla](https://sourceware.org/bugzilla/show_bug.cgi?id=15607#c2) To prevent a child process from inheriting an environment variable, you can instead use [`Command::env_remove`] or [`Command::env_clear`]. [`std::net::ToSocketAddrs`]: crate::net::ToSocketAddrs [`Command::env_remove`]: crate::process::Command::env_remove [`Command::env_clear`]: crate::process::Command::env_clear | |
| 5532 | std::env | set_var | function | This function is sound to call in a single-threaded program. This function is also always sound to call on Windows, in single-threaded and multi-threaded programs. In multi-threaded programs on other operating systems, the only sound option is to not use `set_var` or `remove_var` at all. The exact requirement is: you must ensure that there are no other threads concurrently writing or *reading*(!) the environment through functions or global variables other than the ones in this module. The problem is that these operating systems do not provide a thread-safe way to read the environment, and most C libraries, including libc itself, do not advertise which functions read from the environment. Even functions from the Rust standard library may read the environment without going through this module, e.g. for DNS lookups from [`std::net::ToSocketAddrs`]. No stable guarantee is made about which functions may read from the environment in future versions of a library. All this makes it not practically possible for you to guarantee that no other thread will read the environment, so the only sound option is to not use `set_var` or `remove_var` in multi-threaded programs at all. Discussion of this unsafety on Unix may be found in: - [Austin Group Bugzilla (for POSIX)](https://austingroupbugs.net/view.php?id=188) - [GNU C library Bugzilla](https://sourceware.org/bugzilla/show_bug.cgi?id=15607#c2) To pass an environment variable to a child process, you can instead use [`Command::env`]. [`std::net::ToSocketAddrs`]: crate::net::ToSocketAddrs [`Command::env`]: crate::process::Command::env | |
| 5533 | std::f128 | to_int_unchecked | function | The value must: * Not be `NaN` * Not be infinite * Be representable in the return type `Int`, after truncating off its fractional part | |
| 5534 | std::f16 | to_int_unchecked | function | The value must: * Not be `NaN` * Not be infinite * Be representable in the return type `Int`, after truncating off its fractional part | |
| 5535 | std::f32 | to_int_unchecked | function | The value must: * Not be `NaN` * Not be infinite * Be representable in the return type `Int`, after truncating off its fractional part | |
| 5536 | std::f64 | to_int_unchecked | function | The value must: * Not be `NaN` * Not be infinite * Be representable in the return type `Int`, after truncating off its fractional part | |
| 5537 | std::ffi::os_str::OsStr | from_encoded_bytes_unchecked | function | As the encoding is unspecified, callers must pass in bytes that originated as a mixture of validated UTF-8 and bytes from [`OsStr::as_encoded_bytes`] from within the same Rust version built for the same target platform. For example, reconstructing an `OsStr` from bytes sent over the network or stored in a file will likely violate these safety rules. Due to the encoding being self-synchronizing, the bytes from [`OsStr::as_encoded_bytes`] can be split either immediately before or immediately after any valid non-empty UTF-8 substring. | |
| 5538 | std::ffi::os_str::OsString | from_encoded_bytes_unchecked | function | As the encoding is unspecified, callers must pass in bytes that originated as a mixture of validated UTF-8 and bytes from [`OsStr::as_encoded_bytes`] from within the same Rust version built for the same target platform. For example, reconstructing an `OsString` from bytes sent over the network or stored in a file will likely violate these safety rules. Due to the encoding being self-synchronizing, the bytes from [`OsStr::as_encoded_bytes`] can be split either immediately before or immediately after any valid non-empty UTF-8 substring. | |
| 5539 | std::i128 | unchecked_add | function | This results in undefined behavior when `self + rhs > i128::MAX` or `self + rhs < i128::MIN`, i.e. when [`checked_add`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_add`]: i128::checked_add [`wrapping_add`]: i128::wrapping_add | |
| 5540 | std::i128 | unchecked_cast | function | This results in undefined behavior if the integer value of `self` is bigger than `T::MAX`, or smaller than `T::MIN`, where `T` is the target type. | |
| 5541 | std::i128 | unchecked_div_exact | function | This results in undefined behavior when `rhs == 0`, `self % rhs != 0`, or `self == i128::MIN && rhs == -1`, i.e. when [`checked_div_exact`](Self::checked_div_exact) would return `None`. | |
| 5542 | std::i128 | unchecked_mul | function | This results in undefined behavior when `self * rhs > i128::MAX` or `self * rhs < i128::MIN`, i.e. when [`checked_mul`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_mul`]: i128::checked_mul [`wrapping_mul`]: i128::wrapping_mul | |
| 5543 | std::i128 | unchecked_neg | function | This results in undefined behavior when `self == i128::MIN`, i.e. when [`checked_neg`] would return `None`. [`checked_neg`]: i128::checked_neg | |
| 5544 | std::i128 | unchecked_shl | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shl`] would return `None`. [`checked_shl`]: i128::checked_shl | |
| 5545 | std::i128 | unchecked_shl_exact | function | This results in undefined behavior when `rhs >= self.leading_zeros() && rhs >= self.leading_ones()` i.e. when [`i128::shl_exact`] would return `None`. | |
| 5546 | std::i128 | unchecked_shr | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shr`] would return `None`. [`checked_shr`]: i128::checked_shr | |
| 5547 | std::i128 | unchecked_shr_exact | function | This results in undefined behavior when `rhs > self.trailing_zeros() || rhs >= i128::BITS` i.e. when [`i128::shr_exact`] would return `None`. | |
| 5548 | std::i128 | unchecked_sub | function | This results in undefined behavior when `self - rhs > i128::MAX` or `self - rhs < i128::MIN`, i.e. when [`checked_sub`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_sub`]: i128::checked_sub [`wrapping_sub`]: i128::wrapping_sub | |
| 5549 | std::i16 | unchecked_add | function | This results in undefined behavior when `self + rhs > i16::MAX` or `self + rhs < i16::MIN`, i.e. when [`checked_add`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_add`]: i16::checked_add [`wrapping_add`]: i16::wrapping_add | |
| 5550 | std::i16 | unchecked_cast | function | This results in undefined behavior if the integer value of `self` is bigger than `T::MAX`, or smaller than `T::MIN`, where `T` is the target type. | |
| 5551 | std::i16 | unchecked_div_exact | function | This results in undefined behavior when `rhs == 0`, `self % rhs != 0`, or `self == i16::MIN && rhs == -1`, i.e. when [`checked_div_exact`](Self::checked_div_exact) would return `None`. | |
| 5552 | std::i16 | unchecked_mul | function | This results in undefined behavior when `self * rhs > i16::MAX` or `self * rhs < i16::MIN`, i.e. when [`checked_mul`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_mul`]: i16::checked_mul [`wrapping_mul`]: i16::wrapping_mul | |
| 5553 | std::i16 | unchecked_neg | function | This results in undefined behavior when `self == i16::MIN`, i.e. when [`checked_neg`] would return `None`. [`checked_neg`]: i16::checked_neg | |
| 5554 | std::i16 | unchecked_shl | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shl`] would return `None`. [`checked_shl`]: i16::checked_shl | |
| 5555 | std::i16 | unchecked_shl_exact | function | This results in undefined behavior when `rhs >= self.leading_zeros() && rhs >= self.leading_ones()` i.e. when [`i16::shl_exact`] would return `None`. | |
| 5556 | std::i16 | unchecked_shr | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shr`] would return `None`. [`checked_shr`]: i16::checked_shr | |
| 5557 | std::i16 | unchecked_shr_exact | function | This results in undefined behavior when `rhs > self.trailing_zeros() || rhs >= i16::BITS` i.e. when [`i16::shr_exact`] would return `None`. | |
| 5558 | std::i16 | unchecked_sub | function | This results in undefined behavior when `self - rhs > i16::MAX` or `self - rhs < i16::MIN`, i.e. when [`checked_sub`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_sub`]: i16::checked_sub [`wrapping_sub`]: i16::wrapping_sub | |
| 5559 | std::i32 | unchecked_add | function | This results in undefined behavior when `self + rhs > i32::MAX` or `self + rhs < i32::MIN`, i.e. when [`checked_add`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_add`]: i32::checked_add [`wrapping_add`]: i32::wrapping_add | |
| 5560 | std::i32 | unchecked_cast | function | This results in undefined behavior if the integer value of `self` is bigger than `T::MAX`, or smaller than `T::MIN`, where `T` is the target type. | |
| 5561 | std::i32 | unchecked_div_exact | function | This results in undefined behavior when `rhs == 0`, `self % rhs != 0`, or `self == i32::MIN && rhs == -1`, i.e. when [`checked_div_exact`](Self::checked_div_exact) would return `None`. | |
| 5562 | std::i32 | unchecked_mul | function | This results in undefined behavior when `self * rhs > i32::MAX` or `self * rhs < i32::MIN`, i.e. when [`checked_mul`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_mul`]: i32::checked_mul [`wrapping_mul`]: i32::wrapping_mul | |
| 5563 | std::i32 | unchecked_neg | function | This results in undefined behavior when `self == i32::MIN`, i.e. when [`checked_neg`] would return `None`. [`checked_neg`]: i32::checked_neg | |
| 5564 | std::i32 | unchecked_shl | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shl`] would return `None`. [`checked_shl`]: i32::checked_shl | |
| 5565 | std::i32 | unchecked_shl_exact | function | This results in undefined behavior when `rhs >= self.leading_zeros() && rhs >= self.leading_ones()` i.e. when [`i32::shl_exact`] would return `None`. | |
| 5566 | std::i32 | unchecked_shr | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shr`] would return `None`. [`checked_shr`]: i32::checked_shr | |
| 5567 | std::i32 | unchecked_shr_exact | function | This results in undefined behavior when `rhs > self.trailing_zeros() || rhs >= i32::BITS` i.e. when [`i32::shr_exact`] would return `None`. | |
| 5568 | std::i32 | unchecked_sub | function | This results in undefined behavior when `self - rhs > i32::MAX` or `self - rhs < i32::MIN`, i.e. when [`checked_sub`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_sub`]: i32::checked_sub [`wrapping_sub`]: i32::wrapping_sub | |
| 5569 | std::i64 | unchecked_add | function | This results in undefined behavior when `self + rhs > i64::MAX` or `self + rhs < i64::MIN`, i.e. when [`checked_add`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_add`]: i64::checked_add [`wrapping_add`]: i64::wrapping_add | |
| 5570 | std::i64 | unchecked_cast | function | This results in undefined behavior if the integer value of `self` is bigger than `T::MAX`, or smaller than `T::MIN`, where `T` is the target type. | |
| 5571 | std::i64 | unchecked_div_exact | function | This results in undefined behavior when `rhs == 0`, `self % rhs != 0`, or `self == i64::MIN && rhs == -1`, i.e. when [`checked_div_exact`](Self::checked_div_exact) would return `None`. | |
| 5572 | std::i64 | unchecked_mul | function | This results in undefined behavior when `self * rhs > i64::MAX` or `self * rhs < i64::MIN`, i.e. when [`checked_mul`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_mul`]: i64::checked_mul [`wrapping_mul`]: i64::wrapping_mul | |
| 5573 | std::i64 | unchecked_neg | function | This results in undefined behavior when `self == i64::MIN`, i.e. when [`checked_neg`] would return `None`. [`checked_neg`]: i64::checked_neg | |
| 5574 | std::i64 | unchecked_shl | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shl`] would return `None`. [`checked_shl`]: i64::checked_shl | |
| 5575 | std::i64 | unchecked_shl_exact | function | This results in undefined behavior when `rhs >= self.leading_zeros() && rhs >= self.leading_ones()` i.e. when [`i64::shl_exact`] would return `None`. | |
| 5576 | std::i64 | unchecked_shr | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shr`] would return `None`. [`checked_shr`]: i64::checked_shr | |
| 5577 | std::i64 | unchecked_shr_exact | function | This results in undefined behavior when `rhs > self.trailing_zeros() || rhs >= i64::BITS` i.e. when [`i64::shr_exact`] would return `None`. | |
| 5578 | std::i64 | unchecked_sub | function | This results in undefined behavior when `self - rhs > i64::MAX` or `self - rhs < i64::MIN`, i.e. when [`checked_sub`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_sub`]: i64::checked_sub [`wrapping_sub`]: i64::wrapping_sub | |
| 5579 | std::i8 | unchecked_add | function | This results in undefined behavior when `self + rhs > i8::MAX` or `self + rhs < i8::MIN`, i.e. when [`checked_add`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_add`]: i8::checked_add [`wrapping_add`]: i8::wrapping_add | |
| 5580 | std::i8 | unchecked_cast | function | This results in undefined behavior if the integer value of `self` is bigger than `T::MAX`, or smaller than `T::MIN`, where `T` is the target type. | |
| 5581 | std::i8 | unchecked_div_exact | function | This results in undefined behavior when `rhs == 0`, `self % rhs != 0`, or `self == i8::MIN && rhs == -1`, i.e. when [`checked_div_exact`](Self::checked_div_exact) would return `None`. | |
| 5582 | std::i8 | unchecked_mul | function | This results in undefined behavior when `self * rhs > i8::MAX` or `self * rhs < i8::MIN`, i.e. when [`checked_mul`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_mul`]: i8::checked_mul [`wrapping_mul`]: i8::wrapping_mul | |
| 5583 | std::i8 | unchecked_neg | function | This results in undefined behavior when `self == i8::MIN`, i.e. when [`checked_neg`] would return `None`. [`checked_neg`]: i8::checked_neg | |
| 5584 | std::i8 | unchecked_shl | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shl`] would return `None`. [`checked_shl`]: i8::checked_shl | |
| 5585 | std::i8 | unchecked_shl_exact | function | This results in undefined behavior when `rhs >= self.leading_zeros() && rhs >= self.leading_ones()` i.e. when [`i8::shl_exact`] would return `None`. | |
| 5586 | std::i8 | unchecked_shr | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shr`] would return `None`. [`checked_shr`]: i8::checked_shr | |
| 5587 | std::i8 | unchecked_shr_exact | function | This results in undefined behavior when `rhs > self.trailing_zeros() || rhs >= i8::BITS` i.e. when [`i8::shr_exact`] would return `None`. | |
| 5588 | std::i8 | unchecked_sub | function | This results in undefined behavior when `self - rhs > i8::MAX` or `self - rhs < i8::MIN`, i.e. when [`checked_sub`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_sub`]: i8::checked_sub [`wrapping_sub`]: i8::wrapping_sub | |
| 5589 | std::isize | unchecked_add | function | This results in undefined behavior when `self + rhs > isize::MAX` or `self + rhs < isize::MIN`, i.e. when [`checked_add`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_add`]: isize::checked_add [`wrapping_add`]: isize::wrapping_add | |
| 5590 | std::isize | unchecked_cast | function | This results in undefined behavior if the integer value of `self` is bigger than `T::MAX`, or smaller than `T::MIN`, where `T` is the target type. | |
| 5591 | std::isize | unchecked_div_exact | function | This results in undefined behavior when `rhs == 0`, `self % rhs != 0`, or `self == isize::MIN && rhs == -1`, i.e. when [`checked_div_exact`](Self::checked_div_exact) would return `None`. | |
| 5592 | std::isize | unchecked_mul | function | This results in undefined behavior when `self * rhs > isize::MAX` or `self * rhs < isize::MIN`, i.e. when [`checked_mul`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_mul`]: isize::checked_mul [`wrapping_mul`]: isize::wrapping_mul | |
| 5593 | std::isize | unchecked_neg | function | This results in undefined behavior when `self == isize::MIN`, i.e. when [`checked_neg`] would return `None`. [`checked_neg`]: isize::checked_neg | |
| 5594 | std::isize | unchecked_shl | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shl`] would return `None`. [`checked_shl`]: isize::checked_shl | |
| 5595 | std::isize | unchecked_shl_exact | function | This results in undefined behavior when `rhs >= self.leading_zeros() && rhs >= self.leading_ones()` i.e. when [`isize::shl_exact`] would return `None`. | |
| 5596 | std::isize | unchecked_shr | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shr`] would return `None`. [`checked_shr`]: isize::checked_shr | |
| 5597 | std::isize | unchecked_shr_exact | function | This results in undefined behavior when `rhs > self.trailing_zeros() || rhs >= isize::BITS` i.e. when [`isize::shr_exact`] would return `None`. | |
| 5598 | std::isize | unchecked_sub | function | This results in undefined behavior when `self - rhs > isize::MAX` or `self - rhs < isize::MIN`, i.e. when [`checked_sub`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_sub`]: isize::checked_sub [`wrapping_sub`]: isize::wrapping_sub | |
| 5599 | std::os::fd::owned::BorrowedFd | borrow_raw | function | The resource pointed to by `fd` must remain open for the duration of the returned `BorrowedFd`. | |
| 5600 | std::os::windows::io::handle::BorrowedHandle | borrow_raw | function | The resource pointed to by `handle` must be a valid open handle, it must remain open for the duration of the returned `BorrowedHandle`. Note that it *may* have the value `INVALID_HANDLE_VALUE` (-1), which is sometimes a valid handle value. See [here] for the full story. And, it *may* have the value `NULL` (0), which can occur when consoles are detached from processes, or when `windows_subsystem` is used. [here]: https://devblogs.microsoft.com/oldnewthing/20040302-00/?p=40443 | |
| 5601 | std::os::windows::io::handle::HandleOrInvalid | from_raw_handle | function | The passed `handle` value must either satisfy the safety requirements of [`FromRawHandle::from_raw_handle`], or be `INVALID_HANDLE_VALUE` (-1). Note that not all Windows APIs use `INVALID_HANDLE_VALUE` for errors; see [here] for the full story. [here]: https://devblogs.microsoft.com/oldnewthing/20040302-00/?p=40443 | |
| 5602 | std::os::windows::io::handle::HandleOrNull | from_raw_handle | function | The passed `handle` value must either satisfy the safety requirements of [`FromRawHandle::from_raw_handle`], or be null. Note that not all Windows APIs use null for errors; see [here] for the full story. [here]: https://devblogs.microsoft.com/oldnewthing/20040302-00/?p=40443 | |
| 5603 | std::os::windows::io::socket::BorrowedSocket | borrow_raw | function | The resource pointed to by `socket` must remain open for the duration of the returned `BorrowedSocket`, and it must not have the value `INVALID_SOCKET`. | |
| 5604 | std::os::windows::process::ProcThreadAttributeListBuilder | raw_attribute | function | This function is marked as `unsafe` because it deals with raw pointers and sizes. It is the responsibility of the caller to ensure the value lives longer than the resulting [`ProcThreadAttributeList`] as well as the validity of the size parameter. | |
| 5605 | std::str | as_ascii_unchecked | function | Every character in this string must be ASCII, or else this is UB. | |
| 5606 | std::str | as_bytes_mut | function | The caller must ensure that the content of the slice is valid UTF-8 before the borrow ends and the underlying `str` is used. Use of a `str` whose contents are not valid UTF-8 is undefined behavior. | |
| 5607 | std::str | from_utf8_unchecked | function | The bytes passed in must be valid UTF-8. | |
| 5608 | std::str | from_utf8_unchecked_mut | function | ||
| 5609 | std::str | get_unchecked | function | Callers of this function are responsible that these preconditions are satisfied: * The starting index must not exceed the ending index; * Indexes must be within bounds of the original slice; * Indexes must lie on UTF-8 sequence boundaries. Failing that, the returned string slice may reference invalid memory or violate the invariants communicated by the `str` type. | |
| 5610 | std::str | get_unchecked_mut | function | Callers of this function are responsible that these preconditions are satisfied: * The starting index must not exceed the ending index; * Indexes must be within bounds of the original slice; * Indexes must lie on UTF-8 sequence boundaries. Failing that, the returned string slice may reference invalid memory or violate the invariants communicated by the `str` type. | |
| 5611 | std::str | slice_mut_unchecked | function | Callers of this function are responsible that three preconditions are satisfied: * `begin` must not exceed `end`. * `begin` and `end` must be byte positions within the string slice. * `begin` and `end` must lie on UTF-8 sequence boundaries. | |
| 5612 | std::str | slice_unchecked | function | Callers of this function are responsible that three preconditions are satisfied: * `begin` must not exceed `end`. * `begin` and `end` must be byte positions within the string slice. * `begin` and `end` must lie on UTF-8 sequence boundaries. | |
| 5613 | std::thread::builder::Builder | spawn_unchecked | function | The caller has to ensure that the spawned thread does not outlive any references in the supplied thread closure and its return type. This can be guaranteed in two ways: - ensure that [`join`][`JoinHandle::join`] is called before any referenced data is dropped - use only types with `'static` lifetime bounds, i.e., those with no or only `'static` references (both [`thread::Builder::spawn`][`Builder::spawn`] and [`thread::spawn`] enforce this property statically) | |
| 5614 | std::thread::thread::Thread | from_raw | function | This function is unsafe because improper use may lead to memory unsafety, even if the returned `Thread` is never accessed. Creating a `Thread` from a pointer other than one returned from [`Thread::into_raw`] is **undefined behavior**. Calling this function twice on the same raw pointer can lead to a double-free if both `Thread` instances are dropped. | |
| 5615 | std::u128 | unchecked_add | function | This results in undefined behavior when `self + rhs > u128::MAX`, i.e. when [`checked_add`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_add`]: u128::checked_add [`wrapping_add`]: u128::wrapping_add | |
| 5616 | std::u128 | unchecked_cast | function | This results in undefined behavior if the integer value of `self` is bigger than `T::MAX`, or smaller than `T::MIN`, where `T` is the target type. | |
| 5617 | std::u128 | unchecked_disjoint_bitor | function | Requires that `(self & other) == 0`, otherwise it's immediate UB. Equivalently, requires that `(self | other) == (self + other)`. | |
| 5618 | std::u128 | unchecked_div_exact | function | This results in undefined behavior when `rhs == 0` or `self % rhs != 0`, i.e. when [`checked_div_exact`](Self::checked_div_exact) would return `None`. | |
| 5619 | std::u128 | unchecked_funnel_shl | function | This results in undefined behavior if `n` is greater than or equal to `u128::BITS`, i.e. when [`funnel_shl`](Self::funnel_shl) would panic. | |
| 5620 | std::u128 | unchecked_funnel_shr | function | This results in undefined behavior if `n` is greater than or equal to `u128::BITS`, i.e. when [`funnel_shr`](Self::funnel_shr) would panic. | |
| 5621 | std::u128 | unchecked_mul | function | This results in undefined behavior when `self * rhs > u128::MAX`, i.e. when [`checked_mul`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_mul`]: u128::checked_mul [`wrapping_mul`]: u128::wrapping_mul | |
| 5622 | std::u128 | unchecked_shl | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shl`] would return `None`. [`checked_shl`]: u128::checked_shl | |
| 5623 | std::u128 | unchecked_shl_exact | function | This results in undefined behavior when `rhs > self.leading_zeros() || rhs >= u128::BITS` i.e. when [`u128::shl_exact`] would return `None`. | |
| 5624 | std::u128 | unchecked_shr | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shr`] would return `None`. [`checked_shr`]: u128::checked_shr | |
| 5625 | std::u128 | unchecked_shr_exact | function | This results in undefined behavior when `rhs > self.trailing_zeros() || rhs >= u128::BITS` i.e. when [`u128::shr_exact`] would return `None`. | |
| 5626 | std::u128 | unchecked_sub | function | This results in undefined behavior when `self - rhs < u128::MIN`, i.e. when [`checked_sub`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_sub`]: u128::checked_sub [`wrapping_sub`]: u128::wrapping_sub | |
| 5627 | std::u16 | unchecked_add | function | This results in undefined behavior when `self + rhs > u16::MAX`, i.e. when [`checked_add`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_add`]: u16::checked_add [`wrapping_add`]: u16::wrapping_add | |
| 5628 | std::u16 | unchecked_cast | function | This results in undefined behavior if the integer value of `self` is bigger than `T::MAX`, or smaller than `T::MIN`, where `T` is the target type. | |
| 5629 | std::u16 | unchecked_disjoint_bitor | function | Requires that `(self & other) == 0`, otherwise it's immediate UB. Equivalently, requires that `(self | other) == (self + other)`. | |
| 5630 | std::u16 | unchecked_div_exact | function | This results in undefined behavior when `rhs == 0` or `self % rhs != 0`, i.e. when [`checked_div_exact`](Self::checked_div_exact) would return `None`. | |
| 5631 | std::u16 | unchecked_funnel_shl | function | This results in undefined behavior if `n` is greater than or equal to `u16::BITS`, i.e. when [`funnel_shl`](Self::funnel_shl) would panic. | |
| 5632 | std::u16 | unchecked_funnel_shr | function | This results in undefined behavior if `n` is greater than or equal to `u16::BITS`, i.e. when [`funnel_shr`](Self::funnel_shr) would panic. | |
| 5633 | std::u16 | unchecked_mul | function | This results in undefined behavior when `self * rhs > u16::MAX`, i.e. when [`checked_mul`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_mul`]: u16::checked_mul [`wrapping_mul`]: u16::wrapping_mul | |
| 5634 | std::u16 | unchecked_shl | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shl`] would return `None`. [`checked_shl`]: u16::checked_shl | |
| 5635 | std::u16 | unchecked_shl_exact | function | This results in undefined behavior when `rhs > self.leading_zeros() || rhs >= u16::BITS` i.e. when [`u16::shl_exact`] would return `None`. | |
| 5636 | std::u16 | unchecked_shr | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shr`] would return `None`. [`checked_shr`]: u16::checked_shr | |
| 5637 | std::u16 | unchecked_shr_exact | function | This results in undefined behavior when `rhs > self.trailing_zeros() || rhs >= u16::BITS` i.e. when [`u16::shr_exact`] would return `None`. | |
| 5638 | std::u16 | unchecked_sub | function | This results in undefined behavior when `self - rhs < u16::MIN`, i.e. when [`checked_sub`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_sub`]: u16::checked_sub [`wrapping_sub`]: u16::wrapping_sub | |
| 5639 | std::u32 | unchecked_add | function | This results in undefined behavior when `self + rhs > u32::MAX`, i.e. when [`checked_add`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_add`]: u32::checked_add [`wrapping_add`]: u32::wrapping_add | |
| 5640 | std::u32 | unchecked_cast | function | This results in undefined behavior if the integer value of `self` is bigger than `T::MAX`, or smaller than `T::MIN`, where `T` is the target type. | |
| 5641 | std::u32 | unchecked_disjoint_bitor | function | Requires that `(self & other) == 0`, otherwise it's immediate UB. Equivalently, requires that `(self | other) == (self + other)`. | |
| 5642 | std::u32 | unchecked_div_exact | function | This results in undefined behavior when `rhs == 0` or `self % rhs != 0`, i.e. when [`checked_div_exact`](Self::checked_div_exact) would return `None`. | |
| 5643 | std::u32 | unchecked_funnel_shl | function | This results in undefined behavior if `n` is greater than or equal to `u32::BITS`, i.e. when [`funnel_shl`](Self::funnel_shl) would panic. | |
| 5644 | std::u32 | unchecked_funnel_shr | function | This results in undefined behavior if `n` is greater than or equal to `u32::BITS`, i.e. when [`funnel_shr`](Self::funnel_shr) would panic. | |
| 5645 | std::u32 | unchecked_mul | function | This results in undefined behavior when `self * rhs > u32::MAX`, i.e. when [`checked_mul`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_mul`]: u32::checked_mul [`wrapping_mul`]: u32::wrapping_mul | |
| 5646 | std::u32 | unchecked_shl | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shl`] would return `None`. [`checked_shl`]: u32::checked_shl | |
| 5647 | std::u32 | unchecked_shl_exact | function | This results in undefined behavior when `rhs > self.leading_zeros() || rhs >= u32::BITS` i.e. when [`u32::shl_exact`] would return `None`. | |
| 5648 | std::u32 | unchecked_shr | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shr`] would return `None`. [`checked_shr`]: u32::checked_shr | |
| 5649 | std::u32 | unchecked_shr_exact | function | This results in undefined behavior when `rhs > self.trailing_zeros() || rhs >= u32::BITS` i.e. when [`u32::shr_exact`] would return `None`. | |
| 5650 | std::u32 | unchecked_sub | function | This results in undefined behavior when `self - rhs < u32::MIN`, i.e. when [`checked_sub`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_sub`]: u32::checked_sub [`wrapping_sub`]: u32::wrapping_sub | |
| 5651 | std::u64 | unchecked_add | function | This results in undefined behavior when `self + rhs > u64::MAX`, i.e. when [`checked_add`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_add`]: u64::checked_add [`wrapping_add`]: u64::wrapping_add | |
| 5652 | std::u64 | unchecked_cast | function | This results in undefined behavior if the integer value of `self` is bigger than `T::MAX`, or smaller than `T::MIN`, where `T` is the target type. | |
| 5653 | std::u64 | unchecked_disjoint_bitor | function | Requires that `(self & other) == 0`, otherwise it's immediate UB. Equivalently, requires that `(self | other) == (self + other)`. | |
| 5654 | std::u64 | unchecked_div_exact | function | This results in undefined behavior when `rhs == 0` or `self % rhs != 0`, i.e. when [`checked_div_exact`](Self::checked_div_exact) would return `None`. | |
| 5655 | std::u64 | unchecked_funnel_shl | function | This results in undefined behavior if `n` is greater than or equal to `u64::BITS`, i.e. when [`funnel_shl`](Self::funnel_shl) would panic. | |
| 5656 | std::u64 | unchecked_funnel_shr | function | This results in undefined behavior if `n` is greater than or equal to `u64::BITS`, i.e. when [`funnel_shr`](Self::funnel_shr) would panic. | |
| 5657 | std::u64 | unchecked_mul | function | This results in undefined behavior when `self * rhs > u64::MAX`, i.e. when [`checked_mul`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_mul`]: u64::checked_mul [`wrapping_mul`]: u64::wrapping_mul | |
| 5658 | std::u64 | unchecked_shl | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shl`] would return `None`. [`checked_shl`]: u64::checked_shl | |
| 5659 | std::u64 | unchecked_shl_exact | function | This results in undefined behavior when `rhs > self.leading_zeros() || rhs >= u64::BITS` i.e. when [`u64::shl_exact`] would return `None`. | |
| 5660 | std::u64 | unchecked_shr | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shr`] would return `None`. [`checked_shr`]: u64::checked_shr | |
| 5661 | std::u64 | unchecked_shr_exact | function | This results in undefined behavior when `rhs > self.trailing_zeros() || rhs >= u64::BITS` i.e. when [`u64::shr_exact`] would return `None`. | |
| 5662 | std::u64 | unchecked_sub | function | This results in undefined behavior when `self - rhs < u64::MIN`, i.e. when [`checked_sub`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_sub`]: u64::checked_sub [`wrapping_sub`]: u64::wrapping_sub | |
| 5663 | std::u8 | as_ascii_unchecked | function | This byte must be valid ASCII, or else this is UB. | |
| 5664 | std::u8 | unchecked_add | function | This results in undefined behavior when `self + rhs > u8::MAX`, i.e. when [`checked_add`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_add`]: u8::checked_add [`wrapping_add`]: u8::wrapping_add | |
| 5665 | std::u8 | unchecked_cast | function | This results in undefined behavior if the integer value of `self` is bigger than `T::MAX`, or smaller than `T::MIN`, where `T` is the target type. | |
| 5666 | std::u8 | unchecked_disjoint_bitor | function | Requires that `(self & other) == 0`, otherwise it's immediate UB. Equivalently, requires that `(self | other) == (self + other)`. | |
| 5667 | std::u8 | unchecked_div_exact | function | This results in undefined behavior when `rhs == 0` or `self % rhs != 0`, i.e. when [`checked_div_exact`](Self::checked_div_exact) would return `None`. | |
| 5668 | std::u8 | unchecked_funnel_shl | function | This results in undefined behavior if `n` is greater than or equal to `u8::BITS`, i.e. when [`funnel_shl`](Self::funnel_shl) would panic. | |
| 5669 | std::u8 | unchecked_funnel_shr | function | This results in undefined behavior if `n` is greater than or equal to `u8::BITS`, i.e. when [`funnel_shr`](Self::funnel_shr) would panic. | |
| 5670 | std::u8 | unchecked_mul | function | This results in undefined behavior when `self * rhs > u8::MAX`, i.e. when [`checked_mul`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_mul`]: u8::checked_mul [`wrapping_mul`]: u8::wrapping_mul | |
| 5671 | std::u8 | unchecked_shl | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shl`] would return `None`. [`checked_shl`]: u8::checked_shl | |
| 5672 | std::u8 | unchecked_shl_exact | function | This results in undefined behavior when `rhs > self.leading_zeros() || rhs >= u8::BITS` i.e. when [`u8::shl_exact`] would return `None`. | |
| 5673 | std::u8 | unchecked_shr | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shr`] would return `None`. [`checked_shr`]: u8::checked_shr | |
| 5674 | std::u8 | unchecked_shr_exact | function | This results in undefined behavior when `rhs > self.trailing_zeros() || rhs >= u8::BITS` i.e. when [`u8::shr_exact`] would return `None`. | |
| 5675 | std::u8 | unchecked_sub | function | This results in undefined behavior when `self - rhs < u8::MIN`, i.e. when [`checked_sub`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_sub`]: u8::checked_sub [`wrapping_sub`]: u8::wrapping_sub | |
| 5676 | std::usize | unchecked_add | function | This results in undefined behavior when `self + rhs > usize::MAX`, i.e. when [`checked_add`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_add`]: usize::checked_add [`wrapping_add`]: usize::wrapping_add | |
| 5677 | std::usize | unchecked_cast | function | This results in undefined behavior if the integer value of `self` is bigger than `T::MAX`, or smaller than `T::MIN`, where `T` is the target type. | |
| 5678 | std::usize | unchecked_disjoint_bitor | function | Requires that `(self & other) == 0`, otherwise it's immediate UB. Equivalently, requires that `(self | other) == (self + other)`. | |
| 5679 | std::usize | unchecked_div_exact | function | This results in undefined behavior when `rhs == 0` or `self % rhs != 0`, i.e. when [`checked_div_exact`](Self::checked_div_exact) would return `None`. | |
| 5680 | std::usize | unchecked_funnel_shl | function | This results in undefined behavior if `n` is greater than or equal to `usize::BITS`, i.e. when [`funnel_shl`](Self::funnel_shl) would panic. | |
| 5681 | std::usize | unchecked_funnel_shr | function | This results in undefined behavior if `n` is greater than or equal to `usize::BITS`, i.e. when [`funnel_shr`](Self::funnel_shr) would panic. | |
| 5682 | std::usize | unchecked_mul | function | This results in undefined behavior when `self * rhs > usize::MAX`, i.e. when [`checked_mul`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_mul`]: usize::checked_mul [`wrapping_mul`]: usize::wrapping_mul | |
| 5683 | std::usize | unchecked_shl | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shl`] would return `None`. [`checked_shl`]: usize::checked_shl | |
| 5684 | std::usize | unchecked_shl_exact | function | This results in undefined behavior when `rhs > self.leading_zeros() || rhs >= usize::BITS` i.e. when [`usize::shl_exact`] would return `None`. | |
| 5685 | std::usize | unchecked_shr | function | This results in undefined behavior if `rhs` is larger than or equal to the number of bits in `self`, i.e. when [`checked_shr`] would return `None`. [`checked_shr`]: usize::checked_shr | |
| 5686 | std::usize | unchecked_shr_exact | function | This results in undefined behavior when `rhs > self.trailing_zeros() || rhs >= usize::BITS` i.e. when [`usize::shr_exact`] would return `None`. | |
| 5687 | std::usize | unchecked_sub | function | This results in undefined behavior when `self - rhs < usize::MIN`, i.e. when [`checked_sub`] would return `None`. [`unwrap_unchecked`]: option/enum.Option.html#method.unwrap_unchecked [`checked_sub`]: usize::checked_sub [`wrapping_sub`]: usize::wrapping_sub |