Public Unsafe APIs — nightly (rustc 1.99.0-nightly (504869653 2026-08-03))

Generated from crates: core, alloc, std.

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IndexModule PathAPI NameKindSafety DocTags Mark
1alloc::allocallocfunction

See GlobalAlloc::alloc.

2alloc::allocalloc_zeroedfunction

See GlobalAlloc::alloc_zeroed.

3alloc::allocdeallocfunction

See GlobalAlloc::dealloc.

4alloc::allocreallocfunction

See GlobalAlloc::realloc.

5alloc::alloc::Globaldeallocatemethod
  • ptr must denote a block of memory [currently allocated] via this allocator, and
  • layout must [fit] that block of memory.
Allocated
6alloc::alloc::Globalgrowmethod
  • ptr must denote a block of memory [currently allocated] via this allocator.
  • old_layout must [fit] that block of memory (The new_layout argument need not fit it.).
  • new_layout.size() must be greater than or equal to old_layout.size().

Note that new_layout.align() need not be the same as old_layout.align().

Allocated, ValidNum
7alloc::alloc::Globalgrow_zeroedmethod
  • ptr must denote a block of memory [currently allocated] via this allocator.
  • old_layout must [fit] that block of memory (The new_layout argument need not fit it.).
  • new_layout.size() must be greater than or equal to old_layout.size().

Note that new_layout.align() need not be the same as old_layout.align().

Allocated, ValidNum
8alloc::alloc::Globalshrinkmethod
  • ptr must denote a block of memory [currently allocated] via this allocator.
  • old_layout must [fit] that block of memory (The new_layout argument need not fit it.).
  • new_layout.size() must be smaller than or equal to old_layout.size().

Note that new_layout.align() need not be the same as old_layout.align().

Allocated
9alloc::boxed::Boxassume_initmethod

As with MaybeUninit::assume_init, it is up to the caller to guarantee that the values really are in an initialized state. Calling this when the content is not yet fully initialized causes immediate undefined behavior.


As with MaybeUninit::assume_init, it is up to the caller to guarantee that the value really is in an initialized state. Calling this when the content is not yet fully initialized causes immediate undefined behavior.

Init
10alloc::boxed::Boxdeallocatemethod
  • ptr must denote a block of memory [currently allocated] via this allocator, and
  • layout must [fit] that block of memory.
Allocated
11alloc::boxed::Boxdowncast_uncheckedmethod

The contained value must be of type T. Calling this method with the incorrect type is undefined behavior.

Typed
12alloc::boxed::Boxfrom_non_nullmethod

This function is unsafe because improper use may lead to memory problems. For example, a double-free may occur if the function is called twice on the same NonNull pointer.

The non-null pointer must point to a block of memory allocated by the global allocator.

The safety conditions are described in the [memory layout] section. Note that the [considerations for unsafe code] apply to all Box<T> values.

NonNull, Allocated, MayInvalid
13alloc::boxed::Boxfrom_non_null_inmethod

This function is unsafe because improper use may lead to memory problems. For example, a double-free may occur if the function is called twice on the same raw pointer.

The non-null pointer must point to a block of memory allocated by alloc.

The safety conditions are described in the [memory layout] section. Note that the [considerations for unsafe code] apply to all Box<T, A> values.

NonNull, Allocated, MayInvalid
14alloc::boxed::Boxfrom_rawmethod

This function is unsafe because improper use may lead to memory problems. For example, a double-free may occur if the function is called twice on the same raw pointer.

The raw pointer must point to a block of memory allocated by the global allocator.

The safety conditions are described in the [memory layout] section. Note that the [considerations for unsafe code] apply to all Box<T> values.

Allocated, MayInvalid
15alloc::boxed::Boxfrom_raw_inmethod

This function is unsafe because improper use may lead to memory problems. For example, a double-free may occur if the function is called twice on the same raw pointer.

The raw pointer must point to a block of memory allocated by alloc.

The safety conditions are described in the [memory layout] section. Note that the [considerations for unsafe code] apply to all Box<T, A> values.

Allocated, MayInvalid
16alloc::boxed::Boxgrowmethod
  • ptr must denote a block of memory [currently allocated] via this allocator.
  • old_layout must [fit] that block of memory (The new_layout argument need not fit it.).
  • new_layout.size() must be greater than or equal to old_layout.size().

Note that new_layout.align() need not be the same as old_layout.align().

Allocated, ValidNum
17alloc::boxed::Boxgrow_zeroedmethod
  • ptr must denote a block of memory [currently allocated] via this allocator.
  • old_layout must [fit] that block of memory (The new_layout argument need not fit it.).
  • new_layout.size() must be greater than or equal to old_layout.size().

Note that new_layout.align() need not be the same as old_layout.align().

Allocated, ValidNum
18alloc::boxed::Boxshrinkmethod
  • ptr must denote a block of memory [currently allocated] via this allocator.
  • old_layout must [fit] that block of memory (The new_layout argument need not fit it.).
  • new_layout.size() must be smaller than or equal to old_layout.size().

Note that new_layout.align() need not be the same as old_layout.align().

Allocated
19alloc::bstr::ByteStringclone_to_uninitmethod

Behavior is undefined if any of the following conditions are violated:

  • dest must be [valid] for writes for size_of_val(self) bytes.
  • dest must be properly aligned to align_of_val(self).
Align
20alloc::collections::binary_heap::BinaryHeapas_mut_slicemethod

The caller must ensure that the slice remains a max-heap, i.e. for all indices 0 < i < slice.len(), slice[(i - 1) / 2] >= slice[i], before the borrow ends and the binary heap is used.

21alloc::collections::binary_heap::BinaryHeapfrom_raw_vecmethod

The supplied vec must be a max-heap, i.e. for all indices 0 < i < vec.len(), vec[(i - 1) / 2] >= vec[i].

22alloc::collections::btree::map::CursorMutinsert_after_uncheckedmethod

You must ensure that the BTreeMap invariants are maintained. Specifically:

  • The key of the newly inserted element must be unique in the tree.
  • All keys in the tree must remain in sorted order.
23alloc::collections::btree::map::CursorMutinsert_before_uncheckedmethod

You must ensure that the BTreeMap invariants are maintained. Specifically:

  • The key of the newly inserted element must be unique in the tree.
  • All keys in the tree must remain in sorted order.
24alloc::collections::btree::map::CursorMutwith_mutable_keymethod

Since this cursor allows mutating keys, you must ensure that the BTreeMap invariants are maintained. Specifically:

  • The key of the newly inserted element must be unique in the tree.
  • All keys in the tree must remain in sorted order.
25alloc::collections::btree::map::CursorMutKeyinsert_after_uncheckedmethod

You must ensure that the BTreeMap invariants are maintained. Specifically:

  • The key of the newly inserted element must be unique in the tree.
  • All keys in the tree must remain in sorted order.
26alloc::collections::btree::map::CursorMutKeyinsert_before_uncheckedmethod

You must ensure that the BTreeMap invariants are maintained. Specifically:

  • The key of the newly inserted element must be unique in the tree.
  • All keys in the tree must remain in sorted order.
27alloc::collections::btree::set::CursorMutinsert_after_uncheckedmethod

You must ensure that the BTreeSet invariants are maintained. Specifically:

  • The newly inserted element must be unique in the tree.
  • All elements in the tree must remain in sorted order.
28alloc::collections::btree::set::CursorMutinsert_before_uncheckedmethod

You must ensure that the BTreeSet invariants are maintained. Specifically:

  • The newly inserted element must be unique in the tree.
  • All elements in the tree must remain in sorted order.
29alloc::collections::btree::set::CursorMutwith_mutable_keymethod

Since this cursor allows mutating elements, you must ensure that the BTreeSet invariants are maintained. Specifically:

  • The newly inserted element must be unique in the tree.
  • All elements in the tree must remain in sorted order.
30alloc::collections::btree::set::CursorMutKeyinsert_after_uncheckedmethod

You must ensure that the BTreeSet invariants are maintained. Specifically:

  • The key of the newly inserted element must be unique in the tree.
  • All elements in the tree must remain in sorted order.
31alloc::collections::btree::set::CursorMutKeyinsert_before_uncheckedmethod

You must ensure that the BTreeSet invariants are maintained. Specifically:

  • The newly inserted element must be unique in the tree.
  • All elements in the tree must remain in sorted order.
32alloc::ffi::c_str::CStringfrom_rawmethod

This should only ever be called with a pointer that was earlier obtained by calling CString::into_raw, and the memory it points to must not be accessed through any other pointer during the lifetime of reconstructed CString. Other usage (e.g., trying to take ownership of a string that was allocated by foreign code) is likely to lead to undefined behavior or allocator corruption.

This function does not validate ownership of the raw pointer's memory. A double-free may occur if the function is called twice on the same raw pointer. Additionally, the caller must ensure the pointer is not dangling.

It should be noted that the length isn't just "recomputed," but that the recomputed length must match the original length from the CString::into_raw call. This means the CString::into_raw/from_raw methods should not be used when passing the string to C functions that can modify the string's length.

> Note: If you need to borrow a string that was allocated by > foreign code, use CStr. If you need to take ownership of > a string that was allocated by foreign code, you will need to > make your own provisions for freeing it appropriately, likely > with the foreign code's API to do that.

Allocated, Owning, NonAccessable, Forgotten
33alloc::ffi::c_str::CStringfrom_vec_uncheckedmethod

The caller must ensure v contains no nul bytes in its contents.

34alloc::ffi::c_str::CStringfrom_vec_with_nul_uncheckedmethod

The given Vec must have one nul byte as its last element. This means it cannot be empty nor have any other nul byte anywhere else.

35alloc::rc::Rcassume_initmethod

As with MaybeUninit::assume_init, it is up to the caller to guarantee that the inner value really is in an initialized state. Calling this when the content is not yet fully initialized causes immediate undefined behavior.

Init
36alloc::rc::Rcdeallocatemethod
  • ptr must denote a block of memory [currently allocated] via this allocator, and
  • layout must [fit] that block of memory.
Allocated
37alloc::rc::Rcdecrement_strong_countmethod

The pointer must have been obtained through Rc::into_raw and must satisfy the same layout requirements specified in Rc::from_raw_in[from_raw_in]. The associated Rc instance must be valid (i.e. the strong count must be at least 1) when invoking this method, and ptr must point to a block of memory allocated by the global allocator. This method can be used to release the final Rc and backing storage, but should not be called after the final Rc has been released.

Allocated, Forgotten
38alloc::rc::Rcdecrement_strong_count_inmethod

The pointer must have been obtained through Rc::into_rawand must satisfy the same layout requirements specified in Rc::from_raw_in[from_raw_in]. The associated Rc instance must be valid (i.e. the strong count must be at least 1) when invoking this method, and ptr must point to a block of memory allocated by alloc. This method can be used to release the final Rc and backing storage, but should not be called after the final Rc has been released.

Allocated, Forgotten
39alloc::rc::Rcdowncast_uncheckedmethod

The contained value must be of type T. Calling this method with the incorrect type is undefined behavior.

Typed
40alloc::rc::Rcfrom_rawmethod
  • Creating a Rc<T> from a pointer other than one returned from Rc<U>::into_raw[into_raw] or Rc<U>::into_raw_with_allocator[into_raw_with_allocator] is undefined behavior.
  • If U is sized, it must have the same size and alignment as T. This is trivially true if U is T.
  • If U is unsized, its data pointer must have the same size and alignment as T. This is trivially true if Rc<U> was constructed through Rc<T> and then converted to Rc<U> through an [unsized coercion].
  • Note that if U or U's data pointer is not T but has the same size and alignment, this is basically like transmuting references of different types. See mem::transmute[transmute] for more information on what restrictions apply in this case.
  • The raw pointer must point to a block of memory allocated by the global allocator
  • The user of from_raw has to make sure a specific value of T is only dropped once.

This function is unsafe because improper use may lead to memory unsafety, even if the returned Rc<T> is never accessed.

Allocated, MayInvalid, Forgotten
41alloc::rc::Rcfrom_raw_inmethod
  • Creating a Rc<T, A> from a pointer other than one returned from Rc<U, A>::into_raw[into_raw] or Rc<U, A>::into_raw_with_allocator[into_raw_with_allocator] is undefined behavior.
  • If U is sized, it must have the same size and alignment as T. This is trivially true if U is T.
  • If U is unsized, its data pointer must have the same size and alignment as T. This is trivially true if Rc<U, A> was constructed through Rc<T, A> and then converted to Rc<U, A> through an [unsized coercion].
  • Note that if U or U's data pointer is not T but has the same size and alignment, this is basically like transmuting references of different types. See mem::transmute[transmute] for more information on what restrictions apply in this case.
  • The raw pointer must point to a block of memory allocated by alloc
  • The user of from_raw has to make sure a specific value of T is only dropped once.

This function is unsafe because improper use may lead to memory unsafety, even if the returned Rc<T, A> is never accessed.

Allocated, MayInvalid, Forgotten
42alloc::rc::Rcget_mut_uncheckedmethod

If any other Rc or Weak pointers to the same allocation exist, then they must not be dereferenced or have active borrows for the duration of the returned borrow, and their inner type must be exactly the same as the inner type of this Rc (including lifetimes). This is trivially the case if no such pointers exist, for example immediately after Rc::new.

43alloc::rc::Rcgrowmethod
  • ptr must denote a block of memory [currently allocated] via this allocator.
  • old_layout must [fit] that block of memory (The new_layout argument need not fit it.).
  • new_layout.size() must be greater than or equal to old_layout.size().

Note that new_layout.align() need not be the same as old_layout.align().

Allocated, ValidNum
44alloc::rc::Rcgrow_zeroedmethod
  • ptr must denote a block of memory [currently allocated] via this allocator.
  • old_layout must [fit] that block of memory (The new_layout argument need not fit it.).
  • new_layout.size() must be greater than or equal to old_layout.size().

Note that new_layout.align() need not be the same as old_layout.align().

Allocated, ValidNum
45alloc::rc::Rcincrement_strong_countmethod

The pointer must have been obtained through Rc::into_raw and must satisfy the same layout requirements specified in Rc::from_raw_in. The associated Rc instance must be valid (i.e. the strong count must be at least 1) for the duration of this method, and ptr must point to a block of memory allocated by the global allocator.

Allocated, Forgotten
46alloc::rc::Rcincrement_strong_count_inmethod

The pointer must have been obtained through Rc::into_raw and must satisfy the same layout requirements specified in Rc::from_raw_in[from_raw_in]. The associated Rc instance must be valid (i.e. the strong count must be at least 1) for the duration of this method, and ptr must point to a block of memory allocated by alloc.

Allocated, Forgotten
47alloc::rc::Rcshrinkmethod
  • ptr must denote a block of memory [currently allocated] via this allocator.
  • old_layout must [fit] that block of memory (The new_layout argument need not fit it.).
  • new_layout.size() must be smaller than or equal to old_layout.size().

Note that new_layout.align() need not be the same as old_layout.align().

Allocated
48alloc::rc::Weakfrom_rawmethod

The pointer must have originated from the into_raw and must still own its potential weak reference, and ptr must point to a block of memory allocated by the global allocator.

It is allowed for the strong count to be 0 at the time of calling this. Nevertheless, this takes ownership of one weak reference currently represented as a raw pointer (the weak count is not modified by this operation) and therefore it must be paired with a previous call to into_raw.

Allocated, Owning, Forgotten
49alloc::rc::Weakfrom_raw_inmethod

The pointer must have originated from the into_raw and must still own its potential weak reference, and ptr must point to a block of memory allocated by alloc.

It is allowed for the strong count to be 0 at the time of calling this. Nevertheless, this takes ownership of one weak reference currently represented as a raw pointer (the weak count is not modified by this operation) and therefore it must be paired with a previous call to into_raw.

Allocated, Owning, Forgotten
50alloc::strfrom_boxed_utf8_uncheckedfunction
  • The provided bytes must contain a valid UTF-8 sequence.
ValidString
51alloc::string::Stringas_mut_vecmethod

This function is unsafe because the returned &mut Vec allows writing bytes which are not valid UTF-8. If this constraint is violated, using the original String after dropping the &mut Vec may violate memory safety, as the rest of the standard library assumes that Strings are valid UTF-8.

Valid, ValidString
52alloc::string::Stringfrom_raw_partsmethod

This is highly unsafe, due to the number of invariants that aren't checked:

  • all safety requirements for Vec::<u8>::from_raw_parts.
  • all safety requirements for String::from_utf8_unchecked.

Violating these may cause problems like corrupting the allocator's internal data structures. For example, it is normally not safe to build a String from a pointer to a C char array containing UTF-8 _unless_ you are certain that array was originally allocated by the Rust standard library's allocator.

The ownership of buf is effectively transferred to the String which may then deallocate, reallocate or change the contents of memory pointed to by the pointer at will. Ensure that nothing else uses the pointer after calling this function.

Allocated
53alloc::string::Stringfrom_utf8_uncheckedmethod

This function is unsafe because it does not check that the bytes passed to it are valid UTF-8. If this constraint is violated, it may cause memory unsafety issues with future users of the String, as the rest of the standard library assumes that Strings are valid UTF-8.

ValidString
54alloc::sync::Arcassume_initmethod

As with MaybeUninit::assume_init, it is up to the caller to guarantee that the inner value really is in an initialized state. Calling this when the content is not yet fully initialized causes immediate undefined behavior.

Init
55alloc::sync::Arcdeallocatemethod
  • ptr must denote a block of memory [currently allocated] via this allocator, and
  • layout must [fit] that block of memory.
Allocated
56alloc::sync::Arcdecrement_strong_countmethod

The pointer must have been obtained through Arc::into_raw and must satisfy the same layout requirements specified in Arc::from_raw_in[from_raw_in]. The associated Arc instance must be valid (i.e. the strong count must be at least 1) when invoking this method, and ptr must point to a block of memory allocated by the global allocator. This method can be used to release the final Arc and backing storage, but should not be called after the final Arc has been released.

Allocated, Forgotten
57alloc::sync::Arcdecrement_strong_count_inmethod

The pointer must have been obtained through Arc::into_raw and must satisfy the same layout requirements specified in Arc::from_raw_in[from_raw_in]. The associated Arc instance must be valid (i.e. the strong count must be at least 1) when invoking this method, and ptr must point to a block of memory allocated by alloc. This method can be used to release the final Arc and backing storage, but should not be called after the final Arc has been released.

Allocated, Forgotten
58alloc::sync::Arcdowncast_uncheckedmethod

The contained value must be of type T. Calling this method with the incorrect type is undefined behavior.

Typed
59alloc::sync::Arcfrom_rawmethod
  • Creating a Arc<T> from a pointer other than one returned from Arc<U>::into_raw[into_raw] or Arc<U>::into_raw_with_allocator[into_raw_with_allocator] is undefined behavior.
  • If U is sized, it must have the same size and alignment as T. This is trivially true if U is T.
  • If U is unsized, its data pointer must have the same size and alignment as T. This is trivially true if Arc<U> was constructed through Arc<T> and then converted to Arc<U> through an [unsized coercion].
  • Note that if U or U's data pointer is not T but has the same size and alignment, this is basically like transmuting references of different types. See mem::transmute[transmute] for more information on what restrictions apply in this case.
  • The raw pointer must point to a block of memory allocated by the global allocator.
  • The user of from_raw has to make sure a specific value of T is only dropped once.

This function is unsafe because improper use may lead to memory unsafety, even if the returned Arc<T> is never accessed.

Allocated, MayInvalid, Forgotten
60alloc::sync::Arcfrom_raw_inmethod
  • Creating a Arc<T, A> from a pointer other than one returned from Arc<U, A>::into_raw[into_raw] or Arc<U, A>::into_raw_with_allocator[into_raw_with_allocator] is undefined behavior.
  • If U is sized, it must have the same size and alignment as T. This is trivially true if U is T.
  • If U is unsized, its data pointer must have the same size and alignment as T. This is trivially true if Arc<U, A> was constructed through Arc<T, A> and then converted to Arc<U, A> through an [unsized coercion].
  • Note that if U or U's data pointer is not T but has the same size and alignment, this is basically like transmuting references of different types. See mem::transmute[transmute] for more information on what restrictions apply in this case.
  • The raw pointer must point to a block of memory allocated by alloc
  • The user of from_raw has to make sure a specific value of T is only dropped once.

This function is unsafe because improper use may lead to memory unsafety, even if the returned Arc<T> is never accessed.

Allocated, MayInvalid, Forgotten
61alloc::sync::Arcget_mut_uncheckedmethod

If any other Arc or Weak pointers to the same allocation exist, then they must not be dereferenced or have active borrows for the duration of the returned borrow, and their inner type must be exactly the same as the inner type of this Arc (including lifetimes). This is trivially the case if no such pointers exist, for example immediately after Arc::new.

62alloc::sync::Arcgrowmethod
  • ptr must denote a block of memory [currently allocated] via this allocator.
  • old_layout must [fit] that block of memory (The new_layout argument need not fit it.).
  • new_layout.size() must be greater than or equal to old_layout.size().

Note that new_layout.align() need not be the same as old_layout.align().

Allocated, ValidNum
63alloc::sync::Arcgrow_zeroedmethod
  • ptr must denote a block of memory [currently allocated] via this allocator.
  • old_layout must [fit] that block of memory (The new_layout argument need not fit it.).
  • new_layout.size() must be greater than or equal to old_layout.size().

Note that new_layout.align() need not be the same as old_layout.align().

Allocated, ValidNum
64alloc::sync::Arcincrement_strong_countmethod

The pointer must have been obtained through Arc::into_raw and must satisfy the same layout requirements specified in Arc::from_raw_in[from_raw_in]. The associated Arc instance must be valid (i.e. the strong count must be at least 1) for the duration of this method, and ptr must point to a block of memory allocated by the global allocator.

Allocated, Forgotten
65alloc::sync::Arcincrement_strong_count_inmethod

The pointer must have been obtained through Arc::into_raw and must satisfy the same layout requirements specified in Arc::from_raw_in[from_raw_in]. The associated Arc instance must be valid (i.e. the strong count must be at least 1) for the duration of this method, and ptr must point to a block of memory allocated by alloc.

Allocated, Forgotten
66alloc::sync::Arcshrinkmethod
  • ptr must denote a block of memory [currently allocated] via this allocator.
  • old_layout must [fit] that block of memory (The new_layout argument need not fit it.).
  • new_layout.size() must be smaller than or equal to old_layout.size().

Note that new_layout.align() need not be the same as old_layout.align().

Allocated
67alloc::sync::Weakfrom_rawmethod

The pointer must have originated from the into_raw and must still own its potential weak reference, and must point to a block of memory allocated by global allocator.

It is allowed for the strong count to be 0 at the time of calling this. Nevertheless, this takes ownership of one weak reference currently represented as a raw pointer (the weak count is not modified by this operation) and therefore it must be paired with a previous call to into_raw.

Allocated, Owning, Forgotten
68alloc::sync::Weakfrom_raw_inmethod

The pointer must have originated from the into_raw and must still own its potential weak reference, and must point to a block of memory allocated by alloc.

It is allowed for the strong count to be 0 at the time of calling this. Nevertheless, this takes ownership of one weak reference currently represented as a raw pointer (the weak count is not modified by this operation) and therefore it must be paired with a previous call to into_raw.

Allocated, Owning, Forgotten
69alloc::vec::Vecfrom_partsmethod

This is highly unsafe, due to the number of invariants that aren't checked:

  • ptr must have been allocated using the global allocator, such as via the alloc::alloc function.
  • T needs to have the same alignment as what ptr was allocated with. (T having a less strict alignment is not sufficient, the alignment really needs to be equal to satisfy the dealloc requirement that memory must be allocated and deallocated with the same layout.)
  • The size of T times the capacity (i.e. the allocated size in bytes) needs to be the same size as the pointer was allocated with. (Because similar to alignment, dealloc must be called with the same layout size.)
  • length needs to be less than or equal to capacity.
  • The first length values must be properly initialized values of type T.
  • capacity needs to be the capacity that the pointer was allocated with.
  • The allocated size in bytes must be no larger than isize::MAX. See the safety documentation of pointer::offset.

These requirements are always upheld by any ptr that has been allocated via Vec<T>. Other allocation sources are allowed if the invariants are upheld.

Violating these may cause problems like corrupting the allocator's internal data structures. For example it is normally not safe to build a Vec<u8> from a pointer to a C char array with length size_t, doing so is only safe if the array was initially allocated by a Vec or String. It's also not safe to build one from a Vec<u16> and its length, because the allocator cares about the alignment, and these two types have different alignments. The buffer was allocated with alignment 2 (for u16), but after turning it into a Vec<u8> it'll be deallocated with alignment 1. To avoid these issues, it is often preferable to do casting/transmuting using NonNull::slice_from_raw_parts instead.

The ownership of ptr is effectively transferred to the Vec<T> which may then deallocate, reallocate or change the contents of memory pointed to by the pointer at will. Ensure that nothing else uses the pointer after calling this function.

NonNull, Allocated, InBound, Init
70alloc::vec::Vecfrom_parts_inmethod

This is highly unsafe, due to the number of invariants that aren't checked:

  • ptr must be [currently allocated] via the given allocator alloc.
  • T needs to have the same alignment as what ptr was allocated with. (T having a less strict alignment is not sufficient, the alignment really needs to be equal to satisfy the dealloc requirement that memory must be allocated and deallocated with the same layout.)
  • The size of T times the capacity (i.e. the allocated size in bytes) needs to be the same size as the pointer was allocated with. (Because similar to alignment, dealloc must be called with the same layout size.)
  • length needs to be less than or equal to capacity.
  • The first length values must be properly initialized values of type T.
  • capacity needs to [fit] the layout size that the pointer was allocated with.
  • The allocated size in bytes must be no larger than isize::MAX. See the safety documentation of pointer::offset.

These requirements are always upheld by any ptr that has been allocated via Vec<T, A>. Other allocation sources are allowed if the invariants are upheld.

Violating these may cause problems like corrupting the allocator's internal data structures. For example it is not safe to build a Vec<u8> from a pointer to a C char array with length size_t. It's also not safe to build one from a Vec<u16> and its length, because the allocator cares about the alignment, and these two types have different alignments. The buffer was allocated with alignment 2 (for u16), but after turning it into a Vec<u8> it'll be deallocated with alignment 1.

The ownership of ptr is effectively transferred to the Vec<T> which may then deallocate, reallocate or change the contents of memory pointed to by the pointer at will. Ensure that nothing else uses the pointer after calling this function.

Allocated, InBound, Init
71alloc::vec::Vecfrom_raw_partsmethod

This is highly unsafe, due to the number of invariants that aren't checked:

  • If T is not a zero-sized type and the capacity is nonzero, ptr must have been allocated using the global allocator, such as via the alloc::alloc function. If T is a zero-sized type or the capacity is zero, ptr need only be non-null and aligned.
  • T needs to have the same alignment as what ptr was allocated with, if the pointer is required to be allocated. (T having a less strict alignment is not sufficient, the alignment really needs to be equal to satisfy the dealloc requirement that memory must be allocated and deallocated with the same layout.)
  • The size of T times the capacity (i.e. the allocated size in bytes), if nonzero, needs to be the same size as the pointer was allocated with. (Because similar to alignment, dealloc must be called with the same layout size.)
  • length needs to be less than or equal to capacity.
  • The first length values must be properly initialized values of type T.
  • capacity needs to be the capacity that the pointer was allocated with, if the pointer is required to be allocated.
  • The allocated size in bytes must be no larger than isize::MAX. See the safety documentation of pointer::offset.

These requirements are always upheld by any ptr that has been allocated via Vec<T>. Other allocation sources are allowed if the invariants are upheld.

Violating these may cause problems like corrupting the allocator's internal data structures. For example it is normally not safe to build a Vec<u8> from a pointer to a C char array with length size_t, doing so is only safe if the array was initially allocated by a Vec or String. It's also not safe to build one from a Vec<u16> and its length, because the allocator cares about the alignment, and these two types have different alignments. The buffer was allocated with alignment 2 (for u16), but after turning it into a Vec<u8> it'll be deallocated with alignment 1. To avoid these issues, it is often preferable to do casting/transmuting using slice::from_raw_parts instead.

The ownership of ptr is effectively transferred to the Vec<T> which may then deallocate, reallocate or change the contents of memory pointed to by the pointer at will. Ensure that nothing else uses the pointer after calling this function.

NonNull, Allocated, InBound, Init, NonZero
72alloc::vec::Vecfrom_raw_parts_inmethod

This is highly unsafe, due to the number of invariants that aren't checked:

  • ptr must be [currently allocated] via the given allocator alloc.
  • T needs to have the same alignment as what ptr was allocated with. (T having a less strict alignment is not sufficient, the alignment really needs to be equal to satisfy the dealloc requirement that memory must be allocated and deallocated with the same layout.)
  • The size of T times the capacity (i.e. the allocated size in bytes) needs to be the same size as the pointer was allocated with. (Because similar to alignment, dealloc must be called with the same layout size.)
  • length needs to be less than or equal to capacity.
  • The first length values must be properly initialized values of type T.
  • capacity needs to [fit] the layout size that the pointer was allocated with.
  • The allocated size in bytes must be no larger than isize::MAX. See the safety documentation of pointer::offset.

These requirements are always upheld by any ptr that has been allocated via Vec<T, A>. Other allocation sources are allowed if the invariants are upheld.

Violating these may cause problems like corrupting the allocator's internal data structures. For example it is not safe to build a Vec<u8> from a pointer to a C char array with length size_t. It's also not safe to build one from a Vec<u16> and its length, because the allocator cares about the alignment, and these two types have different alignments. The buffer was allocated with alignment 2 (for u16), but after turning it into a Vec<u8> it'll be deallocated with alignment 1.

The ownership of ptr is effectively transferred to the Vec<T> which may then deallocate, reallocate or change the contents of memory pointed to by the pointer at will. Ensure that nothing else uses the pointer after calling this function.

Allocated, InBound, Init
73alloc::vec::Vecset_lenmethod
  • new_len must be less than or equal to capacity().
  • The elements at old_len..new_len must be initialized.
InBound, ValidNum, Init
74core::allocAllocatortrait

Implementors of Allocator must ensure that a memory block that is [currently allocated] by the allocator points to valid memory, until that memory block is [invalidated]. The implementor must also not violate this invariant of Allocator via allocator equivalences that are in the implementor's control (e.g., via a misbehaving impl Clone for Box<MyAllocator>).

Additionally, any memory block returned by the allocator must satisfy the allocation invariants described in core::ptr. In particular, if a block has base address p and size n, then p as usize + n <= usize::MAX must hold.

This ensures that pointer arithmetic within the allocation (for example, ptr.add(len)) cannot overflow the address space.

Allocated
75core::allocGlobalAlloctrait

The GlobalAlloc trait is an unsafe trait for a number of reasons, and implementors must ensure that they adhere to these contracts:

  • It is undefined behavior for the allocator to read, write, or deallocate any memory that is currently allocated. This memory is owned by the user, the allocator must not touch it.
  • It's undefined behavior if global allocators unwind. This restriction may be lifted in the future, but currently a panic from any of these functions may lead to memory unsafety.
  • Callers of this trait are allowed to rely on the contracts defined on each method, and implementors must ensure such contracts remain true.
Allocated, MayInvalid
76core::allocGlobalAllocatortrait

In addition to the safety requirements of Allocator, global allocators are subject to some additional constraints:

  • It's undefined behavior if global allocators unwind. This restriction may be lifted in the future, but currently a panic from any of these functions may lead to memory unsafety.
  • You must not rely on allocations actually happening, even if there are explicit heap allocations in the source. The optimizer may detect unused allocations that it can either eliminate entirely or move to the stack and thus never invoke the allocator. The optimizer may further assume that allocation is infallible, so code that used to fail due to allocator failures may now suddenly work because the optimizer worked around the need for an allocation. More concretely, the following code example is unsound, irrespective of whether your custom allocator allows counting how many allocations have happened.

``rust,ignore (unsound and has placeholders) drop(Box::new(42)); let number_of_heap_allocs = / call private allocator API /; unsafe { std::hint::assert_unchecked(number_of_heap_allocs > 0); } ``

Note that the optimizations mentioned above are not the only optimization that can be applied. You may generally not rely on heap allocations happening if they can be removed without changing program behavior. Whether allocations happen or not is not part of the program behavior, even if it could be detected via an allocator that tracks allocations by printing or otherwise having side effects.

CanFail, MayInvalid
77core::alloc::Allocatordeallocatetrait_method
  • ptr must denote a block of memory [currently allocated] via this allocator, and
  • layout must [fit] that block of memory.
Allocated
78core::alloc::Allocatorgrowtrait_method
  • ptr must denote a block of memory [currently allocated] via this allocator.
  • old_layout must [fit] that block of memory (The new_layout argument need not fit it.).
  • new_layout.size() must be greater than or equal to old_layout.size().

Note that new_layout.align() need not be the same as old_layout.align().

Allocated, ValidNum
79core::alloc::Allocatorgrow_zeroedtrait_method
  • ptr must denote a block of memory [currently allocated] via this allocator.
  • old_layout must [fit] that block of memory (The new_layout argument need not fit it.).
  • new_layout.size() must be greater than or equal to old_layout.size().

Note that new_layout.align() need not be the same as old_layout.align().

Allocated, ValidNum
80core::alloc::Allocatorshrinktrait_method
  • ptr must denote a block of memory [currently allocated] via this allocator.
  • old_layout must [fit] that block of memory (The new_layout argument need not fit it.).
  • new_layout.size() must be smaller than or equal to old_layout.size().

Note that new_layout.align() need not be the same as old_layout.align().

Allocated
81core::alloc::global::GlobalAllocalloctrait_method

layout must have non-zero size. Attempting to allocate for a zero-sized layout will result in undefined behavior.

(Extension subtraits might provide more specific bounds on behavior, e.g., guarantee a sentinel address or a null pointer in response to a zero-size allocation request.)

The allocated block of memory may or may not be initialized.

NonZero
82core::alloc::global::GlobalAllocalloc_zeroedtrait_method

The caller has to ensure that layout has non-zero size. Like alloc zero sized layout will result in undefined behavior. However the allocated block of memory is guaranteed to be initialized.

NonZero
83core::alloc::global::GlobalAllocdealloctrait_method

The caller must ensure:

  • ptr is a block of memory currently allocated via this allocator and,
  • layout is the same layout that was used to allocate that block of memory.

Otherwise the behavior is undefined.

Allocated
84core::alloc::global::GlobalAllocrealloctrait_method

The caller must ensure that:

  • ptr is allocated via this allocator,
  • layout is the same layout that was used to allocate that block of memory,
  • new_size is greater than zero.
  • new_size, when rounded up to the nearest multiple of layout.align(), does not overflow isize (i.e., the rounded value must be less than or equal to isize::MAX).

If these are not followed, the behavior is undefined.

(Extension subtraits might provide more specific bounds on behavior, e.g., guarantee a sentinel address or a null pointer in response to a zero-size allocation request.)

InBound, ValidNum, NonZero
85core::alloc::layout::Layoutfor_value_rawmethod

This function is safe to call if the pointer is safe to reborrow as &T (in which case you could also call for_value[Self::for_value]). Otherwise, the following conditions must hold:

  • If T is Sized, this function is always safe to call.
  • If the unsized tail of T is:
  • a [slice] [U], str, or a [trait object] dyn Trait, then the size of the entire value (dynamic tail length + statically sized prefix) must fit in isize. For the special case where the dynamic tail length is 0, this function is safe to call.
  • No other kind of unsized tail currently exists that satisfies the trait bounds for this function. If more kinds of unsized tails get introduced in the future, the documentation of this function will have to be extended before it can be used for such types.

Here, unsized tail refers to the type obtained by recursively descending through the last field of a tuple or struct until we arrived at a built-in unsized type.

As a consequence of these rules, it is the case that whenever it is allowed to convert val into a shared reference, then it is also allowed to invoke this function.

86core::alloc::layout::Layoutfrom_size_align_uncheckedmethod

This function is unsafe as it does not verify the preconditions from Layout::from_size_align.

87core::alloc::layout::Layoutfrom_size_alignment_uncheckedmethod

This function is unsafe as it does not verify the preconditions from Layout::from_size_alignment.

88core::arrayas_ascii_uncheckedmethod

Every byte in the array must be in 0..=127, or else this is UB.

89core::array::iter::IntoIternew_uncheckedmethod
  • The buffer[initialized] elements must all be initialized.
  • The range must be canonical, with initialized.start <= initialized.end.
  • The range must be in-bounds for the buffer, with initialized.end <= N. (Like how indexing [0][100..100] fails despite the range being empty.)

It's sound to have more elements initialized than mentioned, though that will most likely result in them being leaked.

90core::ascii::ascii_char::AsciiCharbackward_uncheckedmethod

It is undefined behavior for this operation to overflow the range of values supported by Self. If you cannot guarantee that this will not overflow, use backward or backward_checked instead.

91core::ascii::ascii_char::AsciiChardigit_uncheckedmethod

This is immediate UB if called with d > 64.

If d >= 10 and d <= 64, this is allowed to return any value or panic. Notably, it should not be expected to return hex digits, or any other reasonable extension of the decimal digits.

(This loose safety condition is intended to simplify soundness proofs when writing code using this method, since the implementation doesn't need something really specific, not to make those other arguments do something useful. It might be tightened before stabilization.)

92core::ascii::ascii_char::AsciiCharforward_uncheckedmethod

It is undefined behavior for this operation to overflow the range of values supported by Self. If you cannot guarantee that this will not overflow, use forward or forward_checked instead.

93core::ascii::ascii_char::AsciiCharfrom_u8_uncheckedmethod

b must be in 0..=127, or else this is UB.

94core::booldisjoint_bitormethod
95core::bstr::ByteStrclone_to_uninitmethod

Behavior is undefined if any of the following conditions are violated:

  • dest must be [valid] for writes for size_of_val(self) bytes.
  • dest must be properly aligned to align_of_val(self).
Align
96core::cellCloneFromCelltrait

Implementing this trait for a type is sound if and only if the following code is sound for T = that type.

``` #![feature(cell_get_cloned)]

97core::cell::RefCelltry_borrow_unguardedmethod

Unlike RefCell::borrow, this method is unsafe because it does not return a Ref, thus leaving the borrow flag untouched. Mutably borrowing the RefCell while the reference returned by this method is alive is undefined behavior.

98core::cell::UnsafeCellas_mut_uncheckedmethod
  • It is Undefined Behavior to call this while any other reference(s) to the wrapped value are alive.
  • Mutating the wrapped value through other means while the returned reference is alive is Undefined Behavior.
99core::cell::UnsafeCellas_ref_uncheckedmethod
  • It is Undefined Behavior to call this while any mutable reference to the wrapped value is alive.
  • Mutating the wrapped value while the returned reference is alive is Undefined Behavior.
100core::cell::UnsafeCellreplacemethod

The caller must take care to avoid aliasing and data races.

  • It is Undefined Behavior to allow calls to race with any other access to the wrapped value.
  • It is Undefined Behavior to call this while any other reference(s) to the wrapped value are alive.
Alias, NonData_race
101core::charas_ascii_uncheckedmethod

This char must be within the ASCII range, or else this is UB.

InBound
102core::charbackward_uncheckedmethod

It is undefined behavior for this operation to overflow the range of values supported by Self. If you cannot guarantee that this will not overflow, use backward or backward_checked instead.

103core::charforward_uncheckedmethod

It is undefined behavior for this operation to overflow the range of values supported by Self. If you cannot guarantee that this will not overflow, use forward or forward_checked instead.

104core::charfrom_u32_uncheckedfunction
105core::charfrom_u32_uncheckedmethod

This function is unsafe, as it may construct invalid char values.

For a safe version of this function, see the from_u32 function.

106core::cloneCloneToUninittrait

Implementations must ensure that when .clone_to_uninit(dest) returns normally rather than panicking, it always leaves *dest initialized as a valid value of type Self.

107core::cloneTrivialClonetrait

Clone::clone must be equivalent to copying the value, otherwise calling functions such as slice::clone_from_slice can have undefined behaviour.

108core::clone::CloneToUninitclone_to_uninittrait_method

Behavior is undefined if any of the following conditions are violated:

  • dest must be [valid] for writes for size_of_val(self) bytes.
  • dest must be properly aligned to align_of_val(self).
Align
109core::convert::num::CheckedCastFromIntunchecked_cast_fromtrait_method

This results in undefined behavior when value will overflow when converted to this type.

110core::core_arch::aarch64::mte__arm_mte_create_random_tagfunction
111core::core_arch::aarch64::mte__arm_mte_exclude_tagfunction
112core::core_arch::aarch64::mte__arm_mte_get_tagfunction
113core::core_arch::aarch64::mte__arm_mte_increment_tagfunction
114core::core_arch::aarch64::mte__arm_mte_ptrdifffunction
115core::core_arch::aarch64::mte__arm_mte_set_tagfunction
116core::core_arch::aarch64::neonvld1_dup_f64function
117core::core_arch::aarch64::neonvld1_lane_f64function
118core::core_arch::aarch64::neonvld1q_dup_f64function
119core::core_arch::aarch64::neonvld1q_lane_f64function
120core::core_arch::aarch64::neon::generatedvld1_f16function
  • Neon intrinsic unsafe
121core::core_arch::aarch64::neon::generatedvld1_f32function
  • Neon intrinsic unsafe
122core::core_arch::aarch64::neon::generatedvld1_f64function
  • Neon intrinsic unsafe
123core::core_arch::aarch64::neon::generatedvld1_f64_x2function
  • Neon intrinsic unsafe
124core::core_arch::aarch64::neon::generatedvld1_f64_x3function
  • Neon intrinsic unsafe
125core::core_arch::aarch64::neon::generatedvld1_f64_x4function
  • Neon intrinsic unsafe
126core::core_arch::aarch64::neon::generatedvld1_p16function
  • Neon intrinsic unsafe
127core::core_arch::aarch64::neon::generatedvld1_p64function
  • Neon intrinsic unsafe
128core::core_arch::aarch64::neon::generatedvld1_p8function
  • Neon intrinsic unsafe
129core::core_arch::aarch64::neon::generatedvld1_s16function
  • Neon intrinsic unsafe
130core::core_arch::aarch64::neon::generatedvld1_s32function
  • Neon intrinsic unsafe
131core::core_arch::aarch64::neon::generatedvld1_s64function
  • Neon intrinsic unsafe
132core::core_arch::aarch64::neon::generatedvld1_s8function
  • Neon intrinsic unsafe
133core::core_arch::aarch64::neon::generatedvld1_u16function
  • Neon intrinsic unsafe
134core::core_arch::aarch64::neon::generatedvld1_u32function
  • Neon intrinsic unsafe
135core::core_arch::aarch64::neon::generatedvld1_u64function
  • Neon intrinsic unsafe
136core::core_arch::aarch64::neon::generatedvld1_u8function
  • Neon intrinsic unsafe
137core::core_arch::aarch64::neon::generatedvld1q_f16function
  • Neon intrinsic unsafe
138core::core_arch::aarch64::neon::generatedvld1q_f32function
  • Neon intrinsic unsafe
139core::core_arch::aarch64::neon::generatedvld1q_f64function
  • Neon intrinsic unsafe
140core::core_arch::aarch64::neon::generatedvld1q_f64_x2function
  • Neon intrinsic unsafe
141core::core_arch::aarch64::neon::generatedvld1q_f64_x3function
  • Neon intrinsic unsafe
142core::core_arch::aarch64::neon::generatedvld1q_f64_x4function
  • Neon intrinsic unsafe
143core::core_arch::aarch64::neon::generatedvld1q_p16function
  • Neon intrinsic unsafe
144core::core_arch::aarch64::neon::generatedvld1q_p64function
  • Neon intrinsic unsafe
145core::core_arch::aarch64::neon::generatedvld1q_p8function
  • Neon intrinsic unsafe
146core::core_arch::aarch64::neon::generatedvld1q_s16function
  • Neon intrinsic unsafe
147core::core_arch::aarch64::neon::generatedvld1q_s32function
  • Neon intrinsic unsafe
148core::core_arch::aarch64::neon::generatedvld1q_s64function
  • Neon intrinsic unsafe
149core::core_arch::aarch64::neon::generatedvld1q_s8function
  • Neon intrinsic unsafe
150core::core_arch::aarch64::neon::generatedvld1q_u16function
  • Neon intrinsic unsafe
151core::core_arch::aarch64::neon::generatedvld1q_u32function
  • Neon intrinsic unsafe
152core::core_arch::aarch64::neon::generatedvld1q_u64function
  • Neon intrinsic unsafe
153core::core_arch::aarch64::neon::generatedvld1q_u8function
  • Neon intrinsic unsafe
154core::core_arch::aarch64::neon::generatedvld2_dup_f64function
  • Neon intrinsic unsafe
155core::core_arch::aarch64::neon::generatedvld2_f64function
  • Neon intrinsic unsafe
156core::core_arch::aarch64::neon::generatedvld2_lane_f64function
  • Neon intrinsic unsafe
157core::core_arch::aarch64::neon::generatedvld2_lane_p64function
  • Neon intrinsic unsafe
158core::core_arch::aarch64::neon::generatedvld2_lane_s64function
  • Neon intrinsic unsafe
159core::core_arch::aarch64::neon::generatedvld2_lane_u64function
  • Neon intrinsic unsafe
160core::core_arch::aarch64::neon::generatedvld2q_dup_f64function
  • Neon intrinsic unsafe
161core::core_arch::aarch64::neon::generatedvld2q_dup_p64function
  • Neon intrinsic unsafe
162core::core_arch::aarch64::neon::generatedvld2q_dup_s64function
  • Neon intrinsic unsafe
163core::core_arch::aarch64::neon::generatedvld2q_dup_u64function
  • Neon intrinsic unsafe
164core::core_arch::aarch64::neon::generatedvld2q_f64function
  • Neon intrinsic unsafe
165core::core_arch::aarch64::neon::generatedvld2q_lane_f64function
  • Neon intrinsic unsafe
166core::core_arch::aarch64::neon::generatedvld2q_lane_p64function
  • Neon intrinsic unsafe
167core::core_arch::aarch64::neon::generatedvld2q_lane_p8function
  • Neon intrinsic unsafe
168core::core_arch::aarch64::neon::generatedvld2q_lane_s64function
  • Neon intrinsic unsafe
169core::core_arch::aarch64::neon::generatedvld2q_lane_s8function
  • Neon intrinsic unsafe
170core::core_arch::aarch64::neon::generatedvld2q_lane_u64function
  • Neon intrinsic unsafe
171core::core_arch::aarch64::neon::generatedvld2q_lane_u8function
  • Neon intrinsic unsafe
172core::core_arch::aarch64::neon::generatedvld2q_p64function
  • Neon intrinsic unsafe
173core::core_arch::aarch64::neon::generatedvld2q_s64function
  • Neon intrinsic unsafe
174core::core_arch::aarch64::neon::generatedvld2q_u64function
  • Neon intrinsic unsafe
175core::core_arch::aarch64::neon::generatedvld3_dup_f64function
  • Neon intrinsic unsafe
176core::core_arch::aarch64::neon::generatedvld3_f64function
  • Neon intrinsic unsafe
177core::core_arch::aarch64::neon::generatedvld3_lane_f64function
  • Neon intrinsic unsafe
178core::core_arch::aarch64::neon::generatedvld3_lane_p64function
  • Neon intrinsic unsafe
179core::core_arch::aarch64::neon::generatedvld3_lane_s64function
  • Neon intrinsic unsafe
180core::core_arch::aarch64::neon::generatedvld3_lane_u64function
  • Neon intrinsic unsafe
181core::core_arch::aarch64::neon::generatedvld3q_dup_f64function
  • Neon intrinsic unsafe
182core::core_arch::aarch64::neon::generatedvld3q_dup_p64function
  • Neon intrinsic unsafe
183core::core_arch::aarch64::neon::generatedvld3q_dup_s64function
  • Neon intrinsic unsafe
184core::core_arch::aarch64::neon::generatedvld3q_dup_u64function
  • Neon intrinsic unsafe
185core::core_arch::aarch64::neon::generatedvld3q_f64function
  • Neon intrinsic unsafe
186core::core_arch::aarch64::neon::generatedvld3q_lane_f64function
  • Neon intrinsic unsafe
187core::core_arch::aarch64::neon::generatedvld3q_lane_p64function
  • Neon intrinsic unsafe
188core::core_arch::aarch64::neon::generatedvld3q_lane_p8function
  • Neon intrinsic unsafe
189core::core_arch::aarch64::neon::generatedvld3q_lane_s64function
  • Neon intrinsic unsafe
190core::core_arch::aarch64::neon::generatedvld3q_lane_s8function
  • Neon intrinsic unsafe
191core::core_arch::aarch64::neon::generatedvld3q_lane_u64function
  • Neon intrinsic unsafe
192core::core_arch::aarch64::neon::generatedvld3q_lane_u8function
  • Neon intrinsic unsafe
193core::core_arch::aarch64::neon::generatedvld3q_p64function
  • Neon intrinsic unsafe
194core::core_arch::aarch64::neon::generatedvld3q_s64function
  • Neon intrinsic unsafe
195core::core_arch::aarch64::neon::generatedvld3q_u64function
  • Neon intrinsic unsafe
196core::core_arch::aarch64::neon::generatedvld4_dup_f64function
  • Neon intrinsic unsafe
197core::core_arch::aarch64::neon::generatedvld4_f64function
  • Neon intrinsic unsafe
198core::core_arch::aarch64::neon::generatedvld4_lane_f64function
  • Neon intrinsic unsafe
199core::core_arch::aarch64::neon::generatedvld4_lane_p64function
  • Neon intrinsic unsafe
200core::core_arch::aarch64::neon::generatedvld4_lane_s64function
  • Neon intrinsic unsafe
201core::core_arch::aarch64::neon::generatedvld4_lane_u64function
  • Neon intrinsic unsafe
202core::core_arch::aarch64::neon::generatedvld4q_dup_f64function
  • Neon intrinsic unsafe
203core::core_arch::aarch64::neon::generatedvld4q_dup_p64function
  • Neon intrinsic unsafe
204core::core_arch::aarch64::neon::generatedvld4q_dup_s64function
  • Neon intrinsic unsafe
205core::core_arch::aarch64::neon::generatedvld4q_dup_u64function
  • Neon intrinsic unsafe
206core::core_arch::aarch64::neon::generatedvld4q_f64function
  • Neon intrinsic unsafe
207core::core_arch::aarch64::neon::generatedvld4q_lane_f64function
  • Neon intrinsic unsafe
208core::core_arch::aarch64::neon::generatedvld4q_lane_p64function
  • Neon intrinsic unsafe
209core::core_arch::aarch64::neon::generatedvld4q_lane_p8function
  • Neon intrinsic unsafe
210core::core_arch::aarch64::neon::generatedvld4q_lane_s64function
  • Neon intrinsic unsafe
211core::core_arch::aarch64::neon::generatedvld4q_lane_s8function
  • Neon intrinsic unsafe
212core::core_arch::aarch64::neon::generatedvld4q_lane_u64function
  • Neon intrinsic unsafe
213core::core_arch::aarch64::neon::generatedvld4q_lane_u8function
  • Neon intrinsic unsafe
214core::core_arch::aarch64::neon::generatedvld4q_p64function
  • Neon intrinsic unsafe
215core::core_arch::aarch64::neon::generatedvld4q_s64function
  • Neon intrinsic unsafe
216core::core_arch::aarch64::neon::generatedvld4q_u64function
  • Neon intrinsic unsafe
217core::core_arch::aarch64::neon::generatedvldap1_lane_p64function
  • Neon intrinsic unsafe
218core::core_arch::aarch64::neon::generatedvldap1_lane_s64function
  • Neon intrinsic unsafe
219core::core_arch::aarch64::neon::generatedvldap1_lane_u64function
  • Neon intrinsic unsafe
220core::core_arch::aarch64::neon::generatedvldap1q_lane_f64function
  • Neon intrinsic unsafe
221core::core_arch::aarch64::neon::generatedvldap1q_lane_p64function
  • Neon intrinsic unsafe
222core::core_arch::aarch64::neon::generatedvldap1q_lane_s64function
  • Neon intrinsic unsafe
223core::core_arch::aarch64::neon::generatedvldap1q_lane_u64function
  • Neon intrinsic unsafe
224core::core_arch::aarch64::neon::generatedvluti2_lane_f16function
  • Neon intrinsic unsafe
225core::core_arch::aarch64::neon::generatedvluti2_lane_p16function
  • Neon intrinsic unsafe
226core::core_arch::aarch64::neon::generatedvluti2_lane_p8function
  • Neon intrinsic unsafe
227core::core_arch::aarch64::neon::generatedvluti2_lane_s16function
  • Neon intrinsic unsafe
228core::core_arch::aarch64::neon::generatedvluti2_lane_s8function
  • Neon intrinsic unsafe
229core::core_arch::aarch64::neon::generatedvluti2_lane_u16function
  • Neon intrinsic unsafe
230core::core_arch::aarch64::neon::generatedvluti2_lane_u8function
  • Neon intrinsic unsafe
231core::core_arch::aarch64::neon::generatedvluti2_laneq_f16function
  • Neon intrinsic unsafe
232core::core_arch::aarch64::neon::generatedvluti2_laneq_p16function
  • Neon intrinsic unsafe
233core::core_arch::aarch64::neon::generatedvluti2_laneq_p8function
  • Neon intrinsic unsafe
234core::core_arch::aarch64::neon::generatedvluti2_laneq_s16function
  • Neon intrinsic unsafe
235core::core_arch::aarch64::neon::generatedvluti2_laneq_s8function
  • Neon intrinsic unsafe
236core::core_arch::aarch64::neon::generatedvluti2_laneq_u16function
  • Neon intrinsic unsafe
237core::core_arch::aarch64::neon::generatedvluti2_laneq_u8function
  • Neon intrinsic unsafe
238core::core_arch::aarch64::neon::generatedvluti2q_lane_f16function
  • Neon intrinsic unsafe
239core::core_arch::aarch64::neon::generatedvluti2q_lane_p16function
  • Neon intrinsic unsafe
240core::core_arch::aarch64::neon::generatedvluti2q_lane_p8function
  • Neon intrinsic unsafe
241core::core_arch::aarch64::neon::generatedvluti2q_lane_s16function
  • Neon intrinsic unsafe
242core::core_arch::aarch64::neon::generatedvluti2q_lane_s8function
  • Neon intrinsic unsafe
243core::core_arch::aarch64::neon::generatedvluti2q_lane_u16function
  • Neon intrinsic unsafe
244core::core_arch::aarch64::neon::generatedvluti2q_lane_u8function
  • Neon intrinsic unsafe
245core::core_arch::aarch64::neon::generatedvluti2q_laneq_f16function
  • Neon intrinsic unsafe
246core::core_arch::aarch64::neon::generatedvluti2q_laneq_p16function
  • Neon intrinsic unsafe
247core::core_arch::aarch64::neon::generatedvluti2q_laneq_p8function
  • Neon intrinsic unsafe
248core::core_arch::aarch64::neon::generatedvluti2q_laneq_s16function
  • Neon intrinsic unsafe
249core::core_arch::aarch64::neon::generatedvluti2q_laneq_s8function
  • Neon intrinsic unsafe
250core::core_arch::aarch64::neon::generatedvluti2q_laneq_u16function
  • Neon intrinsic unsafe
251core::core_arch::aarch64::neon::generatedvluti2q_laneq_u8function
  • Neon intrinsic unsafe
252core::core_arch::aarch64::neon::generatedvluti4q_lane_f16_x2function
  • Neon intrinsic unsafe
253core::core_arch::aarch64::neon::generatedvluti4q_lane_p16_x2function
  • Neon intrinsic unsafe
254core::core_arch::aarch64::neon::generatedvluti4q_lane_p8function
  • Neon intrinsic unsafe
255core::core_arch::aarch64::neon::generatedvluti4q_lane_s16_x2function
  • Neon intrinsic unsafe
256core::core_arch::aarch64::neon::generatedvluti4q_lane_s8function
  • Neon intrinsic unsafe
257core::core_arch::aarch64::neon::generatedvluti4q_lane_u16_x2function
  • Neon intrinsic unsafe
258core::core_arch::aarch64::neon::generatedvluti4q_lane_u8function
  • Neon intrinsic unsafe
259core::core_arch::aarch64::neon::generatedvluti4q_laneq_f16_x2function
  • Neon intrinsic unsafe
260core::core_arch::aarch64::neon::generatedvluti4q_laneq_p16_x2function
  • Neon intrinsic unsafe
261core::core_arch::aarch64::neon::generatedvluti4q_laneq_p8function
  • Neon intrinsic unsafe
262core::core_arch::aarch64::neon::generatedvluti4q_laneq_s16_x2function
  • Neon intrinsic unsafe
263core::core_arch::aarch64::neon::generatedvluti4q_laneq_s8function
  • Neon intrinsic unsafe
264core::core_arch::aarch64::neon::generatedvluti4q_laneq_u16_x2function
  • Neon intrinsic unsafe
265core::core_arch::aarch64::neon::generatedvluti4q_laneq_u8function
  • Neon intrinsic unsafe
266core::core_arch::aarch64::neon::generatedvst1_f16function
  • Neon intrinsic unsafe
267core::core_arch::aarch64::neon::generatedvst1_f32function
  • Neon intrinsic unsafe
268core::core_arch::aarch64::neon::generatedvst1_f64function
  • Neon intrinsic unsafe
269core::core_arch::aarch64::neon::generatedvst1_f64_x2function
  • Neon intrinsic unsafe
270core::core_arch::aarch64::neon::generatedvst1_f64_x3function
  • Neon intrinsic unsafe
271core::core_arch::aarch64::neon::generatedvst1_f64_x4function
  • Neon intrinsic unsafe
272core::core_arch::aarch64::neon::generatedvst1_lane_f64function
  • Neon intrinsic unsafe
273core::core_arch::aarch64::neon::generatedvst1_p16function
  • Neon intrinsic unsafe
274core::core_arch::aarch64::neon::generatedvst1_p64function
  • Neon intrinsic unsafe
275core::core_arch::aarch64::neon::generatedvst1_p8function
  • Neon intrinsic unsafe
276core::core_arch::aarch64::neon::generatedvst1_s16function
  • Neon intrinsic unsafe
277core::core_arch::aarch64::neon::generatedvst1_s32function
  • Neon intrinsic unsafe
278core::core_arch::aarch64::neon::generatedvst1_s64function
  • Neon intrinsic unsafe
279core::core_arch::aarch64::neon::generatedvst1_s8function
  • Neon intrinsic unsafe
280core::core_arch::aarch64::neon::generatedvst1_u16function
  • Neon intrinsic unsafe
281core::core_arch::aarch64::neon::generatedvst1_u32function
  • Neon intrinsic unsafe
282core::core_arch::aarch64::neon::generatedvst1_u64function
  • Neon intrinsic unsafe
283core::core_arch::aarch64::neon::generatedvst1_u8function
  • Neon intrinsic unsafe
284core::core_arch::aarch64::neon::generatedvst1q_f16function
  • Neon intrinsic unsafe
285core::core_arch::aarch64::neon::generatedvst1q_f32function
  • Neon intrinsic unsafe
286core::core_arch::aarch64::neon::generatedvst1q_f64function
  • Neon intrinsic unsafe
287core::core_arch::aarch64::neon::generatedvst1q_f64_x2function
  • Neon intrinsic unsafe
288core::core_arch::aarch64::neon::generatedvst1q_f64_x3function
  • Neon intrinsic unsafe
289core::core_arch::aarch64::neon::generatedvst1q_f64_x4function
  • Neon intrinsic unsafe
290core::core_arch::aarch64::neon::generatedvst1q_lane_f64function
  • Neon intrinsic unsafe
291core::core_arch::aarch64::neon::generatedvst1q_p16function
  • Neon intrinsic unsafe
292core::core_arch::aarch64::neon::generatedvst1q_p64function
  • Neon intrinsic unsafe
293core::core_arch::aarch64::neon::generatedvst1q_p8function
  • Neon intrinsic unsafe
294core::core_arch::aarch64::neon::generatedvst1q_s16function
  • Neon intrinsic unsafe
295core::core_arch::aarch64::neon::generatedvst1q_s32function
  • Neon intrinsic unsafe
296core::core_arch::aarch64::neon::generatedvst1q_s64function
  • Neon intrinsic unsafe
297core::core_arch::aarch64::neon::generatedvst1q_s8function
  • Neon intrinsic unsafe
298core::core_arch::aarch64::neon::generatedvst1q_u16function
  • Neon intrinsic unsafe
299core::core_arch::aarch64::neon::generatedvst1q_u32function
  • Neon intrinsic unsafe
300core::core_arch::aarch64::neon::generatedvst1q_u64function
  • Neon intrinsic unsafe
301core::core_arch::aarch64::neon::generatedvst1q_u8function
  • Neon intrinsic unsafe
302core::core_arch::aarch64::neon::generatedvst2_f64function
  • Neon intrinsic unsafe
303core::core_arch::aarch64::neon::generatedvst2_lane_f64function
  • Neon intrinsic unsafe
304core::core_arch::aarch64::neon::generatedvst2_lane_p64function
  • Neon intrinsic unsafe
305core::core_arch::aarch64::neon::generatedvst2_lane_s64function
  • Neon intrinsic unsafe
306core::core_arch::aarch64::neon::generatedvst2_lane_u64function
  • Neon intrinsic unsafe
307core::core_arch::aarch64::neon::generatedvst2q_f64function
  • Neon intrinsic unsafe
308core::core_arch::aarch64::neon::generatedvst2q_lane_f64function
  • Neon intrinsic unsafe
309core::core_arch::aarch64::neon::generatedvst2q_lane_p64function
  • Neon intrinsic unsafe
310core::core_arch::aarch64::neon::generatedvst2q_lane_p8function
  • Neon intrinsic unsafe
311core::core_arch::aarch64::neon::generatedvst2q_lane_s64function
  • Neon intrinsic unsafe
312core::core_arch::aarch64::neon::generatedvst2q_lane_s8function
  • Neon intrinsic unsafe
313core::core_arch::aarch64::neon::generatedvst2q_lane_u64function
  • Neon intrinsic unsafe
314core::core_arch::aarch64::neon::generatedvst2q_lane_u8function
  • Neon intrinsic unsafe
315core::core_arch::aarch64::neon::generatedvst2q_p64function
  • Neon intrinsic unsafe
316core::core_arch::aarch64::neon::generatedvst2q_s64function
  • Neon intrinsic unsafe
317core::core_arch::aarch64::neon::generatedvst2q_u64function
  • Neon intrinsic unsafe
318core::core_arch::aarch64::neon::generatedvst3_f64function
  • Neon intrinsic unsafe
319core::core_arch::aarch64::neon::generatedvst3_lane_f64function
  • Neon intrinsic unsafe
320core::core_arch::aarch64::neon::generatedvst3_lane_p64function
  • Neon intrinsic unsafe
321core::core_arch::aarch64::neon::generatedvst3_lane_s64function
  • Neon intrinsic unsafe
322core::core_arch::aarch64::neon::generatedvst3_lane_u64function
  • Neon intrinsic unsafe
323core::core_arch::aarch64::neon::generatedvst3q_f64function
  • Neon intrinsic unsafe
324core::core_arch::aarch64::neon::generatedvst3q_lane_f64function
  • Neon intrinsic unsafe
325core::core_arch::aarch64::neon::generatedvst3q_lane_p64function
  • Neon intrinsic unsafe
326core::core_arch::aarch64::neon::generatedvst3q_lane_p8function
  • Neon intrinsic unsafe
327core::core_arch::aarch64::neon::generatedvst3q_lane_s64function
  • Neon intrinsic unsafe
328core::core_arch::aarch64::neon::generatedvst3q_lane_s8function
  • Neon intrinsic unsafe
329core::core_arch::aarch64::neon::generatedvst3q_lane_u64function
  • Neon intrinsic unsafe
330core::core_arch::aarch64::neon::generatedvst3q_lane_u8function
  • Neon intrinsic unsafe
331core::core_arch::aarch64::neon::generatedvst3q_p64function
  • Neon intrinsic unsafe
332core::core_arch::aarch64::neon::generatedvst3q_s64function
  • Neon intrinsic unsafe
333core::core_arch::aarch64::neon::generatedvst3q_u64function
  • Neon intrinsic unsafe
334core::core_arch::aarch64::neon::generatedvst4_f64function
  • Neon intrinsic unsafe
335core::core_arch::aarch64::neon::generatedvst4_lane_f64function
  • Neon intrinsic unsafe
336core::core_arch::aarch64::neon::generatedvst4_lane_p64function
  • Neon intrinsic unsafe
337core::core_arch::aarch64::neon::generatedvst4_lane_s64function
  • Neon intrinsic unsafe
338core::core_arch::aarch64::neon::generatedvst4_lane_u64function
  • Neon intrinsic unsafe
339core::core_arch::aarch64::neon::generatedvst4q_f64function
  • Neon intrinsic unsafe
340core::core_arch::aarch64::neon::generatedvst4q_lane_f64function
  • Neon intrinsic unsafe
341core::core_arch::aarch64::neon::generatedvst4q_lane_p64function
  • Neon intrinsic unsafe
342core::core_arch::aarch64::neon::generatedvst4q_lane_p8function
  • Neon intrinsic unsafe
343core::core_arch::aarch64::neon::generatedvst4q_lane_s64function
  • Neon intrinsic unsafe
344core::core_arch::aarch64::neon::generatedvst4q_lane_s8function
  • Neon intrinsic unsafe
345core::core_arch::aarch64::neon::generatedvst4q_lane_u64function
  • Neon intrinsic unsafe
346core::core_arch::aarch64::neon::generatedvst4q_lane_u8function
  • Neon intrinsic unsafe
347core::core_arch::aarch64::neon::generatedvst4q_p64function
  • Neon intrinsic unsafe
348core::core_arch::aarch64::neon::generatedvst4q_s64function
  • Neon intrinsic unsafe
349core::core_arch::aarch64::neon::generatedvst4q_u64function
  • Neon intrinsic unsafe
350core::core_arch::aarch64::neon::generatedvstl1_lane_f64function
  • The pointer in ptr must satisfy the requirements of core::ptr::write.
351core::core_arch::aarch64::neon::generatedvstl1_lane_p64function
  • The pointer in ptr must satisfy the requirements of core::ptr::write.
352core::core_arch::aarch64::neon::generatedvstl1_lane_s64function
  • The pointer in ptr must satisfy the requirements of core::ptr::write.
353core::core_arch::aarch64::neon::generatedvstl1_lane_u64function
  • The pointer in ptr must satisfy the requirements of core::ptr::write.
354core::core_arch::aarch64::neon::generatedvstl1q_lane_f64function
  • The pointer in ptr must satisfy the requirements of core::ptr::write.
355core::core_arch::aarch64::neon::generatedvstl1q_lane_p64function
  • The pointer in ptr must satisfy the requirements of core::ptr::write.
356core::core_arch::aarch64::neon::generatedvstl1q_lane_s64function
  • The pointer in ptr must satisfy the requirements of core::ptr::write.
357core::core_arch::aarch64::neon::generatedvstl1q_lane_u64function
  • The pointer in ptr must satisfy the requirements of core::ptr::write.
358core::core_arch::aarch64::prefetch_prefetchfunction
359core::core_arch::aarch64::rand__rndrfunction
360core::core_arch::aarch64::rand__rndrrsfunction
361core::core_arch::aarch64::sve2::generatedsvldnt1_gather_s64index_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
362core::core_arch::aarch64::sve2::generatedsvldnt1_gather_s64index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
363core::core_arch::aarch64::sve2::generatedsvldnt1_gather_s64index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
364core::core_arch::aarch64::sve2::generatedsvldnt1_gather_s64offset_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
365core::core_arch::aarch64::sve2::generatedsvldnt1_gather_s64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
366core::core_arch::aarch64::sve2::generatedsvldnt1_gather_s64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
367core::core_arch::aarch64::sve2::generatedsvldnt1_gather_u32base_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
368core::core_arch::aarch64::sve2::generatedsvldnt1_gather_u32base_index_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
369core::core_arch::aarch64::sve2::generatedsvldnt1_gather_u32base_index_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
370core::core_arch::aarch64::sve2::generatedsvldnt1_gather_u32base_index_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
371core::core_arch::aarch64::sve2::generatedsvldnt1_gather_u32base_offset_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
372core::core_arch::aarch64::sve2::generatedsvldnt1_gather_u32base_offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
373core::core_arch::aarch64::sve2::generatedsvldnt1_gather_u32base_offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
374core::core_arch::aarch64::sve2::generatedsvldnt1_gather_u32base_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
375core::core_arch::aarch64::sve2::generatedsvldnt1_gather_u32base_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
376core::core_arch::aarch64::sve2::generatedsvldnt1_gather_u32offset_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
377core::core_arch::aarch64::sve2::generatedsvldnt1_gather_u32offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
378core::core_arch::aarch64::sve2::generatedsvldnt1_gather_u32offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
379core::core_arch::aarch64::sve2::generatedsvldnt1_gather_u64base_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
380core::core_arch::aarch64::sve2::generatedsvldnt1_gather_u64base_index_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
381core::core_arch::aarch64::sve2::generatedsvldnt1_gather_u64base_index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
382core::core_arch::aarch64::sve2::generatedsvldnt1_gather_u64base_index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
383core::core_arch::aarch64::sve2::generatedsvldnt1_gather_u64base_offset_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
384core::core_arch::aarch64::sve2::generatedsvldnt1_gather_u64base_offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
385core::core_arch::aarch64::sve2::generatedsvldnt1_gather_u64base_offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
386core::core_arch::aarch64::sve2::generatedsvldnt1_gather_u64base_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
387core::core_arch::aarch64::sve2::generatedsvldnt1_gather_u64base_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
388core::core_arch::aarch64::sve2::generatedsvldnt1_gather_u64index_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
389core::core_arch::aarch64::sve2::generatedsvldnt1_gather_u64index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
390core::core_arch::aarch64::sve2::generatedsvldnt1_gather_u64index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
391core::core_arch::aarch64::sve2::generatedsvldnt1_gather_u64offset_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
392core::core_arch::aarch64::sve2::generatedsvldnt1_gather_u64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
393core::core_arch::aarch64::sve2::generatedsvldnt1_gather_u64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
394core::core_arch::aarch64::sve2::generatedsvldnt1sb_gather_s64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
395core::core_arch::aarch64::sve2::generatedsvldnt1sb_gather_s64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
396core::core_arch::aarch64::sve2::generatedsvldnt1sb_gather_u32base_offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
397core::core_arch::aarch64::sve2::generatedsvldnt1sb_gather_u32base_offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
398core::core_arch::aarch64::sve2::generatedsvldnt1sb_gather_u32base_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
399core::core_arch::aarch64::sve2::generatedsvldnt1sb_gather_u32base_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
400core::core_arch::aarch64::sve2::generatedsvldnt1sb_gather_u32offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
401core::core_arch::aarch64::sve2::generatedsvldnt1sb_gather_u32offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
402core::core_arch::aarch64::sve2::generatedsvldnt1sb_gather_u64base_offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
403core::core_arch::aarch64::sve2::generatedsvldnt1sb_gather_u64base_offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
404core::core_arch::aarch64::sve2::generatedsvldnt1sb_gather_u64base_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
405core::core_arch::aarch64::sve2::generatedsvldnt1sb_gather_u64base_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
406core::core_arch::aarch64::sve2::generatedsvldnt1sb_gather_u64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
407core::core_arch::aarch64::sve2::generatedsvldnt1sb_gather_u64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
408core::core_arch::aarch64::sve2::generatedsvldnt1sh_gather_s64index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
409core::core_arch::aarch64::sve2::generatedsvldnt1sh_gather_s64index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
410core::core_arch::aarch64::sve2::generatedsvldnt1sh_gather_s64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
411core::core_arch::aarch64::sve2::generatedsvldnt1sh_gather_s64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
412core::core_arch::aarch64::sve2::generatedsvldnt1sh_gather_u32base_index_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
413core::core_arch::aarch64::sve2::generatedsvldnt1sh_gather_u32base_index_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
414core::core_arch::aarch64::sve2::generatedsvldnt1sh_gather_u32base_offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
415core::core_arch::aarch64::sve2::generatedsvldnt1sh_gather_u32base_offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
416core::core_arch::aarch64::sve2::generatedsvldnt1sh_gather_u32base_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
417core::core_arch::aarch64::sve2::generatedsvldnt1sh_gather_u32base_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
418core::core_arch::aarch64::sve2::generatedsvldnt1sh_gather_u32offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
419core::core_arch::aarch64::sve2::generatedsvldnt1sh_gather_u32offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
420core::core_arch::aarch64::sve2::generatedsvldnt1sh_gather_u64base_index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
421core::core_arch::aarch64::sve2::generatedsvldnt1sh_gather_u64base_index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
422core::core_arch::aarch64::sve2::generatedsvldnt1sh_gather_u64base_offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
423core::core_arch::aarch64::sve2::generatedsvldnt1sh_gather_u64base_offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
424core::core_arch::aarch64::sve2::generatedsvldnt1sh_gather_u64base_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
425core::core_arch::aarch64::sve2::generatedsvldnt1sh_gather_u64base_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
426core::core_arch::aarch64::sve2::generatedsvldnt1sh_gather_u64index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
427core::core_arch::aarch64::sve2::generatedsvldnt1sh_gather_u64index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
428core::core_arch::aarch64::sve2::generatedsvldnt1sh_gather_u64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
429core::core_arch::aarch64::sve2::generatedsvldnt1sh_gather_u64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
430core::core_arch::aarch64::sve2::generatedsvldnt1sw_gather_s64index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
431core::core_arch::aarch64::sve2::generatedsvldnt1sw_gather_s64index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
432core::core_arch::aarch64::sve2::generatedsvldnt1sw_gather_s64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
433core::core_arch::aarch64::sve2::generatedsvldnt1sw_gather_s64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
434core::core_arch::aarch64::sve2::generatedsvldnt1sw_gather_u64base_index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
435core::core_arch::aarch64::sve2::generatedsvldnt1sw_gather_u64base_index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
436core::core_arch::aarch64::sve2::generatedsvldnt1sw_gather_u64base_offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
437core::core_arch::aarch64::sve2::generatedsvldnt1sw_gather_u64base_offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
438core::core_arch::aarch64::sve2::generatedsvldnt1sw_gather_u64base_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
439core::core_arch::aarch64::sve2::generatedsvldnt1sw_gather_u64base_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
440core::core_arch::aarch64::sve2::generatedsvldnt1sw_gather_u64index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
441core::core_arch::aarch64::sve2::generatedsvldnt1sw_gather_u64index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
442core::core_arch::aarch64::sve2::generatedsvldnt1sw_gather_u64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
443core::core_arch::aarch64::sve2::generatedsvldnt1sw_gather_u64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
444core::core_arch::aarch64::sve2::generatedsvldnt1ub_gather_s64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
445core::core_arch::aarch64::sve2::generatedsvldnt1ub_gather_s64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
446core::core_arch::aarch64::sve2::generatedsvldnt1ub_gather_u32base_offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
447core::core_arch::aarch64::sve2::generatedsvldnt1ub_gather_u32base_offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
448core::core_arch::aarch64::sve2::generatedsvldnt1ub_gather_u32base_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
449core::core_arch::aarch64::sve2::generatedsvldnt1ub_gather_u32base_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
450core::core_arch::aarch64::sve2::generatedsvldnt1ub_gather_u32offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
451core::core_arch::aarch64::sve2::generatedsvldnt1ub_gather_u32offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
452core::core_arch::aarch64::sve2::generatedsvldnt1ub_gather_u64base_offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
453core::core_arch::aarch64::sve2::generatedsvldnt1ub_gather_u64base_offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
454core::core_arch::aarch64::sve2::generatedsvldnt1ub_gather_u64base_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
455core::core_arch::aarch64::sve2::generatedsvldnt1ub_gather_u64base_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
456core::core_arch::aarch64::sve2::generatedsvldnt1ub_gather_u64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
457core::core_arch::aarch64::sve2::generatedsvldnt1ub_gather_u64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
458core::core_arch::aarch64::sve2::generatedsvldnt1uh_gather_s64index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
459core::core_arch::aarch64::sve2::generatedsvldnt1uh_gather_s64index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
460core::core_arch::aarch64::sve2::generatedsvldnt1uh_gather_s64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
461core::core_arch::aarch64::sve2::generatedsvldnt1uh_gather_s64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
462core::core_arch::aarch64::sve2::generatedsvldnt1uh_gather_u32base_index_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
463core::core_arch::aarch64::sve2::generatedsvldnt1uh_gather_u32base_index_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
464core::core_arch::aarch64::sve2::generatedsvldnt1uh_gather_u32base_offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
465core::core_arch::aarch64::sve2::generatedsvldnt1uh_gather_u32base_offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
466core::core_arch::aarch64::sve2::generatedsvldnt1uh_gather_u32base_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
467core::core_arch::aarch64::sve2::generatedsvldnt1uh_gather_u32base_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
468core::core_arch::aarch64::sve2::generatedsvldnt1uh_gather_u32offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
469core::core_arch::aarch64::sve2::generatedsvldnt1uh_gather_u32offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
470core::core_arch::aarch64::sve2::generatedsvldnt1uh_gather_u64base_index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
471core::core_arch::aarch64::sve2::generatedsvldnt1uh_gather_u64base_index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
472core::core_arch::aarch64::sve2::generatedsvldnt1uh_gather_u64base_offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
473core::core_arch::aarch64::sve2::generatedsvldnt1uh_gather_u64base_offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
474core::core_arch::aarch64::sve2::generatedsvldnt1uh_gather_u64base_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
475core::core_arch::aarch64::sve2::generatedsvldnt1uh_gather_u64base_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
476core::core_arch::aarch64::sve2::generatedsvldnt1uh_gather_u64index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
477core::core_arch::aarch64::sve2::generatedsvldnt1uh_gather_u64index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
478core::core_arch::aarch64::sve2::generatedsvldnt1uh_gather_u64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
479core::core_arch::aarch64::sve2::generatedsvldnt1uh_gather_u64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
480core::core_arch::aarch64::sve2::generatedsvldnt1uw_gather_s64index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
481core::core_arch::aarch64::sve2::generatedsvldnt1uw_gather_s64index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
482core::core_arch::aarch64::sve2::generatedsvldnt1uw_gather_s64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
483core::core_arch::aarch64::sve2::generatedsvldnt1uw_gather_s64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
484core::core_arch::aarch64::sve2::generatedsvldnt1uw_gather_u64base_index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
485core::core_arch::aarch64::sve2::generatedsvldnt1uw_gather_u64base_index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
486core::core_arch::aarch64::sve2::generatedsvldnt1uw_gather_u64base_offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
487core::core_arch::aarch64::sve2::generatedsvldnt1uw_gather_u64base_offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
488core::core_arch::aarch64::sve2::generatedsvldnt1uw_gather_u64base_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
489core::core_arch::aarch64::sve2::generatedsvldnt1uw_gather_u64base_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
490core::core_arch::aarch64::sve2::generatedsvldnt1uw_gather_u64index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
491core::core_arch::aarch64::sve2::generatedsvldnt1uw_gather_u64index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
492core::core_arch::aarch64::sve2::generatedsvldnt1uw_gather_u64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
493core::core_arch::aarch64::sve2::generatedsvldnt1uw_gather_u64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
494core::core_arch::aarch64::sve2::generatedsvstnt1_scatter_s64index_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
495core::core_arch::aarch64::sve2::generatedsvstnt1_scatter_s64index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
496core::core_arch::aarch64::sve2::generatedsvstnt1_scatter_s64index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
497core::core_arch::aarch64::sve2::generatedsvstnt1_scatter_s64offset_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
498core::core_arch::aarch64::sve2::generatedsvstnt1_scatter_s64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
499core::core_arch::aarch64::sve2::generatedsvstnt1_scatter_s64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
500core::core_arch::aarch64::sve2::generatedsvstnt1_scatter_u32base_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
501core::core_arch::aarch64::sve2::generatedsvstnt1_scatter_u32base_index_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
502core::core_arch::aarch64::sve2::generatedsvstnt1_scatter_u32base_index_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
503core::core_arch::aarch64::sve2::generatedsvstnt1_scatter_u32base_index_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
504core::core_arch::aarch64::sve2::generatedsvstnt1_scatter_u32base_offset_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
505core::core_arch::aarch64::sve2::generatedsvstnt1_scatter_u32base_offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
506core::core_arch::aarch64::sve2::generatedsvstnt1_scatter_u32base_offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
507core::core_arch::aarch64::sve2::generatedsvstnt1_scatter_u32base_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
508core::core_arch::aarch64::sve2::generatedsvstnt1_scatter_u32base_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
509core::core_arch::aarch64::sve2::generatedsvstnt1_scatter_u32offset_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
510core::core_arch::aarch64::sve2::generatedsvstnt1_scatter_u32offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
511core::core_arch::aarch64::sve2::generatedsvstnt1_scatter_u32offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
512core::core_arch::aarch64::sve2::generatedsvstnt1_scatter_u64base_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
513core::core_arch::aarch64::sve2::generatedsvstnt1_scatter_u64base_index_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
514core::core_arch::aarch64::sve2::generatedsvstnt1_scatter_u64base_index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
515core::core_arch::aarch64::sve2::generatedsvstnt1_scatter_u64base_index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
516core::core_arch::aarch64::sve2::generatedsvstnt1_scatter_u64base_offset_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
517core::core_arch::aarch64::sve2::generatedsvstnt1_scatter_u64base_offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
518core::core_arch::aarch64::sve2::generatedsvstnt1_scatter_u64base_offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
519core::core_arch::aarch64::sve2::generatedsvstnt1_scatter_u64base_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
520core::core_arch::aarch64::sve2::generatedsvstnt1_scatter_u64base_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
521core::core_arch::aarch64::sve2::generatedsvstnt1_scatter_u64index_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
522core::core_arch::aarch64::sve2::generatedsvstnt1_scatter_u64index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
523core::core_arch::aarch64::sve2::generatedsvstnt1_scatter_u64index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
524core::core_arch::aarch64::sve2::generatedsvstnt1_scatter_u64offset_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
525core::core_arch::aarch64::sve2::generatedsvstnt1_scatter_u64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
526core::core_arch::aarch64::sve2::generatedsvstnt1_scatter_u64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
527core::core_arch::aarch64::sve2::generatedsvstnt1b_scatter_s64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
528core::core_arch::aarch64::sve2::generatedsvstnt1b_scatter_s64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
529core::core_arch::aarch64::sve2::generatedsvstnt1b_scatter_u32base_offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
530core::core_arch::aarch64::sve2::generatedsvstnt1b_scatter_u32base_offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
531core::core_arch::aarch64::sve2::generatedsvstnt1b_scatter_u32base_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
532core::core_arch::aarch64::sve2::generatedsvstnt1b_scatter_u32base_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
533core::core_arch::aarch64::sve2::generatedsvstnt1b_scatter_u32offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
534core::core_arch::aarch64::sve2::generatedsvstnt1b_scatter_u32offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
535core::core_arch::aarch64::sve2::generatedsvstnt1b_scatter_u64base_offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
536core::core_arch::aarch64::sve2::generatedsvstnt1b_scatter_u64base_offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
537core::core_arch::aarch64::sve2::generatedsvstnt1b_scatter_u64base_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
538core::core_arch::aarch64::sve2::generatedsvstnt1b_scatter_u64base_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
539core::core_arch::aarch64::sve2::generatedsvstnt1b_scatter_u64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
540core::core_arch::aarch64::sve2::generatedsvstnt1b_scatter_u64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
541core::core_arch::aarch64::sve2::generatedsvstnt1h_scatter_s64index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
542core::core_arch::aarch64::sve2::generatedsvstnt1h_scatter_s64index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
543core::core_arch::aarch64::sve2::generatedsvstnt1h_scatter_s64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
544core::core_arch::aarch64::sve2::generatedsvstnt1h_scatter_s64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
545core::core_arch::aarch64::sve2::generatedsvstnt1h_scatter_u32base_index_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
546core::core_arch::aarch64::sve2::generatedsvstnt1h_scatter_u32base_index_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
547core::core_arch::aarch64::sve2::generatedsvstnt1h_scatter_u32base_offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
548core::core_arch::aarch64::sve2::generatedsvstnt1h_scatter_u32base_offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
549core::core_arch::aarch64::sve2::generatedsvstnt1h_scatter_u32base_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
550core::core_arch::aarch64::sve2::generatedsvstnt1h_scatter_u32base_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
551core::core_arch::aarch64::sve2::generatedsvstnt1h_scatter_u32offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
552core::core_arch::aarch64::sve2::generatedsvstnt1h_scatter_u32offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
553core::core_arch::aarch64::sve2::generatedsvstnt1h_scatter_u64base_index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
554core::core_arch::aarch64::sve2::generatedsvstnt1h_scatter_u64base_index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
555core::core_arch::aarch64::sve2::generatedsvstnt1h_scatter_u64base_offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
556core::core_arch::aarch64::sve2::generatedsvstnt1h_scatter_u64base_offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
557core::core_arch::aarch64::sve2::generatedsvstnt1h_scatter_u64base_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
558core::core_arch::aarch64::sve2::generatedsvstnt1h_scatter_u64base_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
559core::core_arch::aarch64::sve2::generatedsvstnt1h_scatter_u64index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
560core::core_arch::aarch64::sve2::generatedsvstnt1h_scatter_u64index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
561core::core_arch::aarch64::sve2::generatedsvstnt1h_scatter_u64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
562core::core_arch::aarch64::sve2::generatedsvstnt1h_scatter_u64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
563core::core_arch::aarch64::sve2::generatedsvstnt1w_scatter_s64index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
564core::core_arch::aarch64::sve2::generatedsvstnt1w_scatter_s64index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
565core::core_arch::aarch64::sve2::generatedsvstnt1w_scatter_s64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
566core::core_arch::aarch64::sve2::generatedsvstnt1w_scatter_s64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
567core::core_arch::aarch64::sve2::generatedsvstnt1w_scatter_u64base_index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
568core::core_arch::aarch64::sve2::generatedsvstnt1w_scatter_u64base_index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
569core::core_arch::aarch64::sve2::generatedsvstnt1w_scatter_u64base_offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
570core::core_arch::aarch64::sve2::generatedsvstnt1w_scatter_u64base_offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
571core::core_arch::aarch64::sve2::generatedsvstnt1w_scatter_u64base_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
572core::core_arch::aarch64::sve2::generatedsvstnt1w_scatter_u64base_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
573core::core_arch::aarch64::sve2::generatedsvstnt1w_scatter_u64index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
574core::core_arch::aarch64::sve2::generatedsvstnt1w_scatter_u64index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
575core::core_arch::aarch64::sve2::generatedsvstnt1w_scatter_u64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
576core::core_arch::aarch64::sve2::generatedsvstnt1w_scatter_u64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
577core::core_arch::aarch64::sve2::generatedsvwhilerw_f32function
  • pointer::byte_offset_from(pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, op1 and op2.
578core::core_arch::aarch64::sve2::generatedsvwhilerw_f64function
  • pointer::byte_offset_from(pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, op1 and op2.
579core::core_arch::aarch64::sve2::generatedsvwhilerw_s16function
  • pointer::byte_offset_from(pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, op1 and op2.
580core::core_arch::aarch64::sve2::generatedsvwhilerw_s32function
  • pointer::byte_offset_from(pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, op1 and op2.
581core::core_arch::aarch64::sve2::generatedsvwhilerw_s64function
  • pointer::byte_offset_from(pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, op1 and op2.
582core::core_arch::aarch64::sve2::generatedsvwhilerw_s8function
  • pointer::byte_offset_from(pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, op1 and op2.
583core::core_arch::aarch64::sve2::generatedsvwhilerw_u16function
  • pointer::byte_offset_from(pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, op1 and op2.
584core::core_arch::aarch64::sve2::generatedsvwhilerw_u32function
  • pointer::byte_offset_from(pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, op1 and op2.
585core::core_arch::aarch64::sve2::generatedsvwhilerw_u64function
  • pointer::byte_offset_from(pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, op1 and op2.
586core::core_arch::aarch64::sve2::generatedsvwhilerw_u8function
  • pointer::byte_offset_from(pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, op1 and op2.
587core::core_arch::aarch64::sve2::generatedsvwhilewr_f32function
  • pointer::byte_offset_from(pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, op1 and op2.
588core::core_arch::aarch64::sve2::generatedsvwhilewr_f64function
  • pointer::byte_offset_from(pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, op1 and op2.
589core::core_arch::aarch64::sve2::generatedsvwhilewr_s16function
  • pointer::byte_offset_from(pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, op1 and op2.
590core::core_arch::aarch64::sve2::generatedsvwhilewr_s32function
  • pointer::byte_offset_from(pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, op1 and op2.
591core::core_arch::aarch64::sve2::generatedsvwhilewr_s64function
  • pointer::byte_offset_from(pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, op1 and op2.
592core::core_arch::aarch64::sve2::generatedsvwhilewr_s8function
  • pointer::byte_offset_from(pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, op1 and op2.
593core::core_arch::aarch64::sve2::generatedsvwhilewr_u16function
  • pointer::byte_offset_from(pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, op1 and op2.
594core::core_arch::aarch64::sve2::generatedsvwhilewr_u32function
  • pointer::byte_offset_from(pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, op1 and op2.
595core::core_arch::aarch64::sve2::generatedsvwhilewr_u64function
  • pointer::byte_offset_from(pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, op1 and op2.
596core::core_arch::aarch64::sve2::generatedsvwhilewr_u8function
  • pointer::byte_offset_from(pointer#method.byte_offset_from) safety constraints must be met for at least the base pointers, op1 and op2.
597core::core_arch::aarch64::sve::generatedsvld1_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
598core::core_arch::aarch64::sve::generatedsvld1_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
599core::core_arch::aarch64::sve::generatedsvld1_gather_s32index_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
600core::core_arch::aarch64::sve::generatedsvld1_gather_s32index_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
601core::core_arch::aarch64::sve::generatedsvld1_gather_s32index_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
602core::core_arch::aarch64::sve::generatedsvld1_gather_s32offset_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
603core::core_arch::aarch64::sve::generatedsvld1_gather_s32offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
604core::core_arch::aarch64::sve::generatedsvld1_gather_s32offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
605core::core_arch::aarch64::sve::generatedsvld1_gather_s64index_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
606core::core_arch::aarch64::sve::generatedsvld1_gather_s64index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
607core::core_arch::aarch64::sve::generatedsvld1_gather_s64index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
608core::core_arch::aarch64::sve::generatedsvld1_gather_s64offset_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
609core::core_arch::aarch64::sve::generatedsvld1_gather_s64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
610core::core_arch::aarch64::sve::generatedsvld1_gather_s64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
611core::core_arch::aarch64::sve::generatedsvld1_gather_u32base_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
612core::core_arch::aarch64::sve::generatedsvld1_gather_u32base_index_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
613core::core_arch::aarch64::sve::generatedsvld1_gather_u32base_index_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
614core::core_arch::aarch64::sve::generatedsvld1_gather_u32base_index_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
615core::core_arch::aarch64::sve::generatedsvld1_gather_u32base_offset_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
616core::core_arch::aarch64::sve::generatedsvld1_gather_u32base_offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
617core::core_arch::aarch64::sve::generatedsvld1_gather_u32base_offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
618core::core_arch::aarch64::sve::generatedsvld1_gather_u32base_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
619core::core_arch::aarch64::sve::generatedsvld1_gather_u32base_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
620core::core_arch::aarch64::sve::generatedsvld1_gather_u32index_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
621core::core_arch::aarch64::sve::generatedsvld1_gather_u32index_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
622core::core_arch::aarch64::sve::generatedsvld1_gather_u32index_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
623core::core_arch::aarch64::sve::generatedsvld1_gather_u32offset_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
624core::core_arch::aarch64::sve::generatedsvld1_gather_u32offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
625core::core_arch::aarch64::sve::generatedsvld1_gather_u32offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
626core::core_arch::aarch64::sve::generatedsvld1_gather_u64base_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
627core::core_arch::aarch64::sve::generatedsvld1_gather_u64base_index_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
628core::core_arch::aarch64::sve::generatedsvld1_gather_u64base_index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
629core::core_arch::aarch64::sve::generatedsvld1_gather_u64base_index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
630core::core_arch::aarch64::sve::generatedsvld1_gather_u64base_offset_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
631core::core_arch::aarch64::sve::generatedsvld1_gather_u64base_offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
632core::core_arch::aarch64::sve::generatedsvld1_gather_u64base_offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
633core::core_arch::aarch64::sve::generatedsvld1_gather_u64base_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
634core::core_arch::aarch64::sve::generatedsvld1_gather_u64base_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
635core::core_arch::aarch64::sve::generatedsvld1_gather_u64index_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
636core::core_arch::aarch64::sve::generatedsvld1_gather_u64index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
637core::core_arch::aarch64::sve::generatedsvld1_gather_u64index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
638core::core_arch::aarch64::sve::generatedsvld1_gather_u64offset_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
639core::core_arch::aarch64::sve::generatedsvld1_gather_u64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
640core::core_arch::aarch64::sve::generatedsvld1_gather_u64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
641core::core_arch::aarch64::sve::generatedsvld1_s16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
642core::core_arch::aarch64::sve::generatedsvld1_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
643core::core_arch::aarch64::sve::generatedsvld1_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
644core::core_arch::aarch64::sve::generatedsvld1_s8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
645core::core_arch::aarch64::sve::generatedsvld1_u16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
646core::core_arch::aarch64::sve::generatedsvld1_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
647core::core_arch::aarch64::sve::generatedsvld1_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
648core::core_arch::aarch64::sve::generatedsvld1_u8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
649core::core_arch::aarch64::sve::generatedsvld1_vnum_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
650core::core_arch::aarch64::sve::generatedsvld1_vnum_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
651core::core_arch::aarch64::sve::generatedsvld1_vnum_s16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
652core::core_arch::aarch64::sve::generatedsvld1_vnum_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
653core::core_arch::aarch64::sve::generatedsvld1_vnum_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
654core::core_arch::aarch64::sve::generatedsvld1_vnum_s8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
655core::core_arch::aarch64::sve::generatedsvld1_vnum_u16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
656core::core_arch::aarch64::sve::generatedsvld1_vnum_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
657core::core_arch::aarch64::sve::generatedsvld1_vnum_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
658core::core_arch::aarch64::sve::generatedsvld1_vnum_u8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
659core::core_arch::aarch64::sve::generatedsvld1ro_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
660core::core_arch::aarch64::sve::generatedsvld1ro_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
661core::core_arch::aarch64::sve::generatedsvld1ro_s16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
662core::core_arch::aarch64::sve::generatedsvld1ro_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
663core::core_arch::aarch64::sve::generatedsvld1ro_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
664core::core_arch::aarch64::sve::generatedsvld1ro_s8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
665core::core_arch::aarch64::sve::generatedsvld1ro_u16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
666core::core_arch::aarch64::sve::generatedsvld1ro_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
667core::core_arch::aarch64::sve::generatedsvld1ro_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
668core::core_arch::aarch64::sve::generatedsvld1ro_u8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
669core::core_arch::aarch64::sve::generatedsvld1rq_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
670core::core_arch::aarch64::sve::generatedsvld1rq_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
671core::core_arch::aarch64::sve::generatedsvld1rq_s16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
672core::core_arch::aarch64::sve::generatedsvld1rq_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
673core::core_arch::aarch64::sve::generatedsvld1rq_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
674core::core_arch::aarch64::sve::generatedsvld1rq_s8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
675core::core_arch::aarch64::sve::generatedsvld1rq_u16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
676core::core_arch::aarch64::sve::generatedsvld1rq_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
677core::core_arch::aarch64::sve::generatedsvld1rq_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
678core::core_arch::aarch64::sve::generatedsvld1rq_u8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
679core::core_arch::aarch64::sve::generatedsvld1sb_gather_s32offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
680core::core_arch::aarch64::sve::generatedsvld1sb_gather_s32offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
681core::core_arch::aarch64::sve::generatedsvld1sb_gather_s64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
682core::core_arch::aarch64::sve::generatedsvld1sb_gather_s64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
683core::core_arch::aarch64::sve::generatedsvld1sb_gather_u32base_offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
684core::core_arch::aarch64::sve::generatedsvld1sb_gather_u32base_offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
685core::core_arch::aarch64::sve::generatedsvld1sb_gather_u32base_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
686core::core_arch::aarch64::sve::generatedsvld1sb_gather_u32base_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
687core::core_arch::aarch64::sve::generatedsvld1sb_gather_u32offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
688core::core_arch::aarch64::sve::generatedsvld1sb_gather_u32offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
689core::core_arch::aarch64::sve::generatedsvld1sb_gather_u64base_offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
690core::core_arch::aarch64::sve::generatedsvld1sb_gather_u64base_offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
691core::core_arch::aarch64::sve::generatedsvld1sb_gather_u64base_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
692core::core_arch::aarch64::sve::generatedsvld1sb_gather_u64base_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
693core::core_arch::aarch64::sve::generatedsvld1sb_gather_u64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
694core::core_arch::aarch64::sve::generatedsvld1sb_gather_u64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
695core::core_arch::aarch64::sve::generatedsvld1sb_s16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
696core::core_arch::aarch64::sve::generatedsvld1sb_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
697core::core_arch::aarch64::sve::generatedsvld1sb_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
698core::core_arch::aarch64::sve::generatedsvld1sb_u16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
699core::core_arch::aarch64::sve::generatedsvld1sb_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
700core::core_arch::aarch64::sve::generatedsvld1sb_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
701core::core_arch::aarch64::sve::generatedsvld1sb_vnum_s16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
702core::core_arch::aarch64::sve::generatedsvld1sb_vnum_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
703core::core_arch::aarch64::sve::generatedsvld1sb_vnum_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
704core::core_arch::aarch64::sve::generatedsvld1sb_vnum_u16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
705core::core_arch::aarch64::sve::generatedsvld1sb_vnum_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
706core::core_arch::aarch64::sve::generatedsvld1sb_vnum_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
707core::core_arch::aarch64::sve::generatedsvld1sh_gather_s32index_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
708core::core_arch::aarch64::sve::generatedsvld1sh_gather_s32index_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
709core::core_arch::aarch64::sve::generatedsvld1sh_gather_s32offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
710core::core_arch::aarch64::sve::generatedsvld1sh_gather_s32offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
711core::core_arch::aarch64::sve::generatedsvld1sh_gather_s64index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
712core::core_arch::aarch64::sve::generatedsvld1sh_gather_s64index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
713core::core_arch::aarch64::sve::generatedsvld1sh_gather_s64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
714core::core_arch::aarch64::sve::generatedsvld1sh_gather_s64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
715core::core_arch::aarch64::sve::generatedsvld1sh_gather_u32base_index_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
716core::core_arch::aarch64::sve::generatedsvld1sh_gather_u32base_index_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
717core::core_arch::aarch64::sve::generatedsvld1sh_gather_u32base_offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
718core::core_arch::aarch64::sve::generatedsvld1sh_gather_u32base_offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
719core::core_arch::aarch64::sve::generatedsvld1sh_gather_u32base_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
720core::core_arch::aarch64::sve::generatedsvld1sh_gather_u32base_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
721core::core_arch::aarch64::sve::generatedsvld1sh_gather_u32index_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
722core::core_arch::aarch64::sve::generatedsvld1sh_gather_u32index_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
723core::core_arch::aarch64::sve::generatedsvld1sh_gather_u32offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
724core::core_arch::aarch64::sve::generatedsvld1sh_gather_u32offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
725core::core_arch::aarch64::sve::generatedsvld1sh_gather_u64base_index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
726core::core_arch::aarch64::sve::generatedsvld1sh_gather_u64base_index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
727core::core_arch::aarch64::sve::generatedsvld1sh_gather_u64base_offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
728core::core_arch::aarch64::sve::generatedsvld1sh_gather_u64base_offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
729core::core_arch::aarch64::sve::generatedsvld1sh_gather_u64base_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
730core::core_arch::aarch64::sve::generatedsvld1sh_gather_u64base_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
731core::core_arch::aarch64::sve::generatedsvld1sh_gather_u64index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
732core::core_arch::aarch64::sve::generatedsvld1sh_gather_u64index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
733core::core_arch::aarch64::sve::generatedsvld1sh_gather_u64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
734core::core_arch::aarch64::sve::generatedsvld1sh_gather_u64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
735core::core_arch::aarch64::sve::generatedsvld1sh_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
736core::core_arch::aarch64::sve::generatedsvld1sh_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
737core::core_arch::aarch64::sve::generatedsvld1sh_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
738core::core_arch::aarch64::sve::generatedsvld1sh_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
739core::core_arch::aarch64::sve::generatedsvld1sh_vnum_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
740core::core_arch::aarch64::sve::generatedsvld1sh_vnum_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
741core::core_arch::aarch64::sve::generatedsvld1sh_vnum_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
742core::core_arch::aarch64::sve::generatedsvld1sh_vnum_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
743core::core_arch::aarch64::sve::generatedsvld1sw_gather_s64index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
744core::core_arch::aarch64::sve::generatedsvld1sw_gather_s64index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
745core::core_arch::aarch64::sve::generatedsvld1sw_gather_s64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
746core::core_arch::aarch64::sve::generatedsvld1sw_gather_s64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
747core::core_arch::aarch64::sve::generatedsvld1sw_gather_u64base_index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
748core::core_arch::aarch64::sve::generatedsvld1sw_gather_u64base_index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
749core::core_arch::aarch64::sve::generatedsvld1sw_gather_u64base_offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
750core::core_arch::aarch64::sve::generatedsvld1sw_gather_u64base_offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
751core::core_arch::aarch64::sve::generatedsvld1sw_gather_u64base_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
752core::core_arch::aarch64::sve::generatedsvld1sw_gather_u64base_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
753core::core_arch::aarch64::sve::generatedsvld1sw_gather_u64index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
754core::core_arch::aarch64::sve::generatedsvld1sw_gather_u64index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
755core::core_arch::aarch64::sve::generatedsvld1sw_gather_u64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
756core::core_arch::aarch64::sve::generatedsvld1sw_gather_u64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
757core::core_arch::aarch64::sve::generatedsvld1sw_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
758core::core_arch::aarch64::sve::generatedsvld1sw_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
759core::core_arch::aarch64::sve::generatedsvld1sw_vnum_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
760core::core_arch::aarch64::sve::generatedsvld1sw_vnum_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
761core::core_arch::aarch64::sve::generatedsvld1ub_gather_s32offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
762core::core_arch::aarch64::sve::generatedsvld1ub_gather_s32offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
763core::core_arch::aarch64::sve::generatedsvld1ub_gather_s64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
764core::core_arch::aarch64::sve::generatedsvld1ub_gather_s64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
765core::core_arch::aarch64::sve::generatedsvld1ub_gather_u32base_offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
766core::core_arch::aarch64::sve::generatedsvld1ub_gather_u32base_offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
767core::core_arch::aarch64::sve::generatedsvld1ub_gather_u32base_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
768core::core_arch::aarch64::sve::generatedsvld1ub_gather_u32base_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
769core::core_arch::aarch64::sve::generatedsvld1ub_gather_u32offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
770core::core_arch::aarch64::sve::generatedsvld1ub_gather_u32offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
771core::core_arch::aarch64::sve::generatedsvld1ub_gather_u64base_offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
772core::core_arch::aarch64::sve::generatedsvld1ub_gather_u64base_offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
773core::core_arch::aarch64::sve::generatedsvld1ub_gather_u64base_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
774core::core_arch::aarch64::sve::generatedsvld1ub_gather_u64base_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
775core::core_arch::aarch64::sve::generatedsvld1ub_gather_u64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
776core::core_arch::aarch64::sve::generatedsvld1ub_gather_u64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
777core::core_arch::aarch64::sve::generatedsvld1ub_s16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
778core::core_arch::aarch64::sve::generatedsvld1ub_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
779core::core_arch::aarch64::sve::generatedsvld1ub_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
780core::core_arch::aarch64::sve::generatedsvld1ub_u16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
781core::core_arch::aarch64::sve::generatedsvld1ub_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
782core::core_arch::aarch64::sve::generatedsvld1ub_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
783core::core_arch::aarch64::sve::generatedsvld1ub_vnum_s16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
784core::core_arch::aarch64::sve::generatedsvld1ub_vnum_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
785core::core_arch::aarch64::sve::generatedsvld1ub_vnum_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
786core::core_arch::aarch64::sve::generatedsvld1ub_vnum_u16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
787core::core_arch::aarch64::sve::generatedsvld1ub_vnum_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
788core::core_arch::aarch64::sve::generatedsvld1ub_vnum_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
789core::core_arch::aarch64::sve::generatedsvld1uh_gather_s32index_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
790core::core_arch::aarch64::sve::generatedsvld1uh_gather_s32index_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
791core::core_arch::aarch64::sve::generatedsvld1uh_gather_s32offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
792core::core_arch::aarch64::sve::generatedsvld1uh_gather_s32offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
793core::core_arch::aarch64::sve::generatedsvld1uh_gather_s64index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
794core::core_arch::aarch64::sve::generatedsvld1uh_gather_s64index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
795core::core_arch::aarch64::sve::generatedsvld1uh_gather_s64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
796core::core_arch::aarch64::sve::generatedsvld1uh_gather_s64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
797core::core_arch::aarch64::sve::generatedsvld1uh_gather_u32base_index_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
798core::core_arch::aarch64::sve::generatedsvld1uh_gather_u32base_index_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
799core::core_arch::aarch64::sve::generatedsvld1uh_gather_u32base_offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
800core::core_arch::aarch64::sve::generatedsvld1uh_gather_u32base_offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
801core::core_arch::aarch64::sve::generatedsvld1uh_gather_u32base_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
802core::core_arch::aarch64::sve::generatedsvld1uh_gather_u32base_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
803core::core_arch::aarch64::sve::generatedsvld1uh_gather_u32index_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
804core::core_arch::aarch64::sve::generatedsvld1uh_gather_u32index_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
805core::core_arch::aarch64::sve::generatedsvld1uh_gather_u32offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
806core::core_arch::aarch64::sve::generatedsvld1uh_gather_u32offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
807core::core_arch::aarch64::sve::generatedsvld1uh_gather_u64base_index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
808core::core_arch::aarch64::sve::generatedsvld1uh_gather_u64base_index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
809core::core_arch::aarch64::sve::generatedsvld1uh_gather_u64base_offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
810core::core_arch::aarch64::sve::generatedsvld1uh_gather_u64base_offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
811core::core_arch::aarch64::sve::generatedsvld1uh_gather_u64base_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
812core::core_arch::aarch64::sve::generatedsvld1uh_gather_u64base_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
813core::core_arch::aarch64::sve::generatedsvld1uh_gather_u64index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
814core::core_arch::aarch64::sve::generatedsvld1uh_gather_u64index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
815core::core_arch::aarch64::sve::generatedsvld1uh_gather_u64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
816core::core_arch::aarch64::sve::generatedsvld1uh_gather_u64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
817core::core_arch::aarch64::sve::generatedsvld1uh_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
818core::core_arch::aarch64::sve::generatedsvld1uh_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
819core::core_arch::aarch64::sve::generatedsvld1uh_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
820core::core_arch::aarch64::sve::generatedsvld1uh_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
821core::core_arch::aarch64::sve::generatedsvld1uh_vnum_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
822core::core_arch::aarch64::sve::generatedsvld1uh_vnum_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
823core::core_arch::aarch64::sve::generatedsvld1uh_vnum_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
824core::core_arch::aarch64::sve::generatedsvld1uh_vnum_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
825core::core_arch::aarch64::sve::generatedsvld1uw_gather_s64index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
826core::core_arch::aarch64::sve::generatedsvld1uw_gather_s64index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
827core::core_arch::aarch64::sve::generatedsvld1uw_gather_s64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
828core::core_arch::aarch64::sve::generatedsvld1uw_gather_s64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
829core::core_arch::aarch64::sve::generatedsvld1uw_gather_u64base_index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
830core::core_arch::aarch64::sve::generatedsvld1uw_gather_u64base_index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
831core::core_arch::aarch64::sve::generatedsvld1uw_gather_u64base_offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
832core::core_arch::aarch64::sve::generatedsvld1uw_gather_u64base_offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
833core::core_arch::aarch64::sve::generatedsvld1uw_gather_u64base_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
834core::core_arch::aarch64::sve::generatedsvld1uw_gather_u64base_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
835core::core_arch::aarch64::sve::generatedsvld1uw_gather_u64index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
836core::core_arch::aarch64::sve::generatedsvld1uw_gather_u64index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
837core::core_arch::aarch64::sve::generatedsvld1uw_gather_u64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
838core::core_arch::aarch64::sve::generatedsvld1uw_gather_u64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
839core::core_arch::aarch64::sve::generatedsvld1uw_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
840core::core_arch::aarch64::sve::generatedsvld1uw_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
841core::core_arch::aarch64::sve::generatedsvld1uw_vnum_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
842core::core_arch::aarch64::sve::generatedsvld1uw_vnum_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
843core::core_arch::aarch64::sve::generatedsvld2_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
844core::core_arch::aarch64::sve::generatedsvld2_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
845core::core_arch::aarch64::sve::generatedsvld2_s16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
846core::core_arch::aarch64::sve::generatedsvld2_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
847core::core_arch::aarch64::sve::generatedsvld2_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
848core::core_arch::aarch64::sve::generatedsvld2_s8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
849core::core_arch::aarch64::sve::generatedsvld2_u16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
850core::core_arch::aarch64::sve::generatedsvld2_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
851core::core_arch::aarch64::sve::generatedsvld2_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
852core::core_arch::aarch64::sve::generatedsvld2_u8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
853core::core_arch::aarch64::sve::generatedsvld2_vnum_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
854core::core_arch::aarch64::sve::generatedsvld2_vnum_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
855core::core_arch::aarch64::sve::generatedsvld2_vnum_s16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
856core::core_arch::aarch64::sve::generatedsvld2_vnum_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
857core::core_arch::aarch64::sve::generatedsvld2_vnum_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
858core::core_arch::aarch64::sve::generatedsvld2_vnum_s8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
859core::core_arch::aarch64::sve::generatedsvld2_vnum_u16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
860core::core_arch::aarch64::sve::generatedsvld2_vnum_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
861core::core_arch::aarch64::sve::generatedsvld2_vnum_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
862core::core_arch::aarch64::sve::generatedsvld2_vnum_u8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
863core::core_arch::aarch64::sve::generatedsvld3_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
864core::core_arch::aarch64::sve::generatedsvld3_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
865core::core_arch::aarch64::sve::generatedsvld3_s16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
866core::core_arch::aarch64::sve::generatedsvld3_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
867core::core_arch::aarch64::sve::generatedsvld3_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
868core::core_arch::aarch64::sve::generatedsvld3_s8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
869core::core_arch::aarch64::sve::generatedsvld3_u16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
870core::core_arch::aarch64::sve::generatedsvld3_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
871core::core_arch::aarch64::sve::generatedsvld3_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
872core::core_arch::aarch64::sve::generatedsvld3_u8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
873core::core_arch::aarch64::sve::generatedsvld3_vnum_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
874core::core_arch::aarch64::sve::generatedsvld3_vnum_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
875core::core_arch::aarch64::sve::generatedsvld3_vnum_s16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
876core::core_arch::aarch64::sve::generatedsvld3_vnum_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
877core::core_arch::aarch64::sve::generatedsvld3_vnum_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
878core::core_arch::aarch64::sve::generatedsvld3_vnum_s8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
879core::core_arch::aarch64::sve::generatedsvld3_vnum_u16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
880core::core_arch::aarch64::sve::generatedsvld3_vnum_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
881core::core_arch::aarch64::sve::generatedsvld3_vnum_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
882core::core_arch::aarch64::sve::generatedsvld3_vnum_u8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
883core::core_arch::aarch64::sve::generatedsvld4_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
884core::core_arch::aarch64::sve::generatedsvld4_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
885core::core_arch::aarch64::sve::generatedsvld4_s16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
886core::core_arch::aarch64::sve::generatedsvld4_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
887core::core_arch::aarch64::sve::generatedsvld4_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
888core::core_arch::aarch64::sve::generatedsvld4_s8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
889core::core_arch::aarch64::sve::generatedsvld4_u16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
890core::core_arch::aarch64::sve::generatedsvld4_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
891core::core_arch::aarch64::sve::generatedsvld4_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
892core::core_arch::aarch64::sve::generatedsvld4_u8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
893core::core_arch::aarch64::sve::generatedsvld4_vnum_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
894core::core_arch::aarch64::sve::generatedsvld4_vnum_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
895core::core_arch::aarch64::sve::generatedsvld4_vnum_s16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
896core::core_arch::aarch64::sve::generatedsvld4_vnum_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
897core::core_arch::aarch64::sve::generatedsvld4_vnum_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
898core::core_arch::aarch64::sve::generatedsvld4_vnum_s8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
899core::core_arch::aarch64::sve::generatedsvld4_vnum_u16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
900core::core_arch::aarch64::sve::generatedsvld4_vnum_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
901core::core_arch::aarch64::sve::generatedsvld4_vnum_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
902core::core_arch::aarch64::sve::generatedsvld4_vnum_u8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
903core::core_arch::aarch64::sve::generatedsvldff1_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
904core::core_arch::aarch64::sve::generatedsvldff1_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
905core::core_arch::aarch64::sve::generatedsvldff1_gather_s32index_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
906core::core_arch::aarch64::sve::generatedsvldff1_gather_s32index_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
907core::core_arch::aarch64::sve::generatedsvldff1_gather_s32index_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
908core::core_arch::aarch64::sve::generatedsvldff1_gather_s32offset_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
909core::core_arch::aarch64::sve::generatedsvldff1_gather_s32offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
910core::core_arch::aarch64::sve::generatedsvldff1_gather_s32offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
911core::core_arch::aarch64::sve::generatedsvldff1_gather_s64index_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
912core::core_arch::aarch64::sve::generatedsvldff1_gather_s64index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
913core::core_arch::aarch64::sve::generatedsvldff1_gather_s64index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
914core::core_arch::aarch64::sve::generatedsvldff1_gather_s64offset_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
915core::core_arch::aarch64::sve::generatedsvldff1_gather_s64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
916core::core_arch::aarch64::sve::generatedsvldff1_gather_s64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
917core::core_arch::aarch64::sve::generatedsvldff1_gather_u32base_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
918core::core_arch::aarch64::sve::generatedsvldff1_gather_u32base_index_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
919core::core_arch::aarch64::sve::generatedsvldff1_gather_u32base_index_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
920core::core_arch::aarch64::sve::generatedsvldff1_gather_u32base_index_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
921core::core_arch::aarch64::sve::generatedsvldff1_gather_u32base_offset_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
922core::core_arch::aarch64::sve::generatedsvldff1_gather_u32base_offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
923core::core_arch::aarch64::sve::generatedsvldff1_gather_u32base_offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
924core::core_arch::aarch64::sve::generatedsvldff1_gather_u32base_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
925core::core_arch::aarch64::sve::generatedsvldff1_gather_u32base_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
926core::core_arch::aarch64::sve::generatedsvldff1_gather_u32index_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
927core::core_arch::aarch64::sve::generatedsvldff1_gather_u32index_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
928core::core_arch::aarch64::sve::generatedsvldff1_gather_u32index_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
929core::core_arch::aarch64::sve::generatedsvldff1_gather_u32offset_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
930core::core_arch::aarch64::sve::generatedsvldff1_gather_u32offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
931core::core_arch::aarch64::sve::generatedsvldff1_gather_u32offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
932core::core_arch::aarch64::sve::generatedsvldff1_gather_u64base_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
933core::core_arch::aarch64::sve::generatedsvldff1_gather_u64base_index_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
934core::core_arch::aarch64::sve::generatedsvldff1_gather_u64base_index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
935core::core_arch::aarch64::sve::generatedsvldff1_gather_u64base_index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
936core::core_arch::aarch64::sve::generatedsvldff1_gather_u64base_offset_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
937core::core_arch::aarch64::sve::generatedsvldff1_gather_u64base_offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
938core::core_arch::aarch64::sve::generatedsvldff1_gather_u64base_offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
939core::core_arch::aarch64::sve::generatedsvldff1_gather_u64base_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
940core::core_arch::aarch64::sve::generatedsvldff1_gather_u64base_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
941core::core_arch::aarch64::sve::generatedsvldff1_gather_u64index_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
942core::core_arch::aarch64::sve::generatedsvldff1_gather_u64index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
943core::core_arch::aarch64::sve::generatedsvldff1_gather_u64index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
944core::core_arch::aarch64::sve::generatedsvldff1_gather_u64offset_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
945core::core_arch::aarch64::sve::generatedsvldff1_gather_u64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
946core::core_arch::aarch64::sve::generatedsvldff1_gather_u64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
947core::core_arch::aarch64::sve::generatedsvldff1_s16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
948core::core_arch::aarch64::sve::generatedsvldff1_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
949core::core_arch::aarch64::sve::generatedsvldff1_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
950core::core_arch::aarch64::sve::generatedsvldff1_s8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
951core::core_arch::aarch64::sve::generatedsvldff1_u16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
952core::core_arch::aarch64::sve::generatedsvldff1_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
953core::core_arch::aarch64::sve::generatedsvldff1_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
954core::core_arch::aarch64::sve::generatedsvldff1_u8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
955core::core_arch::aarch64::sve::generatedsvldff1_vnum_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
956core::core_arch::aarch64::sve::generatedsvldff1_vnum_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
957core::core_arch::aarch64::sve::generatedsvldff1_vnum_s16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
958core::core_arch::aarch64::sve::generatedsvldff1_vnum_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
959core::core_arch::aarch64::sve::generatedsvldff1_vnum_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
960core::core_arch::aarch64::sve::generatedsvldff1_vnum_s8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
961core::core_arch::aarch64::sve::generatedsvldff1_vnum_u16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
962core::core_arch::aarch64::sve::generatedsvldff1_vnum_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
963core::core_arch::aarch64::sve::generatedsvldff1_vnum_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
964core::core_arch::aarch64::sve::generatedsvldff1_vnum_u8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
965core::core_arch::aarch64::sve::generatedsvldff1sb_gather_s32offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
966core::core_arch::aarch64::sve::generatedsvldff1sb_gather_s32offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
967core::core_arch::aarch64::sve::generatedsvldff1sb_gather_s64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
968core::core_arch::aarch64::sve::generatedsvldff1sb_gather_s64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
969core::core_arch::aarch64::sve::generatedsvldff1sb_gather_u32base_offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
970core::core_arch::aarch64::sve::generatedsvldff1sb_gather_u32base_offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
971core::core_arch::aarch64::sve::generatedsvldff1sb_gather_u32base_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
972core::core_arch::aarch64::sve::generatedsvldff1sb_gather_u32base_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
973core::core_arch::aarch64::sve::generatedsvldff1sb_gather_u32offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
974core::core_arch::aarch64::sve::generatedsvldff1sb_gather_u32offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
975core::core_arch::aarch64::sve::generatedsvldff1sb_gather_u64base_offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
976core::core_arch::aarch64::sve::generatedsvldff1sb_gather_u64base_offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
977core::core_arch::aarch64::sve::generatedsvldff1sb_gather_u64base_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
978core::core_arch::aarch64::sve::generatedsvldff1sb_gather_u64base_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
979core::core_arch::aarch64::sve::generatedsvldff1sb_gather_u64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
980core::core_arch::aarch64::sve::generatedsvldff1sb_gather_u64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
981core::core_arch::aarch64::sve::generatedsvldff1sb_s16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
982core::core_arch::aarch64::sve::generatedsvldff1sb_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
983core::core_arch::aarch64::sve::generatedsvldff1sb_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
984core::core_arch::aarch64::sve::generatedsvldff1sb_u16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
985core::core_arch::aarch64::sve::generatedsvldff1sb_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
986core::core_arch::aarch64::sve::generatedsvldff1sb_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
987core::core_arch::aarch64::sve::generatedsvldff1sb_vnum_s16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
988core::core_arch::aarch64::sve::generatedsvldff1sb_vnum_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
989core::core_arch::aarch64::sve::generatedsvldff1sb_vnum_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
990core::core_arch::aarch64::sve::generatedsvldff1sb_vnum_u16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
991core::core_arch::aarch64::sve::generatedsvldff1sb_vnum_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
992core::core_arch::aarch64::sve::generatedsvldff1sb_vnum_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
993core::core_arch::aarch64::sve::generatedsvldff1sh_gather_s32index_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
994core::core_arch::aarch64::sve::generatedsvldff1sh_gather_s32index_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
995core::core_arch::aarch64::sve::generatedsvldff1sh_gather_s32offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
996core::core_arch::aarch64::sve::generatedsvldff1sh_gather_s32offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
997core::core_arch::aarch64::sve::generatedsvldff1sh_gather_s64index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
998core::core_arch::aarch64::sve::generatedsvldff1sh_gather_s64index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
999core::core_arch::aarch64::sve::generatedsvldff1sh_gather_s64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1000core::core_arch::aarch64::sve::generatedsvldff1sh_gather_s64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1001core::core_arch::aarch64::sve::generatedsvldff1sh_gather_u32base_index_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1002core::core_arch::aarch64::sve::generatedsvldff1sh_gather_u32base_index_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1003core::core_arch::aarch64::sve::generatedsvldff1sh_gather_u32base_offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1004core::core_arch::aarch64::sve::generatedsvldff1sh_gather_u32base_offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1005core::core_arch::aarch64::sve::generatedsvldff1sh_gather_u32base_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1006core::core_arch::aarch64::sve::generatedsvldff1sh_gather_u32base_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1007core::core_arch::aarch64::sve::generatedsvldff1sh_gather_u32index_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1008core::core_arch::aarch64::sve::generatedsvldff1sh_gather_u32index_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1009core::core_arch::aarch64::sve::generatedsvldff1sh_gather_u32offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1010core::core_arch::aarch64::sve::generatedsvldff1sh_gather_u32offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1011core::core_arch::aarch64::sve::generatedsvldff1sh_gather_u64base_index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1012core::core_arch::aarch64::sve::generatedsvldff1sh_gather_u64base_index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1013core::core_arch::aarch64::sve::generatedsvldff1sh_gather_u64base_offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1014core::core_arch::aarch64::sve::generatedsvldff1sh_gather_u64base_offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1015core::core_arch::aarch64::sve::generatedsvldff1sh_gather_u64base_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1016core::core_arch::aarch64::sve::generatedsvldff1sh_gather_u64base_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1017core::core_arch::aarch64::sve::generatedsvldff1sh_gather_u64index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1018core::core_arch::aarch64::sve::generatedsvldff1sh_gather_u64index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1019core::core_arch::aarch64::sve::generatedsvldff1sh_gather_u64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1020core::core_arch::aarch64::sve::generatedsvldff1sh_gather_u64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1021core::core_arch::aarch64::sve::generatedsvldff1sh_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1022core::core_arch::aarch64::sve::generatedsvldff1sh_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1023core::core_arch::aarch64::sve::generatedsvldff1sh_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1024core::core_arch::aarch64::sve::generatedsvldff1sh_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1025core::core_arch::aarch64::sve::generatedsvldff1sh_vnum_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1026core::core_arch::aarch64::sve::generatedsvldff1sh_vnum_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1027core::core_arch::aarch64::sve::generatedsvldff1sh_vnum_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1028core::core_arch::aarch64::sve::generatedsvldff1sh_vnum_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1029core::core_arch::aarch64::sve::generatedsvldff1sw_gather_s64index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1030core::core_arch::aarch64::sve::generatedsvldff1sw_gather_s64index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1031core::core_arch::aarch64::sve::generatedsvldff1sw_gather_s64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1032core::core_arch::aarch64::sve::generatedsvldff1sw_gather_s64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1033core::core_arch::aarch64::sve::generatedsvldff1sw_gather_u64base_index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1034core::core_arch::aarch64::sve::generatedsvldff1sw_gather_u64base_index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1035core::core_arch::aarch64::sve::generatedsvldff1sw_gather_u64base_offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1036core::core_arch::aarch64::sve::generatedsvldff1sw_gather_u64base_offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1037core::core_arch::aarch64::sve::generatedsvldff1sw_gather_u64base_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1038core::core_arch::aarch64::sve::generatedsvldff1sw_gather_u64base_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1039core::core_arch::aarch64::sve::generatedsvldff1sw_gather_u64index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1040core::core_arch::aarch64::sve::generatedsvldff1sw_gather_u64index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1041core::core_arch::aarch64::sve::generatedsvldff1sw_gather_u64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1042core::core_arch::aarch64::sve::generatedsvldff1sw_gather_u64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1043core::core_arch::aarch64::sve::generatedsvldff1sw_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1044core::core_arch::aarch64::sve::generatedsvldff1sw_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1045core::core_arch::aarch64::sve::generatedsvldff1sw_vnum_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1046core::core_arch::aarch64::sve::generatedsvldff1sw_vnum_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1047core::core_arch::aarch64::sve::generatedsvldff1ub_gather_s32offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1048core::core_arch::aarch64::sve::generatedsvldff1ub_gather_s32offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1049core::core_arch::aarch64::sve::generatedsvldff1ub_gather_s64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1050core::core_arch::aarch64::sve::generatedsvldff1ub_gather_s64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1051core::core_arch::aarch64::sve::generatedsvldff1ub_gather_u32base_offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1052core::core_arch::aarch64::sve::generatedsvldff1ub_gather_u32base_offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1053core::core_arch::aarch64::sve::generatedsvldff1ub_gather_u32base_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1054core::core_arch::aarch64::sve::generatedsvldff1ub_gather_u32base_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1055core::core_arch::aarch64::sve::generatedsvldff1ub_gather_u32offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1056core::core_arch::aarch64::sve::generatedsvldff1ub_gather_u32offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1057core::core_arch::aarch64::sve::generatedsvldff1ub_gather_u64base_offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1058core::core_arch::aarch64::sve::generatedsvldff1ub_gather_u64base_offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1059core::core_arch::aarch64::sve::generatedsvldff1ub_gather_u64base_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1060core::core_arch::aarch64::sve::generatedsvldff1ub_gather_u64base_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1061core::core_arch::aarch64::sve::generatedsvldff1ub_gather_u64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1062core::core_arch::aarch64::sve::generatedsvldff1ub_gather_u64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1063core::core_arch::aarch64::sve::generatedsvldff1ub_s16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1064core::core_arch::aarch64::sve::generatedsvldff1ub_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1065core::core_arch::aarch64::sve::generatedsvldff1ub_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1066core::core_arch::aarch64::sve::generatedsvldff1ub_u16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1067core::core_arch::aarch64::sve::generatedsvldff1ub_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1068core::core_arch::aarch64::sve::generatedsvldff1ub_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1069core::core_arch::aarch64::sve::generatedsvldff1ub_vnum_s16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1070core::core_arch::aarch64::sve::generatedsvldff1ub_vnum_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1071core::core_arch::aarch64::sve::generatedsvldff1ub_vnum_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1072core::core_arch::aarch64::sve::generatedsvldff1ub_vnum_u16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1073core::core_arch::aarch64::sve::generatedsvldff1ub_vnum_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1074core::core_arch::aarch64::sve::generatedsvldff1ub_vnum_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1075core::core_arch::aarch64::sve::generatedsvldff1uh_gather_s32index_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1076core::core_arch::aarch64::sve::generatedsvldff1uh_gather_s32index_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1077core::core_arch::aarch64::sve::generatedsvldff1uh_gather_s32offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1078core::core_arch::aarch64::sve::generatedsvldff1uh_gather_s32offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1079core::core_arch::aarch64::sve::generatedsvldff1uh_gather_s64index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1080core::core_arch::aarch64::sve::generatedsvldff1uh_gather_s64index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1081core::core_arch::aarch64::sve::generatedsvldff1uh_gather_s64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1082core::core_arch::aarch64::sve::generatedsvldff1uh_gather_s64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1083core::core_arch::aarch64::sve::generatedsvldff1uh_gather_u32base_index_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1084core::core_arch::aarch64::sve::generatedsvldff1uh_gather_u32base_index_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1085core::core_arch::aarch64::sve::generatedsvldff1uh_gather_u32base_offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1086core::core_arch::aarch64::sve::generatedsvldff1uh_gather_u32base_offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1087core::core_arch::aarch64::sve::generatedsvldff1uh_gather_u32base_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1088core::core_arch::aarch64::sve::generatedsvldff1uh_gather_u32base_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1089core::core_arch::aarch64::sve::generatedsvldff1uh_gather_u32index_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1090core::core_arch::aarch64::sve::generatedsvldff1uh_gather_u32index_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1091core::core_arch::aarch64::sve::generatedsvldff1uh_gather_u32offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1092core::core_arch::aarch64::sve::generatedsvldff1uh_gather_u32offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1093core::core_arch::aarch64::sve::generatedsvldff1uh_gather_u64base_index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1094core::core_arch::aarch64::sve::generatedsvldff1uh_gather_u64base_index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1095core::core_arch::aarch64::sve::generatedsvldff1uh_gather_u64base_offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1096core::core_arch::aarch64::sve::generatedsvldff1uh_gather_u64base_offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1097core::core_arch::aarch64::sve::generatedsvldff1uh_gather_u64base_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1098core::core_arch::aarch64::sve::generatedsvldff1uh_gather_u64base_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1099core::core_arch::aarch64::sve::generatedsvldff1uh_gather_u64index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1100core::core_arch::aarch64::sve::generatedsvldff1uh_gather_u64index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1101core::core_arch::aarch64::sve::generatedsvldff1uh_gather_u64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1102core::core_arch::aarch64::sve::generatedsvldff1uh_gather_u64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1103core::core_arch::aarch64::sve::generatedsvldff1uh_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1104core::core_arch::aarch64::sve::generatedsvldff1uh_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1105core::core_arch::aarch64::sve::generatedsvldff1uh_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1106core::core_arch::aarch64::sve::generatedsvldff1uh_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1107core::core_arch::aarch64::sve::generatedsvldff1uh_vnum_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1108core::core_arch::aarch64::sve::generatedsvldff1uh_vnum_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1109core::core_arch::aarch64::sve::generatedsvldff1uh_vnum_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1110core::core_arch::aarch64::sve::generatedsvldff1uh_vnum_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1111core::core_arch::aarch64::sve::generatedsvldff1uw_gather_s64index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1112core::core_arch::aarch64::sve::generatedsvldff1uw_gather_s64index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1113core::core_arch::aarch64::sve::generatedsvldff1uw_gather_s64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1114core::core_arch::aarch64::sve::generatedsvldff1uw_gather_s64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1115core::core_arch::aarch64::sve::generatedsvldff1uw_gather_u64base_index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1116core::core_arch::aarch64::sve::generatedsvldff1uw_gather_u64base_index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1117core::core_arch::aarch64::sve::generatedsvldff1uw_gather_u64base_offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1118core::core_arch::aarch64::sve::generatedsvldff1uw_gather_u64base_offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1119core::core_arch::aarch64::sve::generatedsvldff1uw_gather_u64base_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1120core::core_arch::aarch64::sve::generatedsvldff1uw_gather_u64base_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1121core::core_arch::aarch64::sve::generatedsvldff1uw_gather_u64index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1122core::core_arch::aarch64::sve::generatedsvldff1uw_gather_u64index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1123core::core_arch::aarch64::sve::generatedsvldff1uw_gather_u64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1124core::core_arch::aarch64::sve::generatedsvldff1uw_gather_u64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1125core::core_arch::aarch64::sve::generatedsvldff1uw_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1126core::core_arch::aarch64::sve::generatedsvldff1uw_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1127core::core_arch::aarch64::sve::generatedsvldff1uw_vnum_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1128core::core_arch::aarch64::sve::generatedsvldff1uw_vnum_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and first-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1129core::core_arch::aarch64::sve::generatedsvldnf1_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1130core::core_arch::aarch64::sve::generatedsvldnf1_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1131core::core_arch::aarch64::sve::generatedsvldnf1_s16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1132core::core_arch::aarch64::sve::generatedsvldnf1_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1133core::core_arch::aarch64::sve::generatedsvldnf1_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1134core::core_arch::aarch64::sve::generatedsvldnf1_s8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1135core::core_arch::aarch64::sve::generatedsvldnf1_u16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1136core::core_arch::aarch64::sve::generatedsvldnf1_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1137core::core_arch::aarch64::sve::generatedsvldnf1_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1138core::core_arch::aarch64::sve::generatedsvldnf1_u8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1139core::core_arch::aarch64::sve::generatedsvldnf1_vnum_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1140core::core_arch::aarch64::sve::generatedsvldnf1_vnum_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1141core::core_arch::aarch64::sve::generatedsvldnf1_vnum_s16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1142core::core_arch::aarch64::sve::generatedsvldnf1_vnum_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1143core::core_arch::aarch64::sve::generatedsvldnf1_vnum_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1144core::core_arch::aarch64::sve::generatedsvldnf1_vnum_s8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1145core::core_arch::aarch64::sve::generatedsvldnf1_vnum_u16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1146core::core_arch::aarch64::sve::generatedsvldnf1_vnum_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1147core::core_arch::aarch64::sve::generatedsvldnf1_vnum_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1148core::core_arch::aarch64::sve::generatedsvldnf1_vnum_u8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1149core::core_arch::aarch64::sve::generatedsvldnf1sb_s16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1150core::core_arch::aarch64::sve::generatedsvldnf1sb_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1151core::core_arch::aarch64::sve::generatedsvldnf1sb_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1152core::core_arch::aarch64::sve::generatedsvldnf1sb_u16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1153core::core_arch::aarch64::sve::generatedsvldnf1sb_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1154core::core_arch::aarch64::sve::generatedsvldnf1sb_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1155core::core_arch::aarch64::sve::generatedsvldnf1sb_vnum_s16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1156core::core_arch::aarch64::sve::generatedsvldnf1sb_vnum_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1157core::core_arch::aarch64::sve::generatedsvldnf1sb_vnum_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1158core::core_arch::aarch64::sve::generatedsvldnf1sb_vnum_u16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1159core::core_arch::aarch64::sve::generatedsvldnf1sb_vnum_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1160core::core_arch::aarch64::sve::generatedsvldnf1sb_vnum_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1161core::core_arch::aarch64::sve::generatedsvldnf1sh_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1162core::core_arch::aarch64::sve::generatedsvldnf1sh_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1163core::core_arch::aarch64::sve::generatedsvldnf1sh_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1164core::core_arch::aarch64::sve::generatedsvldnf1sh_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1165core::core_arch::aarch64::sve::generatedsvldnf1sh_vnum_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1166core::core_arch::aarch64::sve::generatedsvldnf1sh_vnum_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1167core::core_arch::aarch64::sve::generatedsvldnf1sh_vnum_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1168core::core_arch::aarch64::sve::generatedsvldnf1sh_vnum_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1169core::core_arch::aarch64::sve::generatedsvldnf1sw_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1170core::core_arch::aarch64::sve::generatedsvldnf1sw_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1171core::core_arch::aarch64::sve::generatedsvldnf1sw_vnum_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1172core::core_arch::aarch64::sve::generatedsvldnf1sw_vnum_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1173core::core_arch::aarch64::sve::generatedsvldnf1ub_s16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1174core::core_arch::aarch64::sve::generatedsvldnf1ub_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1175core::core_arch::aarch64::sve::generatedsvldnf1ub_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1176core::core_arch::aarch64::sve::generatedsvldnf1ub_u16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1177core::core_arch::aarch64::sve::generatedsvldnf1ub_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1178core::core_arch::aarch64::sve::generatedsvldnf1ub_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1179core::core_arch::aarch64::sve::generatedsvldnf1ub_vnum_s16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1180core::core_arch::aarch64::sve::generatedsvldnf1ub_vnum_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1181core::core_arch::aarch64::sve::generatedsvldnf1ub_vnum_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1182core::core_arch::aarch64::sve::generatedsvldnf1ub_vnum_u16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1183core::core_arch::aarch64::sve::generatedsvldnf1ub_vnum_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1184core::core_arch::aarch64::sve::generatedsvldnf1ub_vnum_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1185core::core_arch::aarch64::sve::generatedsvldnf1uh_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1186core::core_arch::aarch64::sve::generatedsvldnf1uh_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1187core::core_arch::aarch64::sve::generatedsvldnf1uh_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1188core::core_arch::aarch64::sve::generatedsvldnf1uh_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1189core::core_arch::aarch64::sve::generatedsvldnf1uh_vnum_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1190core::core_arch::aarch64::sve::generatedsvldnf1uh_vnum_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1191core::core_arch::aarch64::sve::generatedsvldnf1uh_vnum_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1192core::core_arch::aarch64::sve::generatedsvldnf1uh_vnum_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1193core::core_arch::aarch64::sve::generatedsvldnf1uw_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1194core::core_arch::aarch64::sve::generatedsvldnf1uw_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1195core::core_arch::aarch64::sve::generatedsvldnf1uw_vnum_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1196core::core_arch::aarch64::sve::generatedsvldnf1uw_vnum_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg, the first-fault register (FFR) and non-faulting behaviour).
  • Result lanes corresponding to inactive FFR lanes (either before or as a result of this intrinsic) have "CONSTRAINED UNPREDICTABLE" values, irrespective of predication. Refer to architectural documentation for details.
1197core::core_arch::aarch64::sve::generatedsvldnt1_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
1198core::core_arch::aarch64::sve::generatedsvldnt1_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
1199core::core_arch::aarch64::sve::generatedsvldnt1_s16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
1200core::core_arch::aarch64::sve::generatedsvldnt1_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
1201core::core_arch::aarch64::sve::generatedsvldnt1_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
1202core::core_arch::aarch64::sve::generatedsvldnt1_s8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
1203core::core_arch::aarch64::sve::generatedsvldnt1_u16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
1204core::core_arch::aarch64::sve::generatedsvldnt1_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
1205core::core_arch::aarch64::sve::generatedsvldnt1_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
1206core::core_arch::aarch64::sve::generatedsvldnt1_u8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
1207core::core_arch::aarch64::sve::generatedsvldnt1_vnum_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
1208core::core_arch::aarch64::sve::generatedsvldnt1_vnum_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
1209core::core_arch::aarch64::sve::generatedsvldnt1_vnum_s16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
1210core::core_arch::aarch64::sve::generatedsvldnt1_vnum_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
1211core::core_arch::aarch64::sve::generatedsvldnt1_vnum_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
1212core::core_arch::aarch64::sve::generatedsvldnt1_vnum_s8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
1213core::core_arch::aarch64::sve::generatedsvldnt1_vnum_u16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
1214core::core_arch::aarch64::sve::generatedsvldnt1_vnum_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
1215core::core_arch::aarch64::sve::generatedsvldnt1_vnum_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
1216core::core_arch::aarch64::sve::generatedsvldnt1_vnum_u8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
1217core::core_arch::aarch64::sve::generatedsvprfbfunction
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
1218core::core_arch::aarch64::sve::generatedsvprfb_gather_s32offsetfunction
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
1219core::core_arch::aarch64::sve::generatedsvprfb_gather_s64offsetfunction
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
1220core::core_arch::aarch64::sve::generatedsvprfb_gather_u32basefunction
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1221core::core_arch::aarch64::sve::generatedsvprfb_gather_u32base_offsetfunction
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1222core::core_arch::aarch64::sve::generatedsvprfb_gather_u32offsetfunction
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
1223core::core_arch::aarch64::sve::generatedsvprfb_gather_u64basefunction
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1224core::core_arch::aarch64::sve::generatedsvprfb_gather_u64base_offsetfunction
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1225core::core_arch::aarch64::sve::generatedsvprfb_gather_u64offsetfunction
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
1226core::core_arch::aarch64::sve::generatedsvprfb_vnumfunction
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
1227core::core_arch::aarch64::sve::generatedsvprfdfunction
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
1228core::core_arch::aarch64::sve::generatedsvprfd_gather_s32indexfunction
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
1229core::core_arch::aarch64::sve::generatedsvprfd_gather_s64indexfunction
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
1230core::core_arch::aarch64::sve::generatedsvprfd_gather_u32basefunction
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1231core::core_arch::aarch64::sve::generatedsvprfd_gather_u32base_indexfunction
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1232core::core_arch::aarch64::sve::generatedsvprfd_gather_u32indexfunction
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
1233core::core_arch::aarch64::sve::generatedsvprfd_gather_u64basefunction
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1234core::core_arch::aarch64::sve::generatedsvprfd_gather_u64base_indexfunction
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1235core::core_arch::aarch64::sve::generatedsvprfd_gather_u64indexfunction
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
1236core::core_arch::aarch64::sve::generatedsvprfd_vnumfunction
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
1237core::core_arch::aarch64::sve::generatedsvprfhfunction
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
1238core::core_arch::aarch64::sve::generatedsvprfh_gather_s32indexfunction
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
1239core::core_arch::aarch64::sve::generatedsvprfh_gather_s64indexfunction
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
1240core::core_arch::aarch64::sve::generatedsvprfh_gather_u32basefunction
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1241core::core_arch::aarch64::sve::generatedsvprfh_gather_u32base_indexfunction
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1242core::core_arch::aarch64::sve::generatedsvprfh_gather_u32indexfunction
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
1243core::core_arch::aarch64::sve::generatedsvprfh_gather_u64basefunction
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1244core::core_arch::aarch64::sve::generatedsvprfh_gather_u64base_indexfunction
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1245core::core_arch::aarch64::sve::generatedsvprfh_gather_u64indexfunction
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
1246core::core_arch::aarch64::sve::generatedsvprfh_vnumfunction
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
1247core::core_arch::aarch64::sve::generatedsvprfwfunction
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
1248core::core_arch::aarch64::sve::generatedsvprfw_gather_s32indexfunction
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
1249core::core_arch::aarch64::sve::generatedsvprfw_gather_s64indexfunction
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
1250core::core_arch::aarch64::sve::generatedsvprfw_gather_u32basefunction
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1251core::core_arch::aarch64::sve::generatedsvprfw_gather_u32base_indexfunction
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1252core::core_arch::aarch64::sve::generatedsvprfw_gather_u32indexfunction
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
1253core::core_arch::aarch64::sve::generatedsvprfw_gather_u64basefunction
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1254core::core_arch::aarch64::sve::generatedsvprfw_gather_u64base_indexfunction
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1255core::core_arch::aarch64::sve::generatedsvprfw_gather_u64indexfunction
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
1256core::core_arch::aarch64::sve::generatedsvprfw_vnumfunction
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
1257core::core_arch::aarch64::sve::generatedsvst1_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1258core::core_arch::aarch64::sve::generatedsvst1_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1259core::core_arch::aarch64::sve::generatedsvst1_s16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1260core::core_arch::aarch64::sve::generatedsvst1_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1261core::core_arch::aarch64::sve::generatedsvst1_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1262core::core_arch::aarch64::sve::generatedsvst1_s8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1263core::core_arch::aarch64::sve::generatedsvst1_scatter_s32index_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1264core::core_arch::aarch64::sve::generatedsvst1_scatter_s32index_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1265core::core_arch::aarch64::sve::generatedsvst1_scatter_s32index_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1266core::core_arch::aarch64::sve::generatedsvst1_scatter_s32offset_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1267core::core_arch::aarch64::sve::generatedsvst1_scatter_s32offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1268core::core_arch::aarch64::sve::generatedsvst1_scatter_s32offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1269core::core_arch::aarch64::sve::generatedsvst1_scatter_s64index_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1270core::core_arch::aarch64::sve::generatedsvst1_scatter_s64index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1271core::core_arch::aarch64::sve::generatedsvst1_scatter_s64index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1272core::core_arch::aarch64::sve::generatedsvst1_scatter_s64offset_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1273core::core_arch::aarch64::sve::generatedsvst1_scatter_s64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1274core::core_arch::aarch64::sve::generatedsvst1_scatter_s64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1275core::core_arch::aarch64::sve::generatedsvst1_scatter_u32base_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1276core::core_arch::aarch64::sve::generatedsvst1_scatter_u32base_index_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1277core::core_arch::aarch64::sve::generatedsvst1_scatter_u32base_index_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1278core::core_arch::aarch64::sve::generatedsvst1_scatter_u32base_index_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1279core::core_arch::aarch64::sve::generatedsvst1_scatter_u32base_offset_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1280core::core_arch::aarch64::sve::generatedsvst1_scatter_u32base_offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1281core::core_arch::aarch64::sve::generatedsvst1_scatter_u32base_offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1282core::core_arch::aarch64::sve::generatedsvst1_scatter_u32base_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1283core::core_arch::aarch64::sve::generatedsvst1_scatter_u32base_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1284core::core_arch::aarch64::sve::generatedsvst1_scatter_u32index_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1285core::core_arch::aarch64::sve::generatedsvst1_scatter_u32index_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1286core::core_arch::aarch64::sve::generatedsvst1_scatter_u32index_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1287core::core_arch::aarch64::sve::generatedsvst1_scatter_u32offset_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1288core::core_arch::aarch64::sve::generatedsvst1_scatter_u32offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1289core::core_arch::aarch64::sve::generatedsvst1_scatter_u32offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1290core::core_arch::aarch64::sve::generatedsvst1_scatter_u64base_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1291core::core_arch::aarch64::sve::generatedsvst1_scatter_u64base_index_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1292core::core_arch::aarch64::sve::generatedsvst1_scatter_u64base_index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1293core::core_arch::aarch64::sve::generatedsvst1_scatter_u64base_index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1294core::core_arch::aarch64::sve::generatedsvst1_scatter_u64base_offset_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1295core::core_arch::aarch64::sve::generatedsvst1_scatter_u64base_offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1296core::core_arch::aarch64::sve::generatedsvst1_scatter_u64base_offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1297core::core_arch::aarch64::sve::generatedsvst1_scatter_u64base_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1298core::core_arch::aarch64::sve::generatedsvst1_scatter_u64base_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1299core::core_arch::aarch64::sve::generatedsvst1_scatter_u64index_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1300core::core_arch::aarch64::sve::generatedsvst1_scatter_u64index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1301core::core_arch::aarch64::sve::generatedsvst1_scatter_u64index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1302core::core_arch::aarch64::sve::generatedsvst1_scatter_u64offset_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1303core::core_arch::aarch64::sve::generatedsvst1_scatter_u64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1304core::core_arch::aarch64::sve::generatedsvst1_scatter_u64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1305core::core_arch::aarch64::sve::generatedsvst1_u16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1306core::core_arch::aarch64::sve::generatedsvst1_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1307core::core_arch::aarch64::sve::generatedsvst1_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1308core::core_arch::aarch64::sve::generatedsvst1_u8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1309core::core_arch::aarch64::sve::generatedsvst1_vnum_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1310core::core_arch::aarch64::sve::generatedsvst1_vnum_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1311core::core_arch::aarch64::sve::generatedsvst1_vnum_s16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1312core::core_arch::aarch64::sve::generatedsvst1_vnum_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1313core::core_arch::aarch64::sve::generatedsvst1_vnum_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1314core::core_arch::aarch64::sve::generatedsvst1_vnum_s8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1315core::core_arch::aarch64::sve::generatedsvst1_vnum_u16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1316core::core_arch::aarch64::sve::generatedsvst1_vnum_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1317core::core_arch::aarch64::sve::generatedsvst1_vnum_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1318core::core_arch::aarch64::sve::generatedsvst1_vnum_u8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1319core::core_arch::aarch64::sve::generatedsvst1b_s16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1320core::core_arch::aarch64::sve::generatedsvst1b_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1321core::core_arch::aarch64::sve::generatedsvst1b_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1322core::core_arch::aarch64::sve::generatedsvst1b_scatter_s32offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1323core::core_arch::aarch64::sve::generatedsvst1b_scatter_s32offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1324core::core_arch::aarch64::sve::generatedsvst1b_scatter_s64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1325core::core_arch::aarch64::sve::generatedsvst1b_scatter_s64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1326core::core_arch::aarch64::sve::generatedsvst1b_scatter_u32base_offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1327core::core_arch::aarch64::sve::generatedsvst1b_scatter_u32base_offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1328core::core_arch::aarch64::sve::generatedsvst1b_scatter_u32base_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1329core::core_arch::aarch64::sve::generatedsvst1b_scatter_u32base_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1330core::core_arch::aarch64::sve::generatedsvst1b_scatter_u32offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1331core::core_arch::aarch64::sve::generatedsvst1b_scatter_u32offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1332core::core_arch::aarch64::sve::generatedsvst1b_scatter_u64base_offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1333core::core_arch::aarch64::sve::generatedsvst1b_scatter_u64base_offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1334core::core_arch::aarch64::sve::generatedsvst1b_scatter_u64base_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1335core::core_arch::aarch64::sve::generatedsvst1b_scatter_u64base_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1336core::core_arch::aarch64::sve::generatedsvst1b_scatter_u64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1337core::core_arch::aarch64::sve::generatedsvst1b_scatter_u64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1338core::core_arch::aarch64::sve::generatedsvst1b_u16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1339core::core_arch::aarch64::sve::generatedsvst1b_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1340core::core_arch::aarch64::sve::generatedsvst1b_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1341core::core_arch::aarch64::sve::generatedsvst1b_vnum_s16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1342core::core_arch::aarch64::sve::generatedsvst1b_vnum_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1343core::core_arch::aarch64::sve::generatedsvst1b_vnum_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1344core::core_arch::aarch64::sve::generatedsvst1b_vnum_u16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1345core::core_arch::aarch64::sve::generatedsvst1b_vnum_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1346core::core_arch::aarch64::sve::generatedsvst1b_vnum_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1347core::core_arch::aarch64::sve::generatedsvst1h_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1348core::core_arch::aarch64::sve::generatedsvst1h_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1349core::core_arch::aarch64::sve::generatedsvst1h_scatter_s32index_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1350core::core_arch::aarch64::sve::generatedsvst1h_scatter_s32index_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1351core::core_arch::aarch64::sve::generatedsvst1h_scatter_s32offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1352core::core_arch::aarch64::sve::generatedsvst1h_scatter_s32offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1353core::core_arch::aarch64::sve::generatedsvst1h_scatter_s64index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1354core::core_arch::aarch64::sve::generatedsvst1h_scatter_s64index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1355core::core_arch::aarch64::sve::generatedsvst1h_scatter_s64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1356core::core_arch::aarch64::sve::generatedsvst1h_scatter_s64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1357core::core_arch::aarch64::sve::generatedsvst1h_scatter_u32base_index_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1358core::core_arch::aarch64::sve::generatedsvst1h_scatter_u32base_index_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1359core::core_arch::aarch64::sve::generatedsvst1h_scatter_u32base_offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1360core::core_arch::aarch64::sve::generatedsvst1h_scatter_u32base_offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1361core::core_arch::aarch64::sve::generatedsvst1h_scatter_u32base_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1362core::core_arch::aarch64::sve::generatedsvst1h_scatter_u32base_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1363core::core_arch::aarch64::sve::generatedsvst1h_scatter_u32index_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1364core::core_arch::aarch64::sve::generatedsvst1h_scatter_u32index_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1365core::core_arch::aarch64::sve::generatedsvst1h_scatter_u32offset_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1366core::core_arch::aarch64::sve::generatedsvst1h_scatter_u32offset_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1367core::core_arch::aarch64::sve::generatedsvst1h_scatter_u64base_index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1368core::core_arch::aarch64::sve::generatedsvst1h_scatter_u64base_index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1369core::core_arch::aarch64::sve::generatedsvst1h_scatter_u64base_offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1370core::core_arch::aarch64::sve::generatedsvst1h_scatter_u64base_offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1371core::core_arch::aarch64::sve::generatedsvst1h_scatter_u64base_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1372core::core_arch::aarch64::sve::generatedsvst1h_scatter_u64base_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1373core::core_arch::aarch64::sve::generatedsvst1h_scatter_u64index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1374core::core_arch::aarch64::sve::generatedsvst1h_scatter_u64index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1375core::core_arch::aarch64::sve::generatedsvst1h_scatter_u64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1376core::core_arch::aarch64::sve::generatedsvst1h_scatter_u64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1377core::core_arch::aarch64::sve::generatedsvst1h_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1378core::core_arch::aarch64::sve::generatedsvst1h_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1379core::core_arch::aarch64::sve::generatedsvst1h_vnum_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1380core::core_arch::aarch64::sve::generatedsvst1h_vnum_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1381core::core_arch::aarch64::sve::generatedsvst1h_vnum_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1382core::core_arch::aarch64::sve::generatedsvst1h_vnum_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1383core::core_arch::aarch64::sve::generatedsvst1w_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1384core::core_arch::aarch64::sve::generatedsvst1w_scatter_s64index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1385core::core_arch::aarch64::sve::generatedsvst1w_scatter_s64index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1386core::core_arch::aarch64::sve::generatedsvst1w_scatter_s64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1387core::core_arch::aarch64::sve::generatedsvst1w_scatter_s64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1388core::core_arch::aarch64::sve::generatedsvst1w_scatter_u64base_index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1389core::core_arch::aarch64::sve::generatedsvst1w_scatter_u64base_index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1390core::core_arch::aarch64::sve::generatedsvst1w_scatter_u64base_offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1391core::core_arch::aarch64::sve::generatedsvst1w_scatter_u64base_offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1392core::core_arch::aarch64::sve::generatedsvst1w_scatter_u64base_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1393core::core_arch::aarch64::sve::generatedsvst1w_scatter_u64base_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Addresses passed in bases lack provenance, so this is similar to using a usize as ptr cast (or core::ptr::with_exposed_provenance) on each lane before using it.
1394core::core_arch::aarch64::sve::generatedsvst1w_scatter_u64index_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1395core::core_arch::aarch64::sve::generatedsvst1w_scatter_u64index_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1396core::core_arch::aarch64::sve::generatedsvst1w_scatter_u64offset_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1397core::core_arch::aarch64::sve::generatedsvst1w_scatter_u64offset_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1398core::core_arch::aarch64::sve::generatedsvst1w_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1399core::core_arch::aarch64::sve::generatedsvst1w_vnum_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1400core::core_arch::aarch64::sve::generatedsvst1w_vnum_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1401core::core_arch::aarch64::sve::generatedsvst2_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1402core::core_arch::aarch64::sve::generatedsvst2_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1403core::core_arch::aarch64::sve::generatedsvst2_s16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1404core::core_arch::aarch64::sve::generatedsvst2_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1405core::core_arch::aarch64::sve::generatedsvst2_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1406core::core_arch::aarch64::sve::generatedsvst2_s8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1407core::core_arch::aarch64::sve::generatedsvst2_u16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1408core::core_arch::aarch64::sve::generatedsvst2_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1409core::core_arch::aarch64::sve::generatedsvst2_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1410core::core_arch::aarch64::sve::generatedsvst2_u8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1411core::core_arch::aarch64::sve::generatedsvst2_vnum_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1412core::core_arch::aarch64::sve::generatedsvst2_vnum_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1413core::core_arch::aarch64::sve::generatedsvst2_vnum_s16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1414core::core_arch::aarch64::sve::generatedsvst2_vnum_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1415core::core_arch::aarch64::sve::generatedsvst2_vnum_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1416core::core_arch::aarch64::sve::generatedsvst2_vnum_s8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1417core::core_arch::aarch64::sve::generatedsvst2_vnum_u16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1418core::core_arch::aarch64::sve::generatedsvst2_vnum_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1419core::core_arch::aarch64::sve::generatedsvst2_vnum_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1420core::core_arch::aarch64::sve::generatedsvst2_vnum_u8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1421core::core_arch::aarch64::sve::generatedsvst3_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1422core::core_arch::aarch64::sve::generatedsvst3_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1423core::core_arch::aarch64::sve::generatedsvst3_s16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1424core::core_arch::aarch64::sve::generatedsvst3_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1425core::core_arch::aarch64::sve::generatedsvst3_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1426core::core_arch::aarch64::sve::generatedsvst3_s8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1427core::core_arch::aarch64::sve::generatedsvst3_u16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1428core::core_arch::aarch64::sve::generatedsvst3_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1429core::core_arch::aarch64::sve::generatedsvst3_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1430core::core_arch::aarch64::sve::generatedsvst3_u8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1431core::core_arch::aarch64::sve::generatedsvst3_vnum_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1432core::core_arch::aarch64::sve::generatedsvst3_vnum_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1433core::core_arch::aarch64::sve::generatedsvst3_vnum_s16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1434core::core_arch::aarch64::sve::generatedsvst3_vnum_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1435core::core_arch::aarch64::sve::generatedsvst3_vnum_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1436core::core_arch::aarch64::sve::generatedsvst3_vnum_s8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1437core::core_arch::aarch64::sve::generatedsvst3_vnum_u16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1438core::core_arch::aarch64::sve::generatedsvst3_vnum_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1439core::core_arch::aarch64::sve::generatedsvst3_vnum_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1440core::core_arch::aarch64::sve::generatedsvst3_vnum_u8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1441core::core_arch::aarch64::sve::generatedsvst4_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1442core::core_arch::aarch64::sve::generatedsvst4_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1443core::core_arch::aarch64::sve::generatedsvst4_s16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1444core::core_arch::aarch64::sve::generatedsvst4_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1445core::core_arch::aarch64::sve::generatedsvst4_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1446core::core_arch::aarch64::sve::generatedsvst4_s8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1447core::core_arch::aarch64::sve::generatedsvst4_u16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1448core::core_arch::aarch64::sve::generatedsvst4_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1449core::core_arch::aarch64::sve::generatedsvst4_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1450core::core_arch::aarch64::sve::generatedsvst4_u8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1451core::core_arch::aarch64::sve::generatedsvst4_vnum_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1452core::core_arch::aarch64::sve::generatedsvst4_vnum_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1453core::core_arch::aarch64::sve::generatedsvst4_vnum_s16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1454core::core_arch::aarch64::sve::generatedsvst4_vnum_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1455core::core_arch::aarch64::sve::generatedsvst4_vnum_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1456core::core_arch::aarch64::sve::generatedsvst4_vnum_s8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1457core::core_arch::aarch64::sve::generatedsvst4_vnum_u16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1458core::core_arch::aarch64::sve::generatedsvst4_vnum_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1459core::core_arch::aarch64::sve::generatedsvst4_vnum_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1460core::core_arch::aarch64::sve::generatedsvst4_vnum_u8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg). In particular, note that vnum is scaled by the vector length, VL, which is not known at compile time.
  • This dereferences and accesses the calculated address for each active element (governed by pg).
1461core::core_arch::aarch64::sve::generatedsvstnt1_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
1462core::core_arch::aarch64::sve::generatedsvstnt1_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
1463core::core_arch::aarch64::sve::generatedsvstnt1_s16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
1464core::core_arch::aarch64::sve::generatedsvstnt1_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
1465core::core_arch::aarch64::sve::generatedsvstnt1_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
1466core::core_arch::aarch64::sve::generatedsvstnt1_s8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
1467core::core_arch::aarch64::sve::generatedsvstnt1_u16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
1468core::core_arch::aarch64::sve::generatedsvstnt1_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
1469core::core_arch::aarch64::sve::generatedsvstnt1_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
1470core::core_arch::aarch64::sve::generatedsvstnt1_u8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
1471core::core_arch::aarch64::sve::generatedsvstnt1_vnum_f32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
1472core::core_arch::aarch64::sve::generatedsvstnt1_vnum_f64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
1473core::core_arch::aarch64::sve::generatedsvstnt1_vnum_s16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
1474core::core_arch::aarch64::sve::generatedsvstnt1_vnum_s32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
1475core::core_arch::aarch64::sve::generatedsvstnt1_vnum_s64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
1476core::core_arch::aarch64::sve::generatedsvstnt1_vnum_s8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
1477core::core_arch::aarch64::sve::generatedsvstnt1_vnum_u16function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
1478core::core_arch::aarch64::sve::generatedsvstnt1_vnum_u32function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
1479core::core_arch::aarch64::sve::generatedsvstnt1_vnum_u64function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
1480core::core_arch::aarch64::sve::generatedsvstnt1_vnum_u8function
  • pointer::offset(pointer#method.offset) safety constraints must be met for the address calculation for each active element (governed by pg).
  • This dereferences and accesses the calculated address for each active element (governed by pg).
  • Non-temporal accesses have special memory ordering rules, and explicit barriers may be required for some applications.
1481core::core_arch::aarch64::sve::generatedsvundef2_f32function
  • This creates an uninitialized value, and may be unsound (like core::mem::uninitialized).
1482core::core_arch::aarch64::sve::generatedsvundef2_f64function
  • This creates an uninitialized value, and may be unsound (like core::mem::uninitialized).
1483core::core_arch::aarch64::sve::generatedsvundef2_s16function
  • This creates an uninitialized value, and may be unsound (like core::mem::uninitialized).
1484core::core_arch::aarch64::sve::generatedsvundef2_s32function
  • This creates an uninitialized value, and may be unsound (like core::mem::uninitialized).
1485core::core_arch::aarch64::sve::generatedsvundef2_s64function
  • This creates an uninitialized value, and may be unsound (like core::mem::uninitialized).
1486core::core_arch::aarch64::sve::generatedsvundef2_s8function
  • This creates an uninitialized value, and may be unsound (like core::mem::uninitialized).
1487core::core_arch::aarch64::sve::generatedsvundef2_u16function
  • This creates an uninitialized value, and may be unsound (like core::mem::uninitialized).
1488core::core_arch::aarch64::sve::generatedsvundef2_u32function
  • This creates an uninitialized value, and may be unsound (like core::mem::uninitialized).
1489core::core_arch::aarch64::sve::generatedsvundef2_u64function
  • This creates an uninitialized value, and may be unsound (like core::mem::uninitialized).
1490core::core_arch::aarch64::sve::generatedsvundef2_u8function
  • This creates an uninitialized value, and may be unsound (like core::mem::uninitialized).
1491core::core_arch::aarch64::sve::generatedsvundef3_f32function
  • This creates an uninitialized value, and may be unsound (like core::mem::uninitialized).
1492core::core_arch::aarch64::sve::generatedsvundef3_f64function
  • This creates an uninitialized value, and may be unsound (like core::mem::uninitialized).
1493core::core_arch::aarch64::sve::generatedsvundef3_s16function
  • This creates an uninitialized value, and may be unsound (like core::mem::uninitialized).
1494core::core_arch::aarch64::sve::generatedsvundef3_s32function
  • This creates an uninitialized value, and may be unsound (like core::mem::uninitialized).
1495core::core_arch::aarch64::sve::generatedsvundef3_s64function
  • This creates an uninitialized value, and may be unsound (like core::mem::uninitialized).
1496core::core_arch::aarch64::sve::generatedsvundef3_s8function
  • This creates an uninitialized value, and may be unsound (like core::mem::uninitialized).
1497core::core_arch::aarch64::sve::generatedsvundef3_u16function
  • This creates an uninitialized value, and may be unsound (like core::mem::uninitialized).
1498core::core_arch::aarch64::sve::generatedsvundef3_u32function
  • This creates an uninitialized value, and may be unsound (like core::mem::uninitialized).
1499core::core_arch::aarch64::sve::generatedsvundef3_u64function
  • This creates an uninitialized value, and may be unsound (like core::mem::uninitialized).
1500core::core_arch::aarch64::sve::generatedsvundef3_u8function
  • This creates an uninitialized value, and may be unsound (like core::mem::uninitialized).
1501core::core_arch::aarch64::sve::generatedsvundef4_f32function
  • This creates an uninitialized value, and may be unsound (like core::mem::uninitialized).
1502core::core_arch::aarch64::sve::generatedsvundef4_f64function
  • This creates an uninitialized value, and may be unsound (like core::mem::uninitialized).
1503core::core_arch::aarch64::sve::generatedsvundef4_s16function
  • This creates an uninitialized value, and may be unsound (like core::mem::uninitialized).
1504core::core_arch::aarch64::sve::generatedsvundef4_s32function
  • This creates an uninitialized value, and may be unsound (like core::mem::uninitialized).
1505core::core_arch::aarch64::sve::generatedsvundef4_s64function
  • This creates an uninitialized value, and may be unsound (like core::mem::uninitialized).
1506core::core_arch::aarch64::sve::generatedsvundef4_s8function
  • This creates an uninitialized value, and may be unsound (like core::mem::uninitialized).
1507core::core_arch::aarch64::sve::generatedsvundef4_u16function
  • This creates an uninitialized value, and may be unsound (like core::mem::uninitialized).
1508core::core_arch::aarch64::sve::generatedsvundef4_u32function
  • This creates an uninitialized value, and may be unsound (like core::mem::uninitialized).
1509core::core_arch::aarch64::sve::generatedsvundef4_u64function
  • This creates an uninitialized value, and may be unsound (like core::mem::uninitialized).
1510core::core_arch::aarch64::sve::generatedsvundef4_u8function
  • This creates an uninitialized value, and may be unsound (like core::mem::uninitialized).
1511core::core_arch::aarch64::sve::generatedsvundef_f32function
  • This creates an uninitialized value, and may be unsound (like core::mem::uninitialized).
1512core::core_arch::aarch64::sve::generatedsvundef_f64function
  • This creates an uninitialized value, and may be unsound (like core::mem::uninitialized).
1513core::core_arch::aarch64::sve::generatedsvundef_s16function
  • This creates an uninitialized value, and may be unsound (like core::mem::uninitialized).
1514core::core_arch::aarch64::sve::generatedsvundef_s32function
  • This creates an uninitialized value, and may be unsound (like core::mem::uninitialized).
1515core::core_arch::aarch64::sve::generatedsvundef_s64function
  • This creates an uninitialized value, and may be unsound (like core::mem::uninitialized).
1516core::core_arch::aarch64::sve::generatedsvundef_s8function
  • This creates an uninitialized value, and may be unsound (like core::mem::uninitialized).
1517core::core_arch::aarch64::sve::generatedsvundef_u16function
  • This creates an uninitialized value, and may be unsound (like core::mem::uninitialized).
1518core::core_arch::aarch64::sve::generatedsvundef_u32function
  • This creates an uninitialized value, and may be unsound (like core::mem::uninitialized).
1519core::core_arch::aarch64::sve::generatedsvundef_u64function
  • This creates an uninitialized value, and may be unsound (like core::mem::uninitialized).
1520core::core_arch::aarch64::sve::generatedsvundef_u8function
  • This creates an uninitialized value, and may be unsound (like core::mem::uninitialized).
1521core::core_arch::amdgpuds_bpermutefunction
1522core::core_arch::amdgpuds_permutefunction
1523core::core_arch::amdgpupermfunction
1524core::core_arch::amdgpupermlane16_swapfunction
1525core::core_arch::amdgpupermlane16_u32function
1526core::core_arch::amdgpupermlane16_varfunction
1527core::core_arch::amdgpupermlane32_swapfunction
1528core::core_arch::amdgpupermlane64_u32function
1529core::core_arch::amdgpupermlanex16_u32function
1530core::core_arch::amdgpupermlanex16_varfunction
1531core::core_arch::amdgpureadlane_u32function
1532core::core_arch::amdgpureadlane_u64function
1533core::core_arch::amdgpus_barrier_signalfunction
1534core::core_arch::amdgpus_barrier_signal_isfirstfunction
1535core::core_arch::amdgpus_barrier_waitfunction
1536core::core_arch::amdgpus_get_barrier_statefunction
1537core::core_arch::amdgpusched_barrierfunction
1538core::core_arch::amdgpusched_group_barrierfunction
1539core::core_arch::amdgpuupdate_dppfunction
1540core::core_arch::amdgpuwritelane_u32function
1541core::core_arch::amdgpuwritelane_u64function
1542core::core_arch::arm::dsp__qaddfunction
1543core::core_arch::arm::dsp__qdblfunction
1544core::core_arch::arm::dsp__qsubfunction
1545core::core_arch::arm::dsp__smlabbfunction
1546core::core_arch::arm::dsp__smlabtfunction
1547core::core_arch::arm::dsp__smlatbfunction
1548core::core_arch::arm::dsp__smlattfunction
1549core::core_arch::arm::dsp__smlawbfunction
1550core::core_arch::arm::dsp__smlawtfunction
1551core::core_arch::arm::dsp__smulbbfunction
1552core::core_arch::arm::dsp__smulbtfunction
1553core::core_arch::arm::dsp__smultbfunction
1554core::core_arch::arm::dsp__smulttfunction
1555core::core_arch::arm::dsp__smulwbfunction
1556core::core_arch::arm::dsp__smulwtfunction
1557core::core_arch::arm::sat__ssatfunction
1558core::core_arch::arm::sat__usatfunction
1559core::core_arch::arm::simd32__qadd16function
1560core::core_arch::arm::simd32__qadd8function
1561core::core_arch::arm::simd32__qasxfunction
1562core::core_arch::arm::simd32__qsaxfunction
1563core::core_arch::arm::simd32__qsub16function
1564core::core_arch::arm::simd32__qsub8function
1565core::core_arch::arm::simd32__sadd16function
1566core::core_arch::arm::simd32__sadd8function
1567core::core_arch::arm::simd32__sasxfunction
1568core::core_arch::arm::simd32__selfunction
1569core::core_arch::arm::simd32__shadd16function
1570core::core_arch::arm::simd32__shadd8function
1571core::core_arch::arm::simd32__shsub16function
1572core::core_arch::arm::simd32__shsub8function
1573core::core_arch::arm::simd32__smladfunction
1574core::core_arch::arm::simd32__smlsdfunction
1575core::core_arch::arm::simd32__smuadfunction
1576core::core_arch::arm::simd32__smuadxfunction
1577core::core_arch::arm::simd32__smusdfunction
1578core::core_arch::arm::simd32__smusdxfunction
1579core::core_arch::arm::simd32__ssub8function
1580core::core_arch::arm::simd32__usad8function
1581core::core_arch::arm::simd32__usada8function
1582core::core_arch::arm::simd32__usub8function
1583core::core_arch::arm_shared::barrier__dmbfunction
1584core::core_arch::arm_shared::barrier__dsbfunction
1585core::core_arch::arm_shared::barrier__isbfunction
1586core::core_arch::arm_shared::hints__nopfunction
1587core::core_arch::arm_shared::hints__sevfunction
1588core::core_arch::arm_shared::hints__sevlfunction
1589core::core_arch::arm_shared::hints__wfefunction
1590core::core_arch::arm_shared::hints__wfifunction
1591core::core_arch::arm_shared::hints__yieldfunction
1592core::core_arch::arm_shared::neon::generatedvext_s64function
  • Neon intrinsic unsafe
1593core::core_arch::arm_shared::neon::generatedvext_u64function
  • Neon intrinsic unsafe
1594core::core_arch::arm_shared::neon::generatedvld1_dup_f16function
  • Neon intrinsic unsafe
1595core::core_arch::arm_shared::neon::generatedvld1_dup_f32function
  • Neon intrinsic unsafe
1596core::core_arch::arm_shared::neon::generatedvld1_dup_p16function
  • Neon intrinsic unsafe
1597core::core_arch::arm_shared::neon::generatedvld1_dup_p64function
  • Neon intrinsic unsafe
1598core::core_arch::arm_shared::neon::generatedvld1_dup_p8function
  • Neon intrinsic unsafe
1599core::core_arch::arm_shared::neon::generatedvld1_dup_s16function
  • Neon intrinsic unsafe
1600core::core_arch::arm_shared::neon::generatedvld1_dup_s32function
  • Neon intrinsic unsafe
1601core::core_arch::arm_shared::neon::generatedvld1_dup_s64function
  • Neon intrinsic unsafe
1602core::core_arch::arm_shared::neon::generatedvld1_dup_s8function
  • Neon intrinsic unsafe
1603core::core_arch::arm_shared::neon::generatedvld1_dup_u16function
  • Neon intrinsic unsafe
1604core::core_arch::arm_shared::neon::generatedvld1_dup_u32function
  • Neon intrinsic unsafe
1605core::core_arch::arm_shared::neon::generatedvld1_dup_u64function
  • Neon intrinsic unsafe
1606core::core_arch::arm_shared::neon::generatedvld1_dup_u8function
  • Neon intrinsic unsafe
1607core::core_arch::arm_shared::neon::generatedvld1_f16_x2function
  • Neon intrinsic unsafe
1608core::core_arch::arm_shared::neon::generatedvld1_f16_x3function
  • Neon intrinsic unsafe
1609core::core_arch::arm_shared::neon::generatedvld1_f16_x4function
  • Neon intrinsic unsafe
1610core::core_arch::arm_shared::neon::generatedvld1_f32_x2function
  • Neon intrinsic unsafe
1611core::core_arch::arm_shared::neon::generatedvld1_f32_x3function
  • Neon intrinsic unsafe
1612core::core_arch::arm_shared::neon::generatedvld1_f32_x4function
  • Neon intrinsic unsafe
1613core::core_arch::arm_shared::neon::generatedvld1_lane_f16function
  • Neon intrinsic unsafe
1614core::core_arch::arm_shared::neon::generatedvld1_lane_f32function
  • Neon intrinsic unsafe
1615core::core_arch::arm_shared::neon::generatedvld1_lane_p16function
  • Neon intrinsic unsafe
1616core::core_arch::arm_shared::neon::generatedvld1_lane_p64function
  • Neon intrinsic unsafe
1617core::core_arch::arm_shared::neon::generatedvld1_lane_p8function
  • Neon intrinsic unsafe
1618core::core_arch::arm_shared::neon::generatedvld1_lane_s16function
  • Neon intrinsic unsafe
1619core::core_arch::arm_shared::neon::generatedvld1_lane_s32function
  • Neon intrinsic unsafe
1620core::core_arch::arm_shared::neon::generatedvld1_lane_s64function
  • Neon intrinsic unsafe
1621core::core_arch::arm_shared::neon::generatedvld1_lane_s8function
  • Neon intrinsic unsafe
1622core::core_arch::arm_shared::neon::generatedvld1_lane_u16function
  • Neon intrinsic unsafe
1623core::core_arch::arm_shared::neon::generatedvld1_lane_u32function
  • Neon intrinsic unsafe
1624core::core_arch::arm_shared::neon::generatedvld1_lane_u64function
  • Neon intrinsic unsafe
1625core::core_arch::arm_shared::neon::generatedvld1_lane_u8function
  • Neon intrinsic unsafe
1626core::core_arch::arm_shared::neon::generatedvld1_p16_x2function
  • Neon intrinsic unsafe
1627core::core_arch::arm_shared::neon::generatedvld1_p16_x3function
  • Neon intrinsic unsafe
1628core::core_arch::arm_shared::neon::generatedvld1_p16_x4function
  • Neon intrinsic unsafe
1629core::core_arch::arm_shared::neon::generatedvld1_p64_x2function
  • Neon intrinsic unsafe
1630core::core_arch::arm_shared::neon::generatedvld1_p64_x3function
  • Neon intrinsic unsafe
1631core::core_arch::arm_shared::neon::generatedvld1_p64_x4function
  • Neon intrinsic unsafe
1632core::core_arch::arm_shared::neon::generatedvld1_p8_x2function
  • Neon intrinsic unsafe
1633core::core_arch::arm_shared::neon::generatedvld1_p8_x3function
  • Neon intrinsic unsafe
1634core::core_arch::arm_shared::neon::generatedvld1_p8_x4function
  • Neon intrinsic unsafe
1635core::core_arch::arm_shared::neon::generatedvld1_s16_x2function
  • Neon intrinsic unsafe
1636core::core_arch::arm_shared::neon::generatedvld1_s16_x3function
  • Neon intrinsic unsafe
1637core::core_arch::arm_shared::neon::generatedvld1_s16_x4function
  • Neon intrinsic unsafe
1638core::core_arch::arm_shared::neon::generatedvld1_s32_x2function
  • Neon intrinsic unsafe
1639core::core_arch::arm_shared::neon::generatedvld1_s32_x3function
  • Neon intrinsic unsafe
1640core::core_arch::arm_shared::neon::generatedvld1_s32_x4function
  • Neon intrinsic unsafe
1641core::core_arch::arm_shared::neon::generatedvld1_s64_x2function
  • Neon intrinsic unsafe
1642core::core_arch::arm_shared::neon::generatedvld1_s64_x3function
  • Neon intrinsic unsafe
1643core::core_arch::arm_shared::neon::generatedvld1_s64_x4function
  • Neon intrinsic unsafe
1644core::core_arch::arm_shared::neon::generatedvld1_s8_x2function
  • Neon intrinsic unsafe
1645core::core_arch::arm_shared::neon::generatedvld1_s8_x3function
  • Neon intrinsic unsafe
1646core::core_arch::arm_shared::neon::generatedvld1_s8_x4function
  • Neon intrinsic unsafe
1647core::core_arch::arm_shared::neon::generatedvld1_u16_x2function
  • Neon intrinsic unsafe
1648core::core_arch::arm_shared::neon::generatedvld1_u16_x3function
  • Neon intrinsic unsafe
1649core::core_arch::arm_shared::neon::generatedvld1_u16_x4function
  • Neon intrinsic unsafe
1650core::core_arch::arm_shared::neon::generatedvld1_u32_x2function
  • Neon intrinsic unsafe
1651core::core_arch::arm_shared::neon::generatedvld1_u32_x3function
  • Neon intrinsic unsafe
1652core::core_arch::arm_shared::neon::generatedvld1_u32_x4function
  • Neon intrinsic unsafe
1653core::core_arch::arm_shared::neon::generatedvld1_u64_x2function
  • Neon intrinsic unsafe
1654core::core_arch::arm_shared::neon::generatedvld1_u64_x3function
  • Neon intrinsic unsafe
1655core::core_arch::arm_shared::neon::generatedvld1_u64_x4function
  • Neon intrinsic unsafe
1656core::core_arch::arm_shared::neon::generatedvld1_u8_x2function
  • Neon intrinsic unsafe
1657core::core_arch::arm_shared::neon::generatedvld1_u8_x3function
  • Neon intrinsic unsafe
1658core::core_arch::arm_shared::neon::generatedvld1_u8_x4function
  • Neon intrinsic unsafe
1659core::core_arch::arm_shared::neon::generatedvld1q_dup_f16function
  • Neon intrinsic unsafe
1660core::core_arch::arm_shared::neon::generatedvld1q_dup_f32function
  • Neon intrinsic unsafe
1661core::core_arch::arm_shared::neon::generatedvld1q_dup_p16function
  • Neon intrinsic unsafe
1662core::core_arch::arm_shared::neon::generatedvld1q_dup_p64function
  • Neon intrinsic unsafe
1663core::core_arch::arm_shared::neon::generatedvld1q_dup_p8function
  • Neon intrinsic unsafe
1664core::core_arch::arm_shared::neon::generatedvld1q_dup_s16function
  • Neon intrinsic unsafe
1665core::core_arch::arm_shared::neon::generatedvld1q_dup_s32function
  • Neon intrinsic unsafe
1666core::core_arch::arm_shared::neon::generatedvld1q_dup_s64function
  • Neon intrinsic unsafe
1667core::core_arch::arm_shared::neon::generatedvld1q_dup_s8function
  • Neon intrinsic unsafe
1668core::core_arch::arm_shared::neon::generatedvld1q_dup_u16function
  • Neon intrinsic unsafe
1669core::core_arch::arm_shared::neon::generatedvld1q_dup_u32function
  • Neon intrinsic unsafe
1670core::core_arch::arm_shared::neon::generatedvld1q_dup_u64function
  • Neon intrinsic unsafe
1671core::core_arch::arm_shared::neon::generatedvld1q_dup_u8function
  • Neon intrinsic unsafe
1672core::core_arch::arm_shared::neon::generatedvld1q_f16_x2function
  • Neon intrinsic unsafe
1673core::core_arch::arm_shared::neon::generatedvld1q_f16_x3function
  • Neon intrinsic unsafe
1674core::core_arch::arm_shared::neon::generatedvld1q_f16_x4function
  • Neon intrinsic unsafe
1675core::core_arch::arm_shared::neon::generatedvld1q_f32_x2function
  • Neon intrinsic unsafe
1676core::core_arch::arm_shared::neon::generatedvld1q_f32_x3function
  • Neon intrinsic unsafe
1677core::core_arch::arm_shared::neon::generatedvld1q_f32_x4function
  • Neon intrinsic unsafe
1678core::core_arch::arm_shared::neon::generatedvld1q_lane_f16function
  • Neon intrinsic unsafe
1679core::core_arch::arm_shared::neon::generatedvld1q_lane_f32function
  • Neon intrinsic unsafe
1680core::core_arch::arm_shared::neon::generatedvld1q_lane_p16function
  • Neon intrinsic unsafe
1681core::core_arch::arm_shared::neon::generatedvld1q_lane_p64function
  • Neon intrinsic unsafe
1682core::core_arch::arm_shared::neon::generatedvld1q_lane_p8function
  • Neon intrinsic unsafe
1683core::core_arch::arm_shared::neon::generatedvld1q_lane_s16function
  • Neon intrinsic unsafe
1684core::core_arch::arm_shared::neon::generatedvld1q_lane_s32function
  • Neon intrinsic unsafe
1685core::core_arch::arm_shared::neon::generatedvld1q_lane_s64function
  • Neon intrinsic unsafe
1686core::core_arch::arm_shared::neon::generatedvld1q_lane_s8function
  • Neon intrinsic unsafe
1687core::core_arch::arm_shared::neon::generatedvld1q_lane_u16function
  • Neon intrinsic unsafe
1688core::core_arch::arm_shared::neon::generatedvld1q_lane_u32function
  • Neon intrinsic unsafe
1689core::core_arch::arm_shared::neon::generatedvld1q_lane_u64function
  • Neon intrinsic unsafe
1690core::core_arch::arm_shared::neon::generatedvld1q_lane_u8function
  • Neon intrinsic unsafe
1691core::core_arch::arm_shared::neon::generatedvld1q_p16_x2function
  • Neon intrinsic unsafe
1692core::core_arch::arm_shared::neon::generatedvld1q_p16_x3function
  • Neon intrinsic unsafe
1693core::core_arch::arm_shared::neon::generatedvld1q_p16_x4function
  • Neon intrinsic unsafe
1694core::core_arch::arm_shared::neon::generatedvld1q_p64_x2function
  • Neon intrinsic unsafe
1695core::core_arch::arm_shared::neon::generatedvld1q_p64_x3function
  • Neon intrinsic unsafe
1696core::core_arch::arm_shared::neon::generatedvld1q_p64_x4function
  • Neon intrinsic unsafe
1697core::core_arch::arm_shared::neon::generatedvld1q_p8_x2function
  • Neon intrinsic unsafe
1698core::core_arch::arm_shared::neon::generatedvld1q_p8_x3function
  • Neon intrinsic unsafe
1699core::core_arch::arm_shared::neon::generatedvld1q_p8_x4function
  • Neon intrinsic unsafe
1700core::core_arch::arm_shared::neon::generatedvld1q_s16_x2function
  • Neon intrinsic unsafe
1701core::core_arch::arm_shared::neon::generatedvld1q_s16_x3function
  • Neon intrinsic unsafe
1702core::core_arch::arm_shared::neon::generatedvld1q_s16_x4function
  • Neon intrinsic unsafe
1703core::core_arch::arm_shared::neon::generatedvld1q_s32_x2function
  • Neon intrinsic unsafe
1704core::core_arch::arm_shared::neon::generatedvld1q_s32_x3function
  • Neon intrinsic unsafe
1705core::core_arch::arm_shared::neon::generatedvld1q_s32_x4function
  • Neon intrinsic unsafe
1706core::core_arch::arm_shared::neon::generatedvld1q_s64_x2function
  • Neon intrinsic unsafe
1707core::core_arch::arm_shared::neon::generatedvld1q_s64_x3function
  • Neon intrinsic unsafe
1708core::core_arch::arm_shared::neon::generatedvld1q_s64_x4function
  • Neon intrinsic unsafe
1709core::core_arch::arm_shared::neon::generatedvld1q_s8_x2function
  • Neon intrinsic unsafe
1710core::core_arch::arm_shared::neon::generatedvld1q_s8_x3function
  • Neon intrinsic unsafe
1711core::core_arch::arm_shared::neon::generatedvld1q_s8_x4function
  • Neon intrinsic unsafe
1712core::core_arch::arm_shared::neon::generatedvld1q_u16_x2function
  • Neon intrinsic unsafe
1713core::core_arch::arm_shared::neon::generatedvld1q_u16_x3function
  • Neon intrinsic unsafe
1714core::core_arch::arm_shared::neon::generatedvld1q_u16_x4function
  • Neon intrinsic unsafe
1715core::core_arch::arm_shared::neon::generatedvld1q_u32_x2function
  • Neon intrinsic unsafe
1716core::core_arch::arm_shared::neon::generatedvld1q_u32_x3function
  • Neon intrinsic unsafe
1717core::core_arch::arm_shared::neon::generatedvld1q_u32_x4function
  • Neon intrinsic unsafe
1718core::core_arch::arm_shared::neon::generatedvld1q_u64_x2function
  • Neon intrinsic unsafe
1719core::core_arch::arm_shared::neon::generatedvld1q_u64_x3function
  • Neon intrinsic unsafe
1720core::core_arch::arm_shared::neon::generatedvld1q_u64_x4function
  • Neon intrinsic unsafe
1721core::core_arch::arm_shared::neon::generatedvld1q_u8_x2function
  • Neon intrinsic unsafe
1722core::core_arch::arm_shared::neon::generatedvld1q_u8_x3function
  • Neon intrinsic unsafe
1723core::core_arch::arm_shared::neon::generatedvld1q_u8_x4function
  • Neon intrinsic unsafe
1724core::core_arch::arm_shared::neon::generatedvld2_dup_f16function
  • Neon intrinsic unsafe
1725core::core_arch::arm_shared::neon::generatedvld2_dup_f32function
  • Neon intrinsic unsafe
1726core::core_arch::arm_shared::neon::generatedvld2_dup_p16function
  • Neon intrinsic unsafe
1727core::core_arch::arm_shared::neon::generatedvld2_dup_p64function
  • Neon intrinsic unsafe
1728core::core_arch::arm_shared::neon::generatedvld2_dup_p8function
  • Neon intrinsic unsafe
1729core::core_arch::arm_shared::neon::generatedvld2_dup_s16function
  • Neon intrinsic unsafe
1730core::core_arch::arm_shared::neon::generatedvld2_dup_s32function
  • Neon intrinsic unsafe
1731core::core_arch::arm_shared::neon::generatedvld2_dup_s64function
  • Neon intrinsic unsafe
1732core::core_arch::arm_shared::neon::generatedvld2_dup_s8function
  • Neon intrinsic unsafe
1733core::core_arch::arm_shared::neon::generatedvld2_dup_u16function
  • Neon intrinsic unsafe
1734core::core_arch::arm_shared::neon::generatedvld2_dup_u32function
  • Neon intrinsic unsafe
1735core::core_arch::arm_shared::neon::generatedvld2_dup_u64function
  • Neon intrinsic unsafe
1736core::core_arch::arm_shared::neon::generatedvld2_dup_u8function
  • Neon intrinsic unsafe
1737core::core_arch::arm_shared::neon::generatedvld2_f16function
  • Neon intrinsic unsafe
1738core::core_arch::arm_shared::neon::generatedvld2_f32function
  • Neon intrinsic unsafe
1739core::core_arch::arm_shared::neon::generatedvld2_lane_f16function
  • Neon intrinsic unsafe
1740core::core_arch::arm_shared::neon::generatedvld2_lane_f32function
  • Neon intrinsic unsafe
1741core::core_arch::arm_shared::neon::generatedvld2_lane_p16function
  • Neon intrinsic unsafe
1742core::core_arch::arm_shared::neon::generatedvld2_lane_p8function
  • Neon intrinsic unsafe
1743core::core_arch::arm_shared::neon::generatedvld2_lane_s16function
  • Neon intrinsic unsafe
1744core::core_arch::arm_shared::neon::generatedvld2_lane_s32function
  • Neon intrinsic unsafe
1745core::core_arch::arm_shared::neon::generatedvld2_lane_s8function
  • Neon intrinsic unsafe
1746core::core_arch::arm_shared::neon::generatedvld2_lane_u16function
  • Neon intrinsic unsafe
1747core::core_arch::arm_shared::neon::generatedvld2_lane_u32function
  • Neon intrinsic unsafe
1748core::core_arch::arm_shared::neon::generatedvld2_lane_u8function
  • Neon intrinsic unsafe
1749core::core_arch::arm_shared::neon::generatedvld2_p16function
  • Neon intrinsic unsafe
1750core::core_arch::arm_shared::neon::generatedvld2_p64function
  • Neon intrinsic unsafe
1751core::core_arch::arm_shared::neon::generatedvld2_p8function
  • Neon intrinsic unsafe
1752core::core_arch::arm_shared::neon::generatedvld2_s16function
  • Neon intrinsic unsafe
1753core::core_arch::arm_shared::neon::generatedvld2_s32function
  • Neon intrinsic unsafe
1754core::core_arch::arm_shared::neon::generatedvld2_s64function
  • Neon intrinsic unsafe
1755core::core_arch::arm_shared::neon::generatedvld2_s8function
  • Neon intrinsic unsafe
1756core::core_arch::arm_shared::neon::generatedvld2_u16function
  • Neon intrinsic unsafe
1757core::core_arch::arm_shared::neon::generatedvld2_u32function
  • Neon intrinsic unsafe
1758core::core_arch::arm_shared::neon::generatedvld2_u64function
  • Neon intrinsic unsafe
1759core::core_arch::arm_shared::neon::generatedvld2_u8function
  • Neon intrinsic unsafe
1760core::core_arch::arm_shared::neon::generatedvld2q_dup_f16function
  • Neon intrinsic unsafe
1761core::core_arch::arm_shared::neon::generatedvld2q_dup_f32function
  • Neon intrinsic unsafe
1762core::core_arch::arm_shared::neon::generatedvld2q_dup_p16function
  • Neon intrinsic unsafe
1763core::core_arch::arm_shared::neon::generatedvld2q_dup_p8function
  • Neon intrinsic unsafe
1764core::core_arch::arm_shared::neon::generatedvld2q_dup_s16function
  • Neon intrinsic unsafe
1765core::core_arch::arm_shared::neon::generatedvld2q_dup_s32function
  • Neon intrinsic unsafe
1766core::core_arch::arm_shared::neon::generatedvld2q_dup_s8function
  • Neon intrinsic unsafe
1767core::core_arch::arm_shared::neon::generatedvld2q_dup_u16function
  • Neon intrinsic unsafe
1768core::core_arch::arm_shared::neon::generatedvld2q_dup_u32function
  • Neon intrinsic unsafe
1769core::core_arch::arm_shared::neon::generatedvld2q_dup_u8function
  • Neon intrinsic unsafe
1770core::core_arch::arm_shared::neon::generatedvld2q_f16function
  • Neon intrinsic unsafe
1771core::core_arch::arm_shared::neon::generatedvld2q_f32function
  • Neon intrinsic unsafe
1772core::core_arch::arm_shared::neon::generatedvld2q_lane_f16function
  • Neon intrinsic unsafe
1773core::core_arch::arm_shared::neon::generatedvld2q_lane_f32function
  • Neon intrinsic unsafe
1774core::core_arch::arm_shared::neon::generatedvld2q_lane_p16function
  • Neon intrinsic unsafe
1775core::core_arch::arm_shared::neon::generatedvld2q_lane_s16function
  • Neon intrinsic unsafe
1776core::core_arch::arm_shared::neon::generatedvld2q_lane_s32function
  • Neon intrinsic unsafe
1777core::core_arch::arm_shared::neon::generatedvld2q_lane_u16function
  • Neon intrinsic unsafe
1778core::core_arch::arm_shared::neon::generatedvld2q_lane_u32function
  • Neon intrinsic unsafe
1779core::core_arch::arm_shared::neon::generatedvld2q_p16function
  • Neon intrinsic unsafe
1780core::core_arch::arm_shared::neon::generatedvld2q_p8function
  • Neon intrinsic unsafe
1781core::core_arch::arm_shared::neon::generatedvld2q_s16function
  • Neon intrinsic unsafe
1782core::core_arch::arm_shared::neon::generatedvld2q_s32function
  • Neon intrinsic unsafe
1783core::core_arch::arm_shared::neon::generatedvld2q_s8function
  • Neon intrinsic unsafe
1784core::core_arch::arm_shared::neon::generatedvld2q_u16function
  • Neon intrinsic unsafe
1785core::core_arch::arm_shared::neon::generatedvld2q_u32function
  • Neon intrinsic unsafe
1786core::core_arch::arm_shared::neon::generatedvld2q_u8function
  • Neon intrinsic unsafe
1787core::core_arch::arm_shared::neon::generatedvld3_dup_f16function
  • Neon intrinsic unsafe
1788core::core_arch::arm_shared::neon::generatedvld3_dup_f32function
  • Neon intrinsic unsafe
1789core::core_arch::arm_shared::neon::generatedvld3_dup_p16function
  • Neon intrinsic unsafe
1790core::core_arch::arm_shared::neon::generatedvld3_dup_p64function
  • Neon intrinsic unsafe
1791core::core_arch::arm_shared::neon::generatedvld3_dup_p8function
  • Neon intrinsic unsafe
1792core::core_arch::arm_shared::neon::generatedvld3_dup_s16function
  • Neon intrinsic unsafe
1793core::core_arch::arm_shared::neon::generatedvld3_dup_s32function
  • Neon intrinsic unsafe
1794core::core_arch::arm_shared::neon::generatedvld3_dup_s64function
  • Neon intrinsic unsafe
1795core::core_arch::arm_shared::neon::generatedvld3_dup_s8function
  • Neon intrinsic unsafe
1796core::core_arch::arm_shared::neon::generatedvld3_dup_u16function
  • Neon intrinsic unsafe
1797core::core_arch::arm_shared::neon::generatedvld3_dup_u32function
  • Neon intrinsic unsafe
1798core::core_arch::arm_shared::neon::generatedvld3_dup_u64function
  • Neon intrinsic unsafe
1799core::core_arch::arm_shared::neon::generatedvld3_dup_u8function
  • Neon intrinsic unsafe
1800core::core_arch::arm_shared::neon::generatedvld3_f16function
  • Neon intrinsic unsafe
1801core::core_arch::arm_shared::neon::generatedvld3_f32function
  • Neon intrinsic unsafe
1802core::core_arch::arm_shared::neon::generatedvld3_lane_f16function
  • Neon intrinsic unsafe
1803core::core_arch::arm_shared::neon::generatedvld3_lane_f32function
  • Neon intrinsic unsafe
1804core::core_arch::arm_shared::neon::generatedvld3_lane_p16function
  • Neon intrinsic unsafe
1805core::core_arch::arm_shared::neon::generatedvld3_lane_p8function
  • Neon intrinsic unsafe
1806core::core_arch::arm_shared::neon::generatedvld3_lane_s16function
  • Neon intrinsic unsafe
1807core::core_arch::arm_shared::neon::generatedvld3_lane_s32function
  • Neon intrinsic unsafe
1808core::core_arch::arm_shared::neon::generatedvld3_lane_s8function
  • Neon intrinsic unsafe
1809core::core_arch::arm_shared::neon::generatedvld3_lane_u16function
  • Neon intrinsic unsafe
1810core::core_arch::arm_shared::neon::generatedvld3_lane_u32function
  • Neon intrinsic unsafe
1811core::core_arch::arm_shared::neon::generatedvld3_lane_u8function
  • Neon intrinsic unsafe
1812core::core_arch::arm_shared::neon::generatedvld3_p16function
  • Neon intrinsic unsafe
1813core::core_arch::arm_shared::neon::generatedvld3_p64function
  • Neon intrinsic unsafe
1814core::core_arch::arm_shared::neon::generatedvld3_p8function
  • Neon intrinsic unsafe
1815core::core_arch::arm_shared::neon::generatedvld3_s16function
  • Neon intrinsic unsafe
1816core::core_arch::arm_shared::neon::generatedvld3_s32function
  • Neon intrinsic unsafe
1817core::core_arch::arm_shared::neon::generatedvld3_s64function
  • Neon intrinsic unsafe
1818core::core_arch::arm_shared::neon::generatedvld3_s8function
  • Neon intrinsic unsafe
1819core::core_arch::arm_shared::neon::generatedvld3_u16function
  • Neon intrinsic unsafe
1820core::core_arch::arm_shared::neon::generatedvld3_u32function
  • Neon intrinsic unsafe
1821core::core_arch::arm_shared::neon::generatedvld3_u64function
  • Neon intrinsic unsafe
1822core::core_arch::arm_shared::neon::generatedvld3_u8function
  • Neon intrinsic unsafe
1823core::core_arch::arm_shared::neon::generatedvld3q_dup_f16function
  • Neon intrinsic unsafe
1824core::core_arch::arm_shared::neon::generatedvld3q_dup_f32function
  • Neon intrinsic unsafe
1825core::core_arch::arm_shared::neon::generatedvld3q_dup_p16function
  • Neon intrinsic unsafe
1826core::core_arch::arm_shared::neon::generatedvld3q_dup_p8function
  • Neon intrinsic unsafe
1827core::core_arch::arm_shared::neon::generatedvld3q_dup_s16function
  • Neon intrinsic unsafe
1828core::core_arch::arm_shared::neon::generatedvld3q_dup_s32function
  • Neon intrinsic unsafe
1829core::core_arch::arm_shared::neon::generatedvld3q_dup_s8function
  • Neon intrinsic unsafe
1830core::core_arch::arm_shared::neon::generatedvld3q_dup_u16function
  • Neon intrinsic unsafe
1831core::core_arch::arm_shared::neon::generatedvld3q_dup_u32function
  • Neon intrinsic unsafe
1832core::core_arch::arm_shared::neon::generatedvld3q_dup_u8function
  • Neon intrinsic unsafe
1833core::core_arch::arm_shared::neon::generatedvld3q_f16function
  • Neon intrinsic unsafe
1834core::core_arch::arm_shared::neon::generatedvld3q_f32function
  • Neon intrinsic unsafe
1835core::core_arch::arm_shared::neon::generatedvld3q_lane_f16function
  • Neon intrinsic unsafe
1836core::core_arch::arm_shared::neon::generatedvld3q_lane_f32function
  • Neon intrinsic unsafe
1837core::core_arch::arm_shared::neon::generatedvld3q_lane_p16function
  • Neon intrinsic unsafe
1838core::core_arch::arm_shared::neon::generatedvld3q_lane_s16function
  • Neon intrinsic unsafe
1839core::core_arch::arm_shared::neon::generatedvld3q_lane_s32function
  • Neon intrinsic unsafe
1840core::core_arch::arm_shared::neon::generatedvld3q_lane_u16function
  • Neon intrinsic unsafe
1841core::core_arch::arm_shared::neon::generatedvld3q_lane_u32function
  • Neon intrinsic unsafe
1842core::core_arch::arm_shared::neon::generatedvld3q_p16function
  • Neon intrinsic unsafe
1843core::core_arch::arm_shared::neon::generatedvld3q_p8function
  • Neon intrinsic unsafe
1844core::core_arch::arm_shared::neon::generatedvld3q_s16function
  • Neon intrinsic unsafe
1845core::core_arch::arm_shared::neon::generatedvld3q_s32function
  • Neon intrinsic unsafe
1846core::core_arch::arm_shared::neon::generatedvld3q_s8function
  • Neon intrinsic unsafe
1847core::core_arch::arm_shared::neon::generatedvld3q_u16function
  • Neon intrinsic unsafe
1848core::core_arch::arm_shared::neon::generatedvld3q_u32function
  • Neon intrinsic unsafe
1849core::core_arch::arm_shared::neon::generatedvld3q_u8function
  • Neon intrinsic unsafe
1850core::core_arch::arm_shared::neon::generatedvld4_dup_f16function
  • Neon intrinsic unsafe
1851core::core_arch::arm_shared::neon::generatedvld4_dup_f32function
  • Neon intrinsic unsafe
1852core::core_arch::arm_shared::neon::generatedvld4_dup_p16function
  • Neon intrinsic unsafe
1853core::core_arch::arm_shared::neon::generatedvld4_dup_p64function
  • Neon intrinsic unsafe
1854core::core_arch::arm_shared::neon::generatedvld4_dup_p8function
  • Neon intrinsic unsafe
1855core::core_arch::arm_shared::neon::generatedvld4_dup_s16function
  • Neon intrinsic unsafe
1856core::core_arch::arm_shared::neon::generatedvld4_dup_s32function
  • Neon intrinsic unsafe
1857core::core_arch::arm_shared::neon::generatedvld4_dup_s64function
  • Neon intrinsic unsafe
1858core::core_arch::arm_shared::neon::generatedvld4_dup_s8function
  • Neon intrinsic unsafe
1859core::core_arch::arm_shared::neon::generatedvld4_dup_u16function
  • Neon intrinsic unsafe
1860core::core_arch::arm_shared::neon::generatedvld4_dup_u32function
  • Neon intrinsic unsafe
1861core::core_arch::arm_shared::neon::generatedvld4_dup_u64function
  • Neon intrinsic unsafe
1862core::core_arch::arm_shared::neon::generatedvld4_dup_u8function
  • Neon intrinsic unsafe
1863core::core_arch::arm_shared::neon::generatedvld4_f16function
  • Neon intrinsic unsafe
1864core::core_arch::arm_shared::neon::generatedvld4_f32function
  • Neon intrinsic unsafe
1865core::core_arch::arm_shared::neon::generatedvld4_lane_f16function
  • Neon intrinsic unsafe
1866core::core_arch::arm_shared::neon::generatedvld4_lane_f32function
  • Neon intrinsic unsafe
1867core::core_arch::arm_shared::neon::generatedvld4_lane_p16function
  • Neon intrinsic unsafe
1868core::core_arch::arm_shared::neon::generatedvld4_lane_p8function
  • Neon intrinsic unsafe
1869core::core_arch::arm_shared::neon::generatedvld4_lane_s16function
  • Neon intrinsic unsafe
1870core::core_arch::arm_shared::neon::generatedvld4_lane_s32function
  • Neon intrinsic unsafe
1871core::core_arch::arm_shared::neon::generatedvld4_lane_s8function
  • Neon intrinsic unsafe
1872core::core_arch::arm_shared::neon::generatedvld4_lane_u16function
  • Neon intrinsic unsafe
1873core::core_arch::arm_shared::neon::generatedvld4_lane_u32function
  • Neon intrinsic unsafe
1874core::core_arch::arm_shared::neon::generatedvld4_lane_u8function
  • Neon intrinsic unsafe
1875core::core_arch::arm_shared::neon::generatedvld4_p16function
  • Neon intrinsic unsafe
1876core::core_arch::arm_shared::neon::generatedvld4_p64function
  • Neon intrinsic unsafe
1877core::core_arch::arm_shared::neon::generatedvld4_p8function
  • Neon intrinsic unsafe
1878core::core_arch::arm_shared::neon::generatedvld4_s16function
  • Neon intrinsic unsafe
1879core::core_arch::arm_shared::neon::generatedvld4_s32function
  • Neon intrinsic unsafe
1880core::core_arch::arm_shared::neon::generatedvld4_s64function
  • Neon intrinsic unsafe
1881core::core_arch::arm_shared::neon::generatedvld4_s8function
  • Neon intrinsic unsafe
1882core::core_arch::arm_shared::neon::generatedvld4_u16function
  • Neon intrinsic unsafe
1883core::core_arch::arm_shared::neon::generatedvld4_u32function
  • Neon intrinsic unsafe
1884core::core_arch::arm_shared::neon::generatedvld4_u64function
  • Neon intrinsic unsafe
1885core::core_arch::arm_shared::neon::generatedvld4_u8function
  • Neon intrinsic unsafe
1886core::core_arch::arm_shared::neon::generatedvld4q_dup_f16function
  • Neon intrinsic unsafe
1887core::core_arch::arm_shared::neon::generatedvld4q_dup_f32function
  • Neon intrinsic unsafe
1888core::core_arch::arm_shared::neon::generatedvld4q_dup_p16function
  • Neon intrinsic unsafe
1889core::core_arch::arm_shared::neon::generatedvld4q_dup_p8function
  • Neon intrinsic unsafe
1890core::core_arch::arm_shared::neon::generatedvld4q_dup_s16function
  • Neon intrinsic unsafe
1891core::core_arch::arm_shared::neon::generatedvld4q_dup_s32function
  • Neon intrinsic unsafe
1892core::core_arch::arm_shared::neon::generatedvld4q_dup_s8function
  • Neon intrinsic unsafe
1893core::core_arch::arm_shared::neon::generatedvld4q_dup_u16function
  • Neon intrinsic unsafe
1894core::core_arch::arm_shared::neon::generatedvld4q_dup_u32function
  • Neon intrinsic unsafe
1895core::core_arch::arm_shared::neon::generatedvld4q_dup_u8function
  • Neon intrinsic unsafe
1896core::core_arch::arm_shared::neon::generatedvld4q_f16function
  • Neon intrinsic unsafe
1897core::core_arch::arm_shared::neon::generatedvld4q_f32function
  • Neon intrinsic unsafe
1898core::core_arch::arm_shared::neon::generatedvld4q_lane_f16function
  • Neon intrinsic unsafe
1899core::core_arch::arm_shared::neon::generatedvld4q_lane_f32function
  • Neon intrinsic unsafe
1900core::core_arch::arm_shared::neon::generatedvld4q_lane_p16function
  • Neon intrinsic unsafe
1901core::core_arch::arm_shared::neon::generatedvld4q_lane_s16function
  • Neon intrinsic unsafe
1902core::core_arch::arm_shared::neon::generatedvld4q_lane_s32function
  • Neon intrinsic unsafe
1903core::core_arch::arm_shared::neon::generatedvld4q_lane_u16function
  • Neon intrinsic unsafe
1904core::core_arch::arm_shared::neon::generatedvld4q_lane_u32function
  • Neon intrinsic unsafe
1905core::core_arch::arm_shared::neon::generatedvld4q_p16function
  • Neon intrinsic unsafe
1906core::core_arch::arm_shared::neon::generatedvld4q_p8function
  • Neon intrinsic unsafe
1907core::core_arch::arm_shared::neon::generatedvld4q_s16function
  • Neon intrinsic unsafe
1908core::core_arch::arm_shared::neon::generatedvld4q_s32function
  • Neon intrinsic unsafe
1909core::core_arch::arm_shared::neon::generatedvld4q_s8function
  • Neon intrinsic unsafe
1910core::core_arch::arm_shared::neon::generatedvld4q_u16function
  • Neon intrinsic unsafe
1911core::core_arch::arm_shared::neon::generatedvld4q_u32function
  • Neon intrinsic unsafe
1912core::core_arch::arm_shared::neon::generatedvld4q_u8function
  • Neon intrinsic unsafe
1913core::core_arch::arm_shared::neon::generatedvldrq_p128function
  • Neon intrinsic unsafe
1914core::core_arch::arm_shared::neon::generatedvst1_f16_x2function
  • Neon intrinsic unsafe
1915core::core_arch::arm_shared::neon::generatedvst1_f16_x3function
  • Neon intrinsic unsafe
1916core::core_arch::arm_shared::neon::generatedvst1_f16_x4function
  • Neon intrinsic unsafe
1917core::core_arch::arm_shared::neon::generatedvst1_f32_x2function
  • Neon intrinsic unsafe
1918core::core_arch::arm_shared::neon::generatedvst1_f32_x3function
  • Neon intrinsic unsafe
1919core::core_arch::arm_shared::neon::generatedvst1_f32_x4function
  • Neon intrinsic unsafe
1920core::core_arch::arm_shared::neon::generatedvst1_lane_f16function
  • Neon intrinsic unsafe
1921core::core_arch::arm_shared::neon::generatedvst1_lane_f32function
  • Neon intrinsic unsafe
1922core::core_arch::arm_shared::neon::generatedvst1_lane_p16function
  • Neon intrinsic unsafe
1923core::core_arch::arm_shared::neon::generatedvst1_lane_p64function
  • Neon intrinsic unsafe
1924core::core_arch::arm_shared::neon::generatedvst1_lane_p8function
  • Neon intrinsic unsafe
1925core::core_arch::arm_shared::neon::generatedvst1_lane_s16function
  • Neon intrinsic unsafe
1926core::core_arch::arm_shared::neon::generatedvst1_lane_s32function
  • Neon intrinsic unsafe
1927core::core_arch::arm_shared::neon::generatedvst1_lane_s64function
  • Neon intrinsic unsafe
1928core::core_arch::arm_shared::neon::generatedvst1_lane_s8function
  • Neon intrinsic unsafe
1929core::core_arch::arm_shared::neon::generatedvst1_lane_u16function
  • Neon intrinsic unsafe
1930core::core_arch::arm_shared::neon::generatedvst1_lane_u32function
  • Neon intrinsic unsafe
1931core::core_arch::arm_shared::neon::generatedvst1_lane_u64function
  • Neon intrinsic unsafe
1932core::core_arch::arm_shared::neon::generatedvst1_lane_u8function
  • Neon intrinsic unsafe
1933core::core_arch::arm_shared::neon::generatedvst1_p16_x2function
  • Neon intrinsic unsafe
1934core::core_arch::arm_shared::neon::generatedvst1_p16_x3function
  • Neon intrinsic unsafe
1935core::core_arch::arm_shared::neon::generatedvst1_p16_x4function
  • Neon intrinsic unsafe
1936core::core_arch::arm_shared::neon::generatedvst1_p64_x2function
  • Neon intrinsic unsafe
1937core::core_arch::arm_shared::neon::generatedvst1_p64_x3function
  • Neon intrinsic unsafe
1938core::core_arch::arm_shared::neon::generatedvst1_p64_x4function
  • Neon intrinsic unsafe
1939core::core_arch::arm_shared::neon::generatedvst1_p8_x2function
  • Neon intrinsic unsafe
1940core::core_arch::arm_shared::neon::generatedvst1_p8_x3function
  • Neon intrinsic unsafe
1941core::core_arch::arm_shared::neon::generatedvst1_p8_x4function
  • Neon intrinsic unsafe
1942core::core_arch::arm_shared::neon::generatedvst1_s16_x2function
  • Neon intrinsic unsafe
1943core::core_arch::arm_shared::neon::generatedvst1_s16_x3function
  • Neon intrinsic unsafe
1944core::core_arch::arm_shared::neon::generatedvst1_s16_x4function
  • Neon intrinsic unsafe
1945core::core_arch::arm_shared::neon::generatedvst1_s32_x2function
  • Neon intrinsic unsafe
1946core::core_arch::arm_shared::neon::generatedvst1_s32_x3function
  • Neon intrinsic unsafe
1947core::core_arch::arm_shared::neon::generatedvst1_s32_x4function
  • Neon intrinsic unsafe
1948core::core_arch::arm_shared::neon::generatedvst1_s64_x2function
  • Neon intrinsic unsafe
1949core::core_arch::arm_shared::neon::generatedvst1_s64_x3function
  • Neon intrinsic unsafe
1950core::core_arch::arm_shared::neon::generatedvst1_s64_x4function
  • Neon intrinsic unsafe
1951core::core_arch::arm_shared::neon::generatedvst1_s8_x2function
  • Neon intrinsic unsafe
1952core::core_arch::arm_shared::neon::generatedvst1_s8_x3function
  • Neon intrinsic unsafe
1953core::core_arch::arm_shared::neon::generatedvst1_s8_x4function
  • Neon intrinsic unsafe
1954core::core_arch::arm_shared::neon::generatedvst1_u16_x2function
  • Neon intrinsic unsafe
1955core::core_arch::arm_shared::neon::generatedvst1_u16_x3function
  • Neon intrinsic unsafe
1956core::core_arch::arm_shared::neon::generatedvst1_u16_x4function
  • Neon intrinsic unsafe
1957core::core_arch::arm_shared::neon::generatedvst1_u32_x2function
  • Neon intrinsic unsafe
1958core::core_arch::arm_shared::neon::generatedvst1_u32_x3function
  • Neon intrinsic unsafe
1959core::core_arch::arm_shared::neon::generatedvst1_u32_x4function
  • Neon intrinsic unsafe
1960core::core_arch::arm_shared::neon::generatedvst1_u64_x2function
  • Neon intrinsic unsafe
1961core::core_arch::arm_shared::neon::generatedvst1_u64_x3function
  • Neon intrinsic unsafe
1962core::core_arch::arm_shared::neon::generatedvst1_u64_x4function
  • Neon intrinsic unsafe
1963core::core_arch::arm_shared::neon::generatedvst1_u8_x2function
  • Neon intrinsic unsafe
1964core::core_arch::arm_shared::neon::generatedvst1_u8_x3function
  • Neon intrinsic unsafe
1965core::core_arch::arm_shared::neon::generatedvst1_u8_x4function
  • Neon intrinsic unsafe
1966core::core_arch::arm_shared::neon::generatedvst1q_f16_x2function
  • Neon intrinsic unsafe
1967core::core_arch::arm_shared::neon::generatedvst1q_f16_x3function
  • Neon intrinsic unsafe
1968core::core_arch::arm_shared::neon::generatedvst1q_f16_x4function
  • Neon intrinsic unsafe
1969core::core_arch::arm_shared::neon::generatedvst1q_f32_x2function
  • Neon intrinsic unsafe
1970core::core_arch::arm_shared::neon::generatedvst1q_f32_x3function
  • Neon intrinsic unsafe
1971core::core_arch::arm_shared::neon::generatedvst1q_f32_x4function
  • Neon intrinsic unsafe
1972core::core_arch::arm_shared::neon::generatedvst1q_lane_f16function
  • Neon intrinsic unsafe
1973core::core_arch::arm_shared::neon::generatedvst1q_lane_f32function
  • Neon intrinsic unsafe
1974core::core_arch::arm_shared::neon::generatedvst1q_lane_p16function
  • Neon intrinsic unsafe
1975core::core_arch::arm_shared::neon::generatedvst1q_lane_p64function
  • Neon intrinsic unsafe
1976core::core_arch::arm_shared::neon::generatedvst1q_lane_p8function
  • Neon intrinsic unsafe
1977core::core_arch::arm_shared::neon::generatedvst1q_lane_s16function
  • Neon intrinsic unsafe
1978core::core_arch::arm_shared::neon::generatedvst1q_lane_s32function
  • Neon intrinsic unsafe
1979core::core_arch::arm_shared::neon::generatedvst1q_lane_s64function
  • Neon intrinsic unsafe
1980core::core_arch::arm_shared::neon::generatedvst1q_lane_s8function
  • Neon intrinsic unsafe
1981core::core_arch::arm_shared::neon::generatedvst1q_lane_u16function
  • Neon intrinsic unsafe
1982core::core_arch::arm_shared::neon::generatedvst1q_lane_u32function
  • Neon intrinsic unsafe
1983core::core_arch::arm_shared::neon::generatedvst1q_lane_u64function
  • Neon intrinsic unsafe
1984core::core_arch::arm_shared::neon::generatedvst1q_lane_u8function
  • Neon intrinsic unsafe
1985core::core_arch::arm_shared::neon::generatedvst1q_p16_x2function
  • Neon intrinsic unsafe
1986core::core_arch::arm_shared::neon::generatedvst1q_p16_x3function
  • Neon intrinsic unsafe
1987core::core_arch::arm_shared::neon::generatedvst1q_p16_x4function
  • Neon intrinsic unsafe
1988core::core_arch::arm_shared::neon::generatedvst1q_p64_x2function
  • Neon intrinsic unsafe
1989core::core_arch::arm_shared::neon::generatedvst1q_p64_x3function
  • Neon intrinsic unsafe
1990core::core_arch::arm_shared::neon::generatedvst1q_p64_x4function
  • Neon intrinsic unsafe
1991core::core_arch::arm_shared::neon::generatedvst1q_p8_x2function
  • Neon intrinsic unsafe
1992core::core_arch::arm_shared::neon::generatedvst1q_p8_x3function
  • Neon intrinsic unsafe
1993core::core_arch::arm_shared::neon::generatedvst1q_p8_x4function
  • Neon intrinsic unsafe
1994core::core_arch::arm_shared::neon::generatedvst1q_s16_x2function
  • Neon intrinsic unsafe
1995core::core_arch::arm_shared::neon::generatedvst1q_s16_x3function
  • Neon intrinsic unsafe
1996core::core_arch::arm_shared::neon::generatedvst1q_s16_x4function
  • Neon intrinsic unsafe
1997core::core_arch::arm_shared::neon::generatedvst1q_s32_x2function
  • Neon intrinsic unsafe
1998core::core_arch::arm_shared::neon::generatedvst1q_s32_x3function
  • Neon intrinsic unsafe
1999core::core_arch::arm_shared::neon::generatedvst1q_s32_x4function
  • Neon intrinsic unsafe
2000core::core_arch::arm_shared::neon::generatedvst1q_s64_x2function
  • Neon intrinsic unsafe
2001core::core_arch::arm_shared::neon::generatedvst1q_s64_x3function
  • Neon intrinsic unsafe
2002core::core_arch::arm_shared::neon::generatedvst1q_s64_x4function
  • Neon intrinsic unsafe
2003core::core_arch::arm_shared::neon::generatedvst1q_s8_x2function
  • Neon intrinsic unsafe
2004core::core_arch::arm_shared::neon::generatedvst1q_s8_x3function
  • Neon intrinsic unsafe
2005core::core_arch::arm_shared::neon::generatedvst1q_s8_x4function
  • Neon intrinsic unsafe
2006core::core_arch::arm_shared::neon::generatedvst1q_u16_x2function
  • Neon intrinsic unsafe
2007core::core_arch::arm_shared::neon::generatedvst1q_u16_x3function
  • Neon intrinsic unsafe
2008core::core_arch::arm_shared::neon::generatedvst1q_u16_x4function
  • Neon intrinsic unsafe
2009core::core_arch::arm_shared::neon::generatedvst1q_u32_x2function
  • Neon intrinsic unsafe
2010core::core_arch::arm_shared::neon::generatedvst1q_u32_x3function
  • Neon intrinsic unsafe
2011core::core_arch::arm_shared::neon::generatedvst1q_u32_x4function
  • Neon intrinsic unsafe
2012core::core_arch::arm_shared::neon::generatedvst1q_u64_x2function
  • Neon intrinsic unsafe
2013core::core_arch::arm_shared::neon::generatedvst1q_u64_x3function
  • Neon intrinsic unsafe
2014core::core_arch::arm_shared::neon::generatedvst1q_u64_x4function
  • Neon intrinsic unsafe
2015core::core_arch::arm_shared::neon::generatedvst1q_u8_x2function
  • Neon intrinsic unsafe
2016core::core_arch::arm_shared::neon::generatedvst1q_u8_x3function
  • Neon intrinsic unsafe
2017core::core_arch::arm_shared::neon::generatedvst1q_u8_x4function
  • Neon intrinsic unsafe
2018core::core_arch::arm_shared::neon::generatedvst2_f16function
  • Neon intrinsic unsafe
2019core::core_arch::arm_shared::neon::generatedvst2_f32function
  • Neon intrinsic unsafe
2020core::core_arch::arm_shared::neon::generatedvst2_lane_f16function
  • Neon intrinsic unsafe
2021core::core_arch::arm_shared::neon::generatedvst2_lane_f32function
  • Neon intrinsic unsafe
2022core::core_arch::arm_shared::neon::generatedvst2_lane_p16function
  • Neon intrinsic unsafe
2023core::core_arch::arm_shared::neon::generatedvst2_lane_p8function
  • Neon intrinsic unsafe
2024core::core_arch::arm_shared::neon::generatedvst2_lane_s16function
  • Neon intrinsic unsafe
2025core::core_arch::arm_shared::neon::generatedvst2_lane_s32function
  • Neon intrinsic unsafe
2026core::core_arch::arm_shared::neon::generatedvst2_lane_s8function
  • Neon intrinsic unsafe
2027core::core_arch::arm_shared::neon::generatedvst2_lane_u16function
  • Neon intrinsic unsafe
2028core::core_arch::arm_shared::neon::generatedvst2_lane_u32function
  • Neon intrinsic unsafe
2029core::core_arch::arm_shared::neon::generatedvst2_lane_u8function
  • Neon intrinsic unsafe
2030core::core_arch::arm_shared::neon::generatedvst2_p16function
  • Neon intrinsic unsafe
2031core::core_arch::arm_shared::neon::generatedvst2_p64function
  • Neon intrinsic unsafe
2032core::core_arch::arm_shared::neon::generatedvst2_p8function
  • Neon intrinsic unsafe
2033core::core_arch::arm_shared::neon::generatedvst2_s16function
  • Neon intrinsic unsafe
2034core::core_arch::arm_shared::neon::generatedvst2_s32function
  • Neon intrinsic unsafe
2035core::core_arch::arm_shared::neon::generatedvst2_s64function
  • Neon intrinsic unsafe
2036core::core_arch::arm_shared::neon::generatedvst2_s8function
  • Neon intrinsic unsafe
2037core::core_arch::arm_shared::neon::generatedvst2_u16function
  • Neon intrinsic unsafe
2038core::core_arch::arm_shared::neon::generatedvst2_u32function
  • Neon intrinsic unsafe
2039core::core_arch::arm_shared::neon::generatedvst2_u64function
  • Neon intrinsic unsafe
2040core::core_arch::arm_shared::neon::generatedvst2_u8function
  • Neon intrinsic unsafe
2041core::core_arch::arm_shared::neon::generatedvst2q_f16function
  • Neon intrinsic unsafe
2042core::core_arch::arm_shared::neon::generatedvst2q_f32function
  • Neon intrinsic unsafe
2043core::core_arch::arm_shared::neon::generatedvst2q_lane_f16function
  • Neon intrinsic unsafe
2044core::core_arch::arm_shared::neon::generatedvst2q_lane_f32function
  • Neon intrinsic unsafe
2045core::core_arch::arm_shared::neon::generatedvst2q_lane_p16function
  • Neon intrinsic unsafe
2046core::core_arch::arm_shared::neon::generatedvst2q_lane_s16function
  • Neon intrinsic unsafe
2047core::core_arch::arm_shared::neon::generatedvst2q_lane_s32function
  • Neon intrinsic unsafe
2048core::core_arch::arm_shared::neon::generatedvst2q_lane_u16function
  • Neon intrinsic unsafe
2049core::core_arch::arm_shared::neon::generatedvst2q_lane_u32function
  • Neon intrinsic unsafe
2050core::core_arch::arm_shared::neon::generatedvst2q_p16function
  • Neon intrinsic unsafe
2051core::core_arch::arm_shared::neon::generatedvst2q_p8function
  • Neon intrinsic unsafe
2052core::core_arch::arm_shared::neon::generatedvst2q_s16function
  • Neon intrinsic unsafe
2053core::core_arch::arm_shared::neon::generatedvst2q_s32function
  • Neon intrinsic unsafe
2054core::core_arch::arm_shared::neon::generatedvst2q_s8function
  • Neon intrinsic unsafe
2055core::core_arch::arm_shared::neon::generatedvst2q_u16function
  • Neon intrinsic unsafe
2056core::core_arch::arm_shared::neon::generatedvst2q_u32function
  • Neon intrinsic unsafe
2057core::core_arch::arm_shared::neon::generatedvst2q_u8function
  • Neon intrinsic unsafe
2058core::core_arch::arm_shared::neon::generatedvst3_f16function
  • Neon intrinsic unsafe
2059core::core_arch::arm_shared::neon::generatedvst3_f32function
  • Neon intrinsic unsafe
2060core::core_arch::arm_shared::neon::generatedvst3_lane_f16function
  • Neon intrinsic unsafe
2061core::core_arch::arm_shared::neon::generatedvst3_lane_f32function
  • Neon intrinsic unsafe
2062core::core_arch::arm_shared::neon::generatedvst3_lane_p16function
  • Neon intrinsic unsafe
2063core::core_arch::arm_shared::neon::generatedvst3_lane_p8function
  • Neon intrinsic unsafe
2064core::core_arch::arm_shared::neon::generatedvst3_lane_s16function
  • Neon intrinsic unsafe
2065core::core_arch::arm_shared::neon::generatedvst3_lane_s32function
  • Neon intrinsic unsafe
2066core::core_arch::arm_shared::neon::generatedvst3_lane_s8function
  • Neon intrinsic unsafe
2067core::core_arch::arm_shared::neon::generatedvst3_lane_u16function
  • Neon intrinsic unsafe
2068core::core_arch::arm_shared::neon::generatedvst3_lane_u32function
  • Neon intrinsic unsafe
2069core::core_arch::arm_shared::neon::generatedvst3_lane_u8function
  • Neon intrinsic unsafe
2070core::core_arch::arm_shared::neon::generatedvst3_p16function
  • Neon intrinsic unsafe
2071core::core_arch::arm_shared::neon::generatedvst3_p64function
  • Neon intrinsic unsafe
2072core::core_arch::arm_shared::neon::generatedvst3_p8function
  • Neon intrinsic unsafe
2073core::core_arch::arm_shared::neon::generatedvst3_s16function
  • Neon intrinsic unsafe
2074core::core_arch::arm_shared::neon::generatedvst3_s32function
  • Neon intrinsic unsafe
2075core::core_arch::arm_shared::neon::generatedvst3_s64function
  • Neon intrinsic unsafe
2076core::core_arch::arm_shared::neon::generatedvst3_s8function
  • Neon intrinsic unsafe
2077core::core_arch::arm_shared::neon::generatedvst3_u16function
  • Neon intrinsic unsafe
2078core::core_arch::arm_shared::neon::generatedvst3_u32function
  • Neon intrinsic unsafe
2079core::core_arch::arm_shared::neon::generatedvst3_u64function
  • Neon intrinsic unsafe
2080core::core_arch::arm_shared::neon::generatedvst3_u8function
  • Neon intrinsic unsafe
2081core::core_arch::arm_shared::neon::generatedvst3q_f16function
  • Neon intrinsic unsafe
2082core::core_arch::arm_shared::neon::generatedvst3q_f32function
  • Neon intrinsic unsafe
2083core::core_arch::arm_shared::neon::generatedvst3q_lane_f16function
  • Neon intrinsic unsafe
2084core::core_arch::arm_shared::neon::generatedvst3q_lane_f32function
  • Neon intrinsic unsafe
2085core::core_arch::arm_shared::neon::generatedvst3q_lane_p16function
  • Neon intrinsic unsafe
2086core::core_arch::arm_shared::neon::generatedvst3q_lane_s16function
  • Neon intrinsic unsafe
2087core::core_arch::arm_shared::neon::generatedvst3q_lane_s32function
  • Neon intrinsic unsafe
2088core::core_arch::arm_shared::neon::generatedvst3q_lane_u16function
  • Neon intrinsic unsafe
2089core::core_arch::arm_shared::neon::generatedvst3q_lane_u32function
  • Neon intrinsic unsafe
2090core::core_arch::arm_shared::neon::generatedvst3q_p16function
  • Neon intrinsic unsafe
2091core::core_arch::arm_shared::neon::generatedvst3q_p8function
  • Neon intrinsic unsafe
2092core::core_arch::arm_shared::neon::generatedvst3q_s16function
  • Neon intrinsic unsafe
2093core::core_arch::arm_shared::neon::generatedvst3q_s32function
  • Neon intrinsic unsafe
2094core::core_arch::arm_shared::neon::generatedvst3q_s8function
  • Neon intrinsic unsafe
2095core::core_arch::arm_shared::neon::generatedvst3q_u16function
  • Neon intrinsic unsafe
2096core::core_arch::arm_shared::neon::generatedvst3q_u32function
  • Neon intrinsic unsafe
2097core::core_arch::arm_shared::neon::generatedvst3q_u8function
  • Neon intrinsic unsafe
2098core::core_arch::arm_shared::neon::generatedvst4_f16function
  • Neon intrinsic unsafe
2099core::core_arch::arm_shared::neon::generatedvst4_f32function
  • Neon intrinsic unsafe
2100core::core_arch::arm_shared::neon::generatedvst4_lane_f16function
  • Neon intrinsic unsafe
2101core::core_arch::arm_shared::neon::generatedvst4_lane_f32function
  • Neon intrinsic unsafe
2102core::core_arch::arm_shared::neon::generatedvst4_lane_p16function
  • Neon intrinsic unsafe
2103core::core_arch::arm_shared::neon::generatedvst4_lane_p8function
  • Neon intrinsic unsafe
2104core::core_arch::arm_shared::neon::generatedvst4_lane_s16function
  • Neon intrinsic unsafe
2105core::core_arch::arm_shared::neon::generatedvst4_lane_s32function
  • Neon intrinsic unsafe
2106core::core_arch::arm_shared::neon::generatedvst4_lane_s8function
  • Neon intrinsic unsafe
2107core::core_arch::arm_shared::neon::generatedvst4_lane_u16function
  • Neon intrinsic unsafe
2108core::core_arch::arm_shared::neon::generatedvst4_lane_u32function
  • Neon intrinsic unsafe
2109core::core_arch::arm_shared::neon::generatedvst4_lane_u8function
  • Neon intrinsic unsafe
2110core::core_arch::arm_shared::neon::generatedvst4_p16function
  • Neon intrinsic unsafe
2111core::core_arch::arm_shared::neon::generatedvst4_p64function
  • Neon intrinsic unsafe
2112core::core_arch::arm_shared::neon::generatedvst4_p8function
  • Neon intrinsic unsafe
2113core::core_arch::arm_shared::neon::generatedvst4_s16function
  • Neon intrinsic unsafe
2114core::core_arch::arm_shared::neon::generatedvst4_s32function
  • Neon intrinsic unsafe
2115core::core_arch::arm_shared::neon::generatedvst4_s64function
  • Neon intrinsic unsafe
2116core::core_arch::arm_shared::neon::generatedvst4_s8function
  • Neon intrinsic unsafe
2117core::core_arch::arm_shared::neon::generatedvst4_u16function
  • Neon intrinsic unsafe
2118core::core_arch::arm_shared::neon::generatedvst4_u32function
  • Neon intrinsic unsafe
2119core::core_arch::arm_shared::neon::generatedvst4_u64function
  • Neon intrinsic unsafe
2120core::core_arch::arm_shared::neon::generatedvst4_u8function
  • Neon intrinsic unsafe
2121core::core_arch::arm_shared::neon::generatedvst4q_f16function
  • Neon intrinsic unsafe
2122core::core_arch::arm_shared::neon::generatedvst4q_f32function
  • Neon intrinsic unsafe
2123core::core_arch::arm_shared::neon::generatedvst4q_lane_f16function
  • Neon intrinsic unsafe
2124core::core_arch::arm_shared::neon::generatedvst4q_lane_f32function
  • Neon intrinsic unsafe
2125core::core_arch::arm_shared::neon::generatedvst4q_lane_p16function
  • Neon intrinsic unsafe
2126core::core_arch::arm_shared::neon::generatedvst4q_lane_s16function
  • Neon intrinsic unsafe
2127core::core_arch::arm_shared::neon::generatedvst4q_lane_s32function
  • Neon intrinsic unsafe
2128core::core_arch::arm_shared::neon::generatedvst4q_lane_u16function
  • Neon intrinsic unsafe
2129core::core_arch::arm_shared::neon::generatedvst4q_lane_u32function
  • Neon intrinsic unsafe
2130core::core_arch::arm_shared::neon::generatedvst4q_p16function
  • Neon intrinsic unsafe
2131core::core_arch::arm_shared::neon::generatedvst4q_p8function
  • Neon intrinsic unsafe
2132core::core_arch::arm_shared::neon::generatedvst4q_s16function
  • Neon intrinsic unsafe
2133core::core_arch::arm_shared::neon::generatedvst4q_s32function
  • Neon intrinsic unsafe
2134core::core_arch::arm_shared::neon::generatedvst4q_s8function
  • Neon intrinsic unsafe
2135core::core_arch::arm_shared::neon::generatedvst4q_u16function
  • Neon intrinsic unsafe
2136core::core_arch::arm_shared::neon::generatedvst4q_u32function
  • Neon intrinsic unsafe
2137core::core_arch::arm_shared::neon::generatedvst4q_u8function
  • Neon intrinsic unsafe
2138core::core_arch::arm_shared::neon::generatedvstrq_p128function
  • Neon intrinsic unsafe
2139core::core_arch::arm_shared::sealed::Dmb__dmbtrait_method
2140core::core_arch::arm_shared::sealed::Dsb__dsbtrait_method
2141core::core_arch::arm_shared::sealed::Isb__isbtrait_method
2142core::core_arch::hexagon::scalarQ6_P_abs_Pfunction
2143core::core_arch::hexagon::scalarQ6_P_add_PPfunction
2144core::core_arch::hexagon::scalarQ6_P_add_PP_satfunction
2145core::core_arch::hexagon::scalarQ6_P_add_RPfunction
2146core::core_arch::hexagon::scalarQ6_P_and_PPfunction
2147core::core_arch::hexagon::scalarQ6_P_and_PnPfunction
2148core::core_arch::hexagon::scalarQ6_P_asl_PIfunction
2149core::core_arch::hexagon::scalarQ6_P_asl_PRfunction
2150core::core_arch::hexagon::scalarQ6_P_aslacc_PIfunction
2151core::core_arch::hexagon::scalarQ6_P_aslacc_PRfunction
2152core::core_arch::hexagon::scalarQ6_P_asland_PIfunction
2153core::core_arch::hexagon::scalarQ6_P_asland_PRfunction
2154core::core_arch::hexagon::scalarQ6_P_aslnac_PIfunction
2155core::core_arch::hexagon::scalarQ6_P_aslnac_PRfunction
2156core::core_arch::hexagon::scalarQ6_P_aslor_PIfunction
2157core::core_arch::hexagon::scalarQ6_P_aslor_PRfunction
2158core::core_arch::hexagon::scalarQ6_P_aslxacc_PIfunction
2159core::core_arch::hexagon::scalarQ6_P_aslxacc_PRfunction
2160core::core_arch::hexagon::scalarQ6_P_asr_PIfunction
2161core::core_arch::hexagon::scalarQ6_P_asr_PI_rndfunction
2162core::core_arch::hexagon::scalarQ6_P_asr_PRfunction
2163core::core_arch::hexagon::scalarQ6_P_asracc_PIfunction
2164core::core_arch::hexagon::scalarQ6_P_asracc_PRfunction
2165core::core_arch::hexagon::scalarQ6_P_asrand_PIfunction
2166core::core_arch::hexagon::scalarQ6_P_asrand_PRfunction
2167core::core_arch::hexagon::scalarQ6_P_asrnac_PIfunction
2168core::core_arch::hexagon::scalarQ6_P_asrnac_PRfunction
2169core::core_arch::hexagon::scalarQ6_P_asror_PIfunction
2170core::core_arch::hexagon::scalarQ6_P_asror_PRfunction
2171core::core_arch::hexagon::scalarQ6_P_asrrnd_PIfunction
2172core::core_arch::hexagon::scalarQ6_P_asrxacc_PRfunction
2173core::core_arch::hexagon::scalarQ6_P_bitsplit_RIfunction
2174core::core_arch::hexagon::scalarQ6_P_bitsplit_RRfunction
2175core::core_arch::hexagon::scalarQ6_P_brev_Pfunction
2176core::core_arch::hexagon::scalarQ6_P_cmpy_RR_conj_s1_satfunction
2177core::core_arch::hexagon::scalarQ6_P_cmpy_RR_conj_satfunction
2178core::core_arch::hexagon::scalarQ6_P_cmpy_RR_s1_satfunction
2179core::core_arch::hexagon::scalarQ6_P_cmpy_RR_satfunction
2180core::core_arch::hexagon::scalarQ6_P_cmpyacc_RR_conj_s1_satfunction
2181core::core_arch::hexagon::scalarQ6_P_cmpyacc_RR_conj_satfunction
2182core::core_arch::hexagon::scalarQ6_P_cmpyacc_RR_s1_satfunction
2183core::core_arch::hexagon::scalarQ6_P_cmpyacc_RR_satfunction
2184core::core_arch::hexagon::scalarQ6_P_cmpyi_RRfunction
2185core::core_arch::hexagon::scalarQ6_P_cmpyiacc_RRfunction
2186core::core_arch::hexagon::scalarQ6_P_cmpyiw_PPfunction
2187core::core_arch::hexagon::scalarQ6_P_cmpyiw_PP_conjfunction
2188core::core_arch::hexagon::scalarQ6_P_cmpyiwacc_PPfunction
2189core::core_arch::hexagon::scalarQ6_P_cmpyiwacc_PP_conjfunction
2190core::core_arch::hexagon::scalarQ6_P_cmpynac_RR_conj_s1_satfunction
2191core::core_arch::hexagon::scalarQ6_P_cmpynac_RR_conj_satfunction
2192core::core_arch::hexagon::scalarQ6_P_cmpynac_RR_s1_satfunction
2193core::core_arch::hexagon::scalarQ6_P_cmpynac_RR_satfunction
2194core::core_arch::hexagon::scalarQ6_P_cmpyr_RRfunction
2195core::core_arch::hexagon::scalarQ6_P_cmpyracc_RRfunction
2196core::core_arch::hexagon::scalarQ6_P_cmpyrw_PPfunction
2197core::core_arch::hexagon::scalarQ6_P_cmpyrw_PP_conjfunction
2198core::core_arch::hexagon::scalarQ6_P_cmpyrwacc_PPfunction
2199core::core_arch::hexagon::scalarQ6_P_cmpyrwacc_PP_conjfunction
2200core::core_arch::hexagon::scalarQ6_P_combine_IIfunction
2201core::core_arch::hexagon::scalarQ6_P_combine_IRfunction
2202core::core_arch::hexagon::scalarQ6_P_combine_RIfunction
2203core::core_arch::hexagon::scalarQ6_P_combine_RRfunction
2204core::core_arch::hexagon::scalarQ6_P_convert_d2df_Pfunction
2205core::core_arch::hexagon::scalarQ6_P_convert_df2d_Pfunction
2206core::core_arch::hexagon::scalarQ6_P_convert_df2d_P_chopfunction
2207core::core_arch::hexagon::scalarQ6_P_convert_df2ud_Pfunction
2208core::core_arch::hexagon::scalarQ6_P_convert_df2ud_P_chopfunction
2209core::core_arch::hexagon::scalarQ6_P_convert_sf2d_Rfunction
2210core::core_arch::hexagon::scalarQ6_P_convert_sf2d_R_chopfunction
2211core::core_arch::hexagon::scalarQ6_P_convert_sf2df_Rfunction
2212core::core_arch::hexagon::scalarQ6_P_convert_sf2ud_Rfunction
2213core::core_arch::hexagon::scalarQ6_P_convert_sf2ud_R_chopfunction
2214core::core_arch::hexagon::scalarQ6_P_convert_ud2df_Pfunction
2215core::core_arch::hexagon::scalarQ6_P_convert_uw2df_Rfunction
2216core::core_arch::hexagon::scalarQ6_P_convert_w2df_Rfunction
2217core::core_arch::hexagon::scalarQ6_P_cround_PIfunction
2218core::core_arch::hexagon::scalarQ6_P_cround_PRfunction
2219core::core_arch::hexagon::scalarQ6_P_deinterleave_Pfunction
2220core::core_arch::hexagon::scalarQ6_P_dfadd_PPfunction
2221core::core_arch::hexagon::scalarQ6_P_dfmake_I_negfunction
2222core::core_arch::hexagon::scalarQ6_P_dfmake_I_posfunction
2223core::core_arch::hexagon::scalarQ6_P_dfmax_PPfunction
2224core::core_arch::hexagon::scalarQ6_P_dfmin_PPfunction
2225core::core_arch::hexagon::scalarQ6_P_dfmpyfix_PPfunction
2226core::core_arch::hexagon::scalarQ6_P_dfmpyhhacc_PPfunction
2227core::core_arch::hexagon::scalarQ6_P_dfmpylhacc_PPfunction
2228core::core_arch::hexagon::scalarQ6_P_dfmpyll_PPfunction
2229core::core_arch::hexagon::scalarQ6_P_dfsub_PPfunction
2230core::core_arch::hexagon::scalarQ6_P_equals_Ifunction
2231core::core_arch::hexagon::scalarQ6_P_equals_Pfunction
2232core::core_arch::hexagon::scalarQ6_P_extract_PIIfunction
2233core::core_arch::hexagon::scalarQ6_P_extract_PPfunction
2234core::core_arch::hexagon::scalarQ6_P_extractu_PIIfunction
2235core::core_arch::hexagon::scalarQ6_P_extractu_PPfunction
2236core::core_arch::hexagon::scalarQ6_P_insert_PIIfunction
2237core::core_arch::hexagon::scalarQ6_P_insert_PPfunction
2238core::core_arch::hexagon::scalarQ6_P_interleave_Pfunction
2239core::core_arch::hexagon::scalarQ6_P_lfs_PPfunction
2240core::core_arch::hexagon::scalarQ6_P_lsl_PRfunction
2241core::core_arch::hexagon::scalarQ6_P_lslacc_PRfunction
2242core::core_arch::hexagon::scalarQ6_P_lsland_PRfunction
2243core::core_arch::hexagon::scalarQ6_P_lslnac_PRfunction
2244core::core_arch::hexagon::scalarQ6_P_lslor_PRfunction
2245core::core_arch::hexagon::scalarQ6_P_lslxacc_PRfunction
2246core::core_arch::hexagon::scalarQ6_P_lsr_PIfunction
2247core::core_arch::hexagon::scalarQ6_P_lsr_PRfunction
2248core::core_arch::hexagon::scalarQ6_P_lsracc_PIfunction
2249core::core_arch::hexagon::scalarQ6_P_lsracc_PRfunction
2250core::core_arch::hexagon::scalarQ6_P_lsrand_PIfunction
2251core::core_arch::hexagon::scalarQ6_P_lsrand_PRfunction
2252core::core_arch::hexagon::scalarQ6_P_lsrnac_PIfunction
2253core::core_arch::hexagon::scalarQ6_P_lsrnac_PRfunction
2254core::core_arch::hexagon::scalarQ6_P_lsror_PIfunction
2255core::core_arch::hexagon::scalarQ6_P_lsror_PRfunction
2256core::core_arch::hexagon::scalarQ6_P_lsrxacc_PIfunction
2257core::core_arch::hexagon::scalarQ6_P_lsrxacc_PRfunction
2258core::core_arch::hexagon::scalarQ6_P_mask_pfunction
2259core::core_arch::hexagon::scalarQ6_P_max_PPfunction
2260core::core_arch::hexagon::scalarQ6_P_maxu_PPfunction
2261core::core_arch::hexagon::scalarQ6_P_min_PPfunction
2262core::core_arch::hexagon::scalarQ6_P_minu_PPfunction
2263core::core_arch::hexagon::scalarQ6_P_mpy_RRfunction
2264core::core_arch::hexagon::scalarQ6_P_mpy_RhRhfunction
2265core::core_arch::hexagon::scalarQ6_P_mpy_RhRh_rndfunction
2266core::core_arch::hexagon::scalarQ6_P_mpy_RhRh_s1function
2267core::core_arch::hexagon::scalarQ6_P_mpy_RhRh_s1_rndfunction
2268core::core_arch::hexagon::scalarQ6_P_mpy_RhRlfunction
2269core::core_arch::hexagon::scalarQ6_P_mpy_RhRl_rndfunction
2270core::core_arch::hexagon::scalarQ6_P_mpy_RhRl_s1function
2271core::core_arch::hexagon::scalarQ6_P_mpy_RhRl_s1_rndfunction
2272core::core_arch::hexagon::scalarQ6_P_mpy_RlRhfunction
2273core::core_arch::hexagon::scalarQ6_P_mpy_RlRh_rndfunction
2274core::core_arch::hexagon::scalarQ6_P_mpy_RlRh_s1function
2275core::core_arch::hexagon::scalarQ6_P_mpy_RlRh_s1_rndfunction
2276core::core_arch::hexagon::scalarQ6_P_mpy_RlRlfunction
2277core::core_arch::hexagon::scalarQ6_P_mpy_RlRl_rndfunction
2278core::core_arch::hexagon::scalarQ6_P_mpy_RlRl_s1function
2279core::core_arch::hexagon::scalarQ6_P_mpy_RlRl_s1_rndfunction
2280core::core_arch::hexagon::scalarQ6_P_mpyacc_RRfunction
2281core::core_arch::hexagon::scalarQ6_P_mpyacc_RhRhfunction
2282core::core_arch::hexagon::scalarQ6_P_mpyacc_RhRh_s1function
2283core::core_arch::hexagon::scalarQ6_P_mpyacc_RhRlfunction
2284core::core_arch::hexagon::scalarQ6_P_mpyacc_RhRl_s1function
2285core::core_arch::hexagon::scalarQ6_P_mpyacc_RlRhfunction
2286core::core_arch::hexagon::scalarQ6_P_mpyacc_RlRh_s1function
2287core::core_arch::hexagon::scalarQ6_P_mpyacc_RlRlfunction
2288core::core_arch::hexagon::scalarQ6_P_mpyacc_RlRl_s1function
2289core::core_arch::hexagon::scalarQ6_P_mpynac_RRfunction
2290core::core_arch::hexagon::scalarQ6_P_mpynac_RhRhfunction
2291core::core_arch::hexagon::scalarQ6_P_mpynac_RhRh_s1function
2292core::core_arch::hexagon::scalarQ6_P_mpynac_RhRlfunction
2293core::core_arch::hexagon::scalarQ6_P_mpynac_RhRl_s1function
2294core::core_arch::hexagon::scalarQ6_P_mpynac_RlRhfunction
2295core::core_arch::hexagon::scalarQ6_P_mpynac_RlRh_s1function
2296core::core_arch::hexagon::scalarQ6_P_mpynac_RlRlfunction
2297core::core_arch::hexagon::scalarQ6_P_mpynac_RlRl_s1function
2298core::core_arch::hexagon::scalarQ6_P_mpyu_RRfunction
2299core::core_arch::hexagon::scalarQ6_P_mpyu_RhRhfunction
2300core::core_arch::hexagon::scalarQ6_P_mpyu_RhRh_s1function
2301core::core_arch::hexagon::scalarQ6_P_mpyu_RhRlfunction
2302core::core_arch::hexagon::scalarQ6_P_mpyu_RhRl_s1function
2303core::core_arch::hexagon::scalarQ6_P_mpyu_RlRhfunction
2304core::core_arch::hexagon::scalarQ6_P_mpyu_RlRh_s1function
2305core::core_arch::hexagon::scalarQ6_P_mpyu_RlRlfunction
2306core::core_arch::hexagon::scalarQ6_P_mpyu_RlRl_s1function
2307core::core_arch::hexagon::scalarQ6_P_mpyuacc_RRfunction
2308core::core_arch::hexagon::scalarQ6_P_mpyuacc_RhRhfunction
2309core::core_arch::hexagon::scalarQ6_P_mpyuacc_RhRh_s1function
2310core::core_arch::hexagon::scalarQ6_P_mpyuacc_RhRlfunction
2311core::core_arch::hexagon::scalarQ6_P_mpyuacc_RhRl_s1function
2312core::core_arch::hexagon::scalarQ6_P_mpyuacc_RlRhfunction
2313core::core_arch::hexagon::scalarQ6_P_mpyuacc_RlRh_s1function
2314core::core_arch::hexagon::scalarQ6_P_mpyuacc_RlRlfunction
2315core::core_arch::hexagon::scalarQ6_P_mpyuacc_RlRl_s1function
2316core::core_arch::hexagon::scalarQ6_P_mpyunac_RRfunction
2317core::core_arch::hexagon::scalarQ6_P_mpyunac_RhRhfunction
2318core::core_arch::hexagon::scalarQ6_P_mpyunac_RhRh_s1function
2319core::core_arch::hexagon::scalarQ6_P_mpyunac_RhRlfunction
2320core::core_arch::hexagon::scalarQ6_P_mpyunac_RhRl_s1function
2321core::core_arch::hexagon::scalarQ6_P_mpyunac_RlRhfunction
2322core::core_arch::hexagon::scalarQ6_P_mpyunac_RlRh_s1function
2323core::core_arch::hexagon::scalarQ6_P_mpyunac_RlRlfunction
2324core::core_arch::hexagon::scalarQ6_P_mpyunac_RlRl_s1function
2325core::core_arch::hexagon::scalarQ6_P_neg_Pfunction
2326core::core_arch::hexagon::scalarQ6_P_not_Pfunction
2327core::core_arch::hexagon::scalarQ6_P_or_PPfunction
2328core::core_arch::hexagon::scalarQ6_P_or_PnPfunction
2329core::core_arch::hexagon::scalarQ6_P_packhl_RRfunction
2330core::core_arch::hexagon::scalarQ6_P_pmpyw_RRfunction
2331core::core_arch::hexagon::scalarQ6_P_pmpywxacc_RRfunction
2332core::core_arch::hexagon::scalarQ6_P_rol_PIfunction
2333core::core_arch::hexagon::scalarQ6_P_rolacc_PIfunction
2334core::core_arch::hexagon::scalarQ6_P_roland_PIfunction
2335core::core_arch::hexagon::scalarQ6_P_rolnac_PIfunction
2336core::core_arch::hexagon::scalarQ6_P_rolor_PIfunction
2337core::core_arch::hexagon::scalarQ6_P_rolxacc_PIfunction
2338core::core_arch::hexagon::scalarQ6_P_shuffeb_PPfunction
2339core::core_arch::hexagon::scalarQ6_P_shuffeh_PPfunction
2340core::core_arch::hexagon::scalarQ6_P_shuffob_PPfunction
2341core::core_arch::hexagon::scalarQ6_P_shuffoh_PPfunction
2342core::core_arch::hexagon::scalarQ6_P_sub_PPfunction
2343core::core_arch::hexagon::scalarQ6_P_sxtw_Rfunction
2344core::core_arch::hexagon::scalarQ6_P_vabsdiffb_PPfunction
2345core::core_arch::hexagon::scalarQ6_P_vabsdiffh_PPfunction
2346core::core_arch::hexagon::scalarQ6_P_vabsdiffub_PPfunction
2347core::core_arch::hexagon::scalarQ6_P_vabsdiffw_PPfunction
2348core::core_arch::hexagon::scalarQ6_P_vabsh_Pfunction
2349core::core_arch::hexagon::scalarQ6_P_vabsh_P_satfunction
2350core::core_arch::hexagon::scalarQ6_P_vabsw_Pfunction
2351core::core_arch::hexagon::scalarQ6_P_vabsw_P_satfunction
2352core::core_arch::hexagon::scalarQ6_P_vaddb_PPfunction
2353core::core_arch::hexagon::scalarQ6_P_vaddh_PPfunction
2354core::core_arch::hexagon::scalarQ6_P_vaddh_PP_satfunction
2355core::core_arch::hexagon::scalarQ6_P_vaddub_PPfunction
2356core::core_arch::hexagon::scalarQ6_P_vaddub_PP_satfunction
2357core::core_arch::hexagon::scalarQ6_P_vadduh_PP_satfunction
2358core::core_arch::hexagon::scalarQ6_P_vaddw_PPfunction
2359core::core_arch::hexagon::scalarQ6_P_vaddw_PP_satfunction
2360core::core_arch::hexagon::scalarQ6_P_valignb_PPIfunction
2361core::core_arch::hexagon::scalarQ6_P_valignb_PPpfunction
2362core::core_arch::hexagon::scalarQ6_P_vaslh_PIfunction
2363core::core_arch::hexagon::scalarQ6_P_vaslh_PRfunction
2364core::core_arch::hexagon::scalarQ6_P_vaslw_PIfunction
2365core::core_arch::hexagon::scalarQ6_P_vaslw_PRfunction
2366core::core_arch::hexagon::scalarQ6_P_vasrh_PIfunction
2367core::core_arch::hexagon::scalarQ6_P_vasrh_PI_rndfunction
2368core::core_arch::hexagon::scalarQ6_P_vasrh_PRfunction
2369core::core_arch::hexagon::scalarQ6_P_vasrw_PIfunction
2370core::core_arch::hexagon::scalarQ6_P_vasrw_PRfunction
2371core::core_arch::hexagon::scalarQ6_P_vavgh_PPfunction
2372core::core_arch::hexagon::scalarQ6_P_vavgh_PP_crndfunction
2373core::core_arch::hexagon::scalarQ6_P_vavgh_PP_rndfunction
2374core::core_arch::hexagon::scalarQ6_P_vavgub_PPfunction
2375core::core_arch::hexagon::scalarQ6_P_vavgub_PP_rndfunction
2376core::core_arch::hexagon::scalarQ6_P_vavguh_PPfunction
2377core::core_arch::hexagon::scalarQ6_P_vavguh_PP_rndfunction
2378core::core_arch::hexagon::scalarQ6_P_vavguw_PPfunction
2379core::core_arch::hexagon::scalarQ6_P_vavguw_PP_rndfunction
2380core::core_arch::hexagon::scalarQ6_P_vavgw_PPfunction
2381core::core_arch::hexagon::scalarQ6_P_vavgw_PP_crndfunction
2382core::core_arch::hexagon::scalarQ6_P_vavgw_PP_rndfunction
2383core::core_arch::hexagon::scalarQ6_P_vclip_PIfunction
2384core::core_arch::hexagon::scalarQ6_P_vcmpyi_PP_s1_satfunction
2385core::core_arch::hexagon::scalarQ6_P_vcmpyi_PP_satfunction
2386core::core_arch::hexagon::scalarQ6_P_vcmpyiacc_PP_satfunction
2387core::core_arch::hexagon::scalarQ6_P_vcmpyr_PP_s1_satfunction
2388core::core_arch::hexagon::scalarQ6_P_vcmpyr_PP_satfunction
2389core::core_arch::hexagon::scalarQ6_P_vcmpyracc_PP_satfunction
2390core::core_arch::hexagon::scalarQ6_P_vcnegh_PRfunction
2391core::core_arch::hexagon::scalarQ6_P_vconj_P_satfunction
2392core::core_arch::hexagon::scalarQ6_P_vcrotate_PRfunction
2393core::core_arch::hexagon::scalarQ6_P_vdmpy_PP_s1_satfunction
2394core::core_arch::hexagon::scalarQ6_P_vdmpy_PP_satfunction
2395core::core_arch::hexagon::scalarQ6_P_vdmpyacc_PP_s1_satfunction
2396core::core_arch::hexagon::scalarQ6_P_vdmpyacc_PP_satfunction
2397core::core_arch::hexagon::scalarQ6_P_vdmpybsu_PP_satfunction
2398core::core_arch::hexagon::scalarQ6_P_vdmpybsuacc_PP_satfunction
2399core::core_arch::hexagon::scalarQ6_P_vdmpyw_PPfunction
2400core::core_arch::hexagon::scalarQ6_P_vdmpywacc_PPfunction
2401core::core_arch::hexagon::scalarQ6_P_vlslh_PRfunction
2402core::core_arch::hexagon::scalarQ6_P_vlslw_PRfunction
2403core::core_arch::hexagon::scalarQ6_P_vlsrh_PIfunction
2404core::core_arch::hexagon::scalarQ6_P_vlsrh_PRfunction
2405core::core_arch::hexagon::scalarQ6_P_vlsrw_PIfunction
2406core::core_arch::hexagon::scalarQ6_P_vlsrw_PRfunction
2407core::core_arch::hexagon::scalarQ6_P_vmaxb_PPfunction
2408core::core_arch::hexagon::scalarQ6_P_vmaxh_PPfunction
2409core::core_arch::hexagon::scalarQ6_P_vmaxub_PPfunction
2410core::core_arch::hexagon::scalarQ6_P_vmaxuh_PPfunction
2411core::core_arch::hexagon::scalarQ6_P_vmaxuw_PPfunction
2412core::core_arch::hexagon::scalarQ6_P_vmaxw_PPfunction
2413core::core_arch::hexagon::scalarQ6_P_vminb_PPfunction
2414core::core_arch::hexagon::scalarQ6_P_vminh_PPfunction
2415core::core_arch::hexagon::scalarQ6_P_vminub_PPfunction
2416core::core_arch::hexagon::scalarQ6_P_vminuh_PPfunction
2417core::core_arch::hexagon::scalarQ6_P_vminuw_PPfunction
2418core::core_arch::hexagon::scalarQ6_P_vminw_PPfunction
2419core::core_arch::hexagon::scalarQ6_P_vmpybsu_RRfunction
2420core::core_arch::hexagon::scalarQ6_P_vmpybsuacc_RRfunction
2421core::core_arch::hexagon::scalarQ6_P_vmpybu_RRfunction
2422core::core_arch::hexagon::scalarQ6_P_vmpybuacc_RRfunction
2423core::core_arch::hexagon::scalarQ6_P_vmpyeh_PP_s1_satfunction
2424core::core_arch::hexagon::scalarQ6_P_vmpyeh_PP_satfunction
2425core::core_arch::hexagon::scalarQ6_P_vmpyehacc_PPfunction
2426core::core_arch::hexagon::scalarQ6_P_vmpyehacc_PP_s1_satfunction
2427core::core_arch::hexagon::scalarQ6_P_vmpyehacc_PP_satfunction
2428core::core_arch::hexagon::scalarQ6_P_vmpyh_RR_s1_satfunction
2429core::core_arch::hexagon::scalarQ6_P_vmpyh_RR_satfunction
2430core::core_arch::hexagon::scalarQ6_P_vmpyhacc_RRfunction
2431core::core_arch::hexagon::scalarQ6_P_vmpyhacc_RR_s1_satfunction
2432core::core_arch::hexagon::scalarQ6_P_vmpyhacc_RR_satfunction
2433core::core_arch::hexagon::scalarQ6_P_vmpyhsu_RR_s1_satfunction
2434core::core_arch::hexagon::scalarQ6_P_vmpyhsu_RR_satfunction
2435core::core_arch::hexagon::scalarQ6_P_vmpyhsuacc_RR_s1_satfunction
2436core::core_arch::hexagon::scalarQ6_P_vmpyhsuacc_RR_satfunction
2437core::core_arch::hexagon::scalarQ6_P_vmpyweh_PP_rnd_satfunction
2438core::core_arch::hexagon::scalarQ6_P_vmpyweh_PP_s1_rnd_satfunction
2439core::core_arch::hexagon::scalarQ6_P_vmpyweh_PP_s1_satfunction
2440core::core_arch::hexagon::scalarQ6_P_vmpyweh_PP_satfunction
2441core::core_arch::hexagon::scalarQ6_P_vmpywehacc_PP_rnd_satfunction
2442core::core_arch::hexagon::scalarQ6_P_vmpywehacc_PP_s1_rnd_satfunction
2443core::core_arch::hexagon::scalarQ6_P_vmpywehacc_PP_s1_satfunction
2444core::core_arch::hexagon::scalarQ6_P_vmpywehacc_PP_satfunction
2445core::core_arch::hexagon::scalarQ6_P_vmpyweuh_PP_rnd_satfunction
2446core::core_arch::hexagon::scalarQ6_P_vmpyweuh_PP_s1_rnd_satfunction
2447core::core_arch::hexagon::scalarQ6_P_vmpyweuh_PP_s1_satfunction
2448core::core_arch::hexagon::scalarQ6_P_vmpyweuh_PP_satfunction
2449core::core_arch::hexagon::scalarQ6_P_vmpyweuhacc_PP_rnd_satfunction
2450core::core_arch::hexagon::scalarQ6_P_vmpyweuhacc_PP_s1_rnd_satfunction
2451core::core_arch::hexagon::scalarQ6_P_vmpyweuhacc_PP_s1_satfunction
2452core::core_arch::hexagon::scalarQ6_P_vmpyweuhacc_PP_satfunction
2453core::core_arch::hexagon::scalarQ6_P_vmpywoh_PP_rnd_satfunction
2454core::core_arch::hexagon::scalarQ6_P_vmpywoh_PP_s1_rnd_satfunction
2455core::core_arch::hexagon::scalarQ6_P_vmpywoh_PP_s1_satfunction
2456core::core_arch::hexagon::scalarQ6_P_vmpywoh_PP_satfunction
2457core::core_arch::hexagon::scalarQ6_P_vmpywohacc_PP_rnd_satfunction
2458core::core_arch::hexagon::scalarQ6_P_vmpywohacc_PP_s1_rnd_satfunction
2459core::core_arch::hexagon::scalarQ6_P_vmpywohacc_PP_s1_satfunction
2460core::core_arch::hexagon::scalarQ6_P_vmpywohacc_PP_satfunction
2461core::core_arch::hexagon::scalarQ6_P_vmpywouh_PP_rnd_satfunction
2462core::core_arch::hexagon::scalarQ6_P_vmpywouh_PP_s1_rnd_satfunction
2463core::core_arch::hexagon::scalarQ6_P_vmpywouh_PP_s1_satfunction
2464core::core_arch::hexagon::scalarQ6_P_vmpywouh_PP_satfunction
2465core::core_arch::hexagon::scalarQ6_P_vmpywouhacc_PP_rnd_satfunction
2466core::core_arch::hexagon::scalarQ6_P_vmpywouhacc_PP_s1_rnd_satfunction
2467core::core_arch::hexagon::scalarQ6_P_vmpywouhacc_PP_s1_satfunction
2468core::core_arch::hexagon::scalarQ6_P_vmpywouhacc_PP_satfunction
2469core::core_arch::hexagon::scalarQ6_P_vmux_pPPfunction
2470core::core_arch::hexagon::scalarQ6_P_vnavgh_PPfunction
2471core::core_arch::hexagon::scalarQ6_P_vnavgh_PP_crnd_satfunction
2472core::core_arch::hexagon::scalarQ6_P_vnavgh_PP_rnd_satfunction
2473core::core_arch::hexagon::scalarQ6_P_vnavgw_PPfunction
2474core::core_arch::hexagon::scalarQ6_P_vnavgw_PP_crnd_satfunction
2475core::core_arch::hexagon::scalarQ6_P_vnavgw_PP_rnd_satfunction
2476core::core_arch::hexagon::scalarQ6_P_vpmpyh_RRfunction
2477core::core_arch::hexagon::scalarQ6_P_vpmpyhxacc_RRfunction
2478core::core_arch::hexagon::scalarQ6_P_vraddub_PPfunction
2479core::core_arch::hexagon::scalarQ6_P_vraddubacc_PPfunction
2480core::core_arch::hexagon::scalarQ6_P_vrcmpyi_PPfunction
2481core::core_arch::hexagon::scalarQ6_P_vrcmpyi_PP_conjfunction
2482core::core_arch::hexagon::scalarQ6_P_vrcmpyiacc_PPfunction
2483core::core_arch::hexagon::scalarQ6_P_vrcmpyiacc_PP_conjfunction
2484core::core_arch::hexagon::scalarQ6_P_vrcmpyr_PPfunction
2485core::core_arch::hexagon::scalarQ6_P_vrcmpyr_PP_conjfunction
2486core::core_arch::hexagon::scalarQ6_P_vrcmpyracc_PPfunction
2487core::core_arch::hexagon::scalarQ6_P_vrcmpyracc_PP_conjfunction
2488core::core_arch::hexagon::scalarQ6_P_vrcmpys_PR_s1_satfunction
2489core::core_arch::hexagon::scalarQ6_P_vrcmpysacc_PR_s1_satfunction
2490core::core_arch::hexagon::scalarQ6_P_vrcneghacc_PRfunction
2491core::core_arch::hexagon::scalarQ6_P_vrcrotate_PRIfunction
2492core::core_arch::hexagon::scalarQ6_P_vrcrotateacc_PRIfunction
2493core::core_arch::hexagon::scalarQ6_P_vrmaxh_PRfunction
2494core::core_arch::hexagon::scalarQ6_P_vrmaxuh_PRfunction
2495core::core_arch::hexagon::scalarQ6_P_vrmaxuw_PRfunction
2496core::core_arch::hexagon::scalarQ6_P_vrmaxw_PRfunction
2497core::core_arch::hexagon::scalarQ6_P_vrminh_PRfunction
2498core::core_arch::hexagon::scalarQ6_P_vrminuh_PRfunction
2499core::core_arch::hexagon::scalarQ6_P_vrminuw_PRfunction
2500core::core_arch::hexagon::scalarQ6_P_vrminw_PRfunction
2501core::core_arch::hexagon::scalarQ6_P_vrmpybsu_PPfunction
2502core::core_arch::hexagon::scalarQ6_P_vrmpybsuacc_PPfunction
2503core::core_arch::hexagon::scalarQ6_P_vrmpybu_PPfunction
2504core::core_arch::hexagon::scalarQ6_P_vrmpybuacc_PPfunction
2505core::core_arch::hexagon::scalarQ6_P_vrmpyh_PPfunction
2506core::core_arch::hexagon::scalarQ6_P_vrmpyhacc_PPfunction
2507core::core_arch::hexagon::scalarQ6_P_vrmpyweh_PPfunction
2508core::core_arch::hexagon::scalarQ6_P_vrmpyweh_PP_s1function
2509core::core_arch::hexagon::scalarQ6_P_vrmpywehacc_PPfunction
2510core::core_arch::hexagon::scalarQ6_P_vrmpywehacc_PP_s1function
2511core::core_arch::hexagon::scalarQ6_P_vrmpywoh_PPfunction
2512core::core_arch::hexagon::scalarQ6_P_vrmpywoh_PP_s1function
2513core::core_arch::hexagon::scalarQ6_P_vrmpywohacc_PPfunction
2514core::core_arch::hexagon::scalarQ6_P_vrmpywohacc_PP_s1function
2515core::core_arch::hexagon::scalarQ6_P_vrsadub_PPfunction
2516core::core_arch::hexagon::scalarQ6_P_vrsadubacc_PPfunction
2517core::core_arch::hexagon::scalarQ6_P_vsathb_Pfunction
2518core::core_arch::hexagon::scalarQ6_P_vsathub_Pfunction
2519core::core_arch::hexagon::scalarQ6_P_vsatwh_Pfunction
2520core::core_arch::hexagon::scalarQ6_P_vsatwuh_Pfunction
2521core::core_arch::hexagon::scalarQ6_P_vsplatb_Rfunction
2522core::core_arch::hexagon::scalarQ6_P_vsplath_Rfunction
2523core::core_arch::hexagon::scalarQ6_P_vspliceb_PPIfunction
2524core::core_arch::hexagon::scalarQ6_P_vspliceb_PPpfunction
2525core::core_arch::hexagon::scalarQ6_P_vsubb_PPfunction
2526core::core_arch::hexagon::scalarQ6_P_vsubh_PPfunction
2527core::core_arch::hexagon::scalarQ6_P_vsubh_PP_satfunction
2528core::core_arch::hexagon::scalarQ6_P_vsubub_PPfunction
2529core::core_arch::hexagon::scalarQ6_P_vsubub_PP_satfunction
2530core::core_arch::hexagon::scalarQ6_P_vsubuh_PP_satfunction
2531core::core_arch::hexagon::scalarQ6_P_vsubw_PPfunction
2532core::core_arch::hexagon::scalarQ6_P_vsubw_PP_satfunction
2533core::core_arch::hexagon::scalarQ6_P_vsxtbh_Rfunction
2534core::core_arch::hexagon::scalarQ6_P_vsxthw_Rfunction
2535core::core_arch::hexagon::scalarQ6_P_vtrunehb_PPfunction
2536core::core_arch::hexagon::scalarQ6_P_vtrunewh_PPfunction
2537core::core_arch::hexagon::scalarQ6_P_vtrunohb_PPfunction
2538core::core_arch::hexagon::scalarQ6_P_vtrunowh_PPfunction
2539core::core_arch::hexagon::scalarQ6_P_vxaddsubh_PP_rnd_rs1_satfunction
2540core::core_arch::hexagon::scalarQ6_P_vxaddsubh_PP_satfunction
2541core::core_arch::hexagon::scalarQ6_P_vxaddsubw_PP_satfunction
2542core::core_arch::hexagon::scalarQ6_P_vxsubaddh_PP_rnd_rs1_satfunction
2543core::core_arch::hexagon::scalarQ6_P_vxsubaddh_PP_satfunction
2544core::core_arch::hexagon::scalarQ6_P_vxsubaddw_PP_satfunction
2545core::core_arch::hexagon::scalarQ6_P_vzxtbh_Rfunction
2546core::core_arch::hexagon::scalarQ6_P_vzxthw_Rfunction
2547core::core_arch::hexagon::scalarQ6_P_xor_PPfunction
2548core::core_arch::hexagon::scalarQ6_P_xorxacc_PPfunction
2549core::core_arch::hexagon::scalarQ6_R_abs_Rfunction
2550core::core_arch::hexagon::scalarQ6_R_abs_R_satfunction
2551core::core_arch::hexagon::scalarQ6_R_add_RIfunction
2552core::core_arch::hexagon::scalarQ6_R_add_RRfunction
2553core::core_arch::hexagon::scalarQ6_R_add_RR_satfunction
2554core::core_arch::hexagon::scalarQ6_R_add_RhRh_s16function
2555core::core_arch::hexagon::scalarQ6_R_add_RhRh_sat_s16function
2556core::core_arch::hexagon::scalarQ6_R_add_RhRl_s16function
2557core::core_arch::hexagon::scalarQ6_R_add_RhRl_sat_s16function
2558core::core_arch::hexagon::scalarQ6_R_add_RlRhfunction
2559core::core_arch::hexagon::scalarQ6_R_add_RlRh_s16function
2560core::core_arch::hexagon::scalarQ6_R_add_RlRh_satfunction
2561core::core_arch::hexagon::scalarQ6_R_add_RlRh_sat_s16function
2562core::core_arch::hexagon::scalarQ6_R_add_RlRlfunction
2563core::core_arch::hexagon::scalarQ6_R_add_RlRl_s16function
2564core::core_arch::hexagon::scalarQ6_R_add_RlRl_satfunction
2565core::core_arch::hexagon::scalarQ6_R_add_RlRl_sat_s16function
2566core::core_arch::hexagon::scalarQ6_R_add_add_RRIfunction
2567core::core_arch::hexagon::scalarQ6_R_add_asl_IRIfunction
2568core::core_arch::hexagon::scalarQ6_R_add_clb_PIfunction
2569core::core_arch::hexagon::scalarQ6_R_add_clb_RIfunction
2570core::core_arch::hexagon::scalarQ6_R_add_lsr_IRIfunction
2571core::core_arch::hexagon::scalarQ6_R_add_mpyi_IRIfunction
2572core::core_arch::hexagon::scalarQ6_R_add_mpyi_IRRfunction
2573core::core_arch::hexagon::scalarQ6_R_add_mpyi_RIRfunction
2574core::core_arch::hexagon::scalarQ6_R_add_mpyi_RRIfunction
2575core::core_arch::hexagon::scalarQ6_R_add_mpyi_RRRfunction
2576core::core_arch::hexagon::scalarQ6_R_add_sub_RIRfunction
2577core::core_arch::hexagon::scalarQ6_R_addacc_RIfunction
2578core::core_arch::hexagon::scalarQ6_R_addacc_RRfunction
2579core::core_arch::hexagon::scalarQ6_R_addasl_RRIfunction
2580core::core_arch::hexagon::scalarQ6_R_addnac_RIfunction
2581core::core_arch::hexagon::scalarQ6_R_addnac_RRfunction
2582core::core_arch::hexagon::scalarQ6_R_and_RIfunction
2583core::core_arch::hexagon::scalarQ6_R_and_RRfunction
2584core::core_arch::hexagon::scalarQ6_R_and_RnRfunction
2585core::core_arch::hexagon::scalarQ6_R_and_asl_IRIfunction
2586core::core_arch::hexagon::scalarQ6_R_and_lsr_IRIfunction
2587core::core_arch::hexagon::scalarQ6_R_andand_RRfunction
2588core::core_arch::hexagon::scalarQ6_R_andand_RnRfunction
2589core::core_arch::hexagon::scalarQ6_R_andor_RIfunction
2590core::core_arch::hexagon::scalarQ6_R_andor_RRfunction
2591core::core_arch::hexagon::scalarQ6_R_andor_RnRfunction
2592core::core_arch::hexagon::scalarQ6_R_andxacc_RRfunction
2593core::core_arch::hexagon::scalarQ6_R_andxacc_RnRfunction
2594core::core_arch::hexagon::scalarQ6_R_asl_RIfunction
2595core::core_arch::hexagon::scalarQ6_R_asl_RI_satfunction
2596core::core_arch::hexagon::scalarQ6_R_asl_RRfunction
2597core::core_arch::hexagon::scalarQ6_R_asl_RR_satfunction
2598core::core_arch::hexagon::scalarQ6_R_aslacc_RIfunction
2599core::core_arch::hexagon::scalarQ6_R_aslacc_RRfunction
2600core::core_arch::hexagon::scalarQ6_R_asland_RIfunction
2601core::core_arch::hexagon::scalarQ6_R_asland_RRfunction
2602core::core_arch::hexagon::scalarQ6_R_aslh_Rfunction
2603core::core_arch::hexagon::scalarQ6_R_aslnac_RIfunction
2604core::core_arch::hexagon::scalarQ6_R_aslnac_RRfunction
2605core::core_arch::hexagon::scalarQ6_R_aslor_RIfunction
2606core::core_arch::hexagon::scalarQ6_R_aslor_RRfunction
2607core::core_arch::hexagon::scalarQ6_R_aslxacc_RIfunction
2608core::core_arch::hexagon::scalarQ6_R_asr_RIfunction
2609core::core_arch::hexagon::scalarQ6_R_asr_RI_rndfunction
2610core::core_arch::hexagon::scalarQ6_R_asr_RRfunction
2611core::core_arch::hexagon::scalarQ6_R_asr_RR_satfunction
2612core::core_arch::hexagon::scalarQ6_R_asracc_RIfunction
2613core::core_arch::hexagon::scalarQ6_R_asracc_RRfunction
2614core::core_arch::hexagon::scalarQ6_R_asrand_RIfunction
2615core::core_arch::hexagon::scalarQ6_R_asrand_RRfunction
2616core::core_arch::hexagon::scalarQ6_R_asrh_Rfunction
2617core::core_arch::hexagon::scalarQ6_R_asrnac_RIfunction
2618core::core_arch::hexagon::scalarQ6_R_asrnac_RRfunction
2619core::core_arch::hexagon::scalarQ6_R_asror_RIfunction
2620core::core_arch::hexagon::scalarQ6_R_asror_RRfunction
2621core::core_arch::hexagon::scalarQ6_R_asrrnd_RIfunction
2622core::core_arch::hexagon::scalarQ6_R_brev_Rfunction
2623core::core_arch::hexagon::scalarQ6_R_cl0_Pfunction
2624core::core_arch::hexagon::scalarQ6_R_cl0_Rfunction
2625core::core_arch::hexagon::scalarQ6_R_cl1_Pfunction
2626core::core_arch::hexagon::scalarQ6_R_cl1_Rfunction
2627core::core_arch::hexagon::scalarQ6_R_clb_Pfunction
2628core::core_arch::hexagon::scalarQ6_R_clb_Rfunction
2629core::core_arch::hexagon::scalarQ6_R_clip_RIfunction
2630core::core_arch::hexagon::scalarQ6_R_clrbit_RIfunction
2631core::core_arch::hexagon::scalarQ6_R_clrbit_RRfunction
2632core::core_arch::hexagon::scalarQ6_R_cmp_eq_RIfunction
2633core::core_arch::hexagon::scalarQ6_R_cmp_eq_RRfunction
2634core::core_arch::hexagon::scalarQ6_R_cmpy_RR_conj_rnd_satfunction
2635core::core_arch::hexagon::scalarQ6_R_cmpy_RR_conj_s1_rnd_satfunction
2636core::core_arch::hexagon::scalarQ6_R_cmpy_RR_rnd_satfunction
2637core::core_arch::hexagon::scalarQ6_R_cmpy_RR_s1_rnd_satfunction
2638core::core_arch::hexagon::scalarQ6_R_cmpyiw_PP_conj_s1_rnd_satfunction
2639core::core_arch::hexagon::scalarQ6_R_cmpyiw_PP_conj_s1_satfunction
2640core::core_arch::hexagon::scalarQ6_R_cmpyiw_PP_s1_rnd_satfunction
2641core::core_arch::hexagon::scalarQ6_R_cmpyiw_PP_s1_satfunction
2642core::core_arch::hexagon::scalarQ6_R_cmpyiwh_PR_conj_s1_rnd_satfunction
2643core::core_arch::hexagon::scalarQ6_R_cmpyiwh_PR_s1_rnd_satfunction
2644core::core_arch::hexagon::scalarQ6_R_cmpyrw_PP_conj_s1_rnd_satfunction
2645core::core_arch::hexagon::scalarQ6_R_cmpyrw_PP_conj_s1_satfunction
2646core::core_arch::hexagon::scalarQ6_R_cmpyrw_PP_s1_rnd_satfunction
2647core::core_arch::hexagon::scalarQ6_R_cmpyrw_PP_s1_satfunction
2648core::core_arch::hexagon::scalarQ6_R_cmpyrwh_PR_conj_s1_rnd_satfunction
2649core::core_arch::hexagon::scalarQ6_R_cmpyrwh_PR_s1_rnd_satfunction
2650core::core_arch::hexagon::scalarQ6_R_combine_RhRhfunction
2651core::core_arch::hexagon::scalarQ6_R_combine_RhRlfunction
2652core::core_arch::hexagon::scalarQ6_R_combine_RlRhfunction
2653core::core_arch::hexagon::scalarQ6_R_combine_RlRlfunction
2654core::core_arch::hexagon::scalarQ6_R_convert_d2sf_Pfunction
2655core::core_arch::hexagon::scalarQ6_R_convert_df2sf_Pfunction
2656core::core_arch::hexagon::scalarQ6_R_convert_df2uw_Pfunction
2657core::core_arch::hexagon::scalarQ6_R_convert_df2uw_P_chopfunction
2658core::core_arch::hexagon::scalarQ6_R_convert_df2w_Pfunction
2659core::core_arch::hexagon::scalarQ6_R_convert_df2w_P_chopfunction
2660core::core_arch::hexagon::scalarQ6_R_convert_sf2uw_Rfunction
2661core::core_arch::hexagon::scalarQ6_R_convert_sf2uw_R_chopfunction
2662core::core_arch::hexagon::scalarQ6_R_convert_sf2w_Rfunction
2663core::core_arch::hexagon::scalarQ6_R_convert_sf2w_R_chopfunction
2664core::core_arch::hexagon::scalarQ6_R_convert_ud2sf_Pfunction
2665core::core_arch::hexagon::scalarQ6_R_convert_uw2sf_Rfunction
2666core::core_arch::hexagon::scalarQ6_R_convert_w2sf_Rfunction
2667core::core_arch::hexagon::scalarQ6_R_cround_RIfunction
2668core::core_arch::hexagon::scalarQ6_R_cround_RRfunction
2669core::core_arch::hexagon::scalarQ6_R_ct0_Pfunction
2670core::core_arch::hexagon::scalarQ6_R_ct0_Rfunction
2671core::core_arch::hexagon::scalarQ6_R_ct1_Pfunction
2672core::core_arch::hexagon::scalarQ6_R_ct1_Rfunction
2673core::core_arch::hexagon::scalarQ6_R_dmpausefunction
2674core::core_arch::hexagon::scalarQ6_R_dmpollfunction
2675core::core_arch::hexagon::scalarQ6_R_dmwaitfunction
2676core::core_arch::hexagon::scalarQ6_R_equals_Ifunction
2677core::core_arch::hexagon::scalarQ6_R_equals_Rfunction
2678core::core_arch::hexagon::scalarQ6_R_equals_pfunction
2679core::core_arch::hexagon::scalarQ6_R_extract_RIIfunction
2680core::core_arch::hexagon::scalarQ6_R_extract_RPfunction
2681core::core_arch::hexagon::scalarQ6_R_extractu_RIIfunction
2682core::core_arch::hexagon::scalarQ6_R_extractu_RPfunction
2683core::core_arch::hexagon::scalarQ6_R_insert_RIIfunction
2684core::core_arch::hexagon::scalarQ6_R_insert_RPfunction
2685core::core_arch::hexagon::scalarQ6_R_lsl_IRfunction
2686core::core_arch::hexagon::scalarQ6_R_lsl_RRfunction
2687core::core_arch::hexagon::scalarQ6_R_lslacc_RRfunction
2688core::core_arch::hexagon::scalarQ6_R_lsland_RRfunction
2689core::core_arch::hexagon::scalarQ6_R_lslnac_RRfunction
2690core::core_arch::hexagon::scalarQ6_R_lslor_RRfunction
2691core::core_arch::hexagon::scalarQ6_R_lsr_RIfunction
2692core::core_arch::hexagon::scalarQ6_R_lsr_RRfunction
2693core::core_arch::hexagon::scalarQ6_R_lsracc_RIfunction
2694core::core_arch::hexagon::scalarQ6_R_lsracc_RRfunction
2695core::core_arch::hexagon::scalarQ6_R_lsrand_RIfunction
2696core::core_arch::hexagon::scalarQ6_R_lsrand_RRfunction
2697core::core_arch::hexagon::scalarQ6_R_lsrnac_RIfunction
2698core::core_arch::hexagon::scalarQ6_R_lsrnac_RRfunction
2699core::core_arch::hexagon::scalarQ6_R_lsror_RIfunction
2700core::core_arch::hexagon::scalarQ6_R_lsror_RRfunction
2701core::core_arch::hexagon::scalarQ6_R_lsrxacc_RIfunction
2702core::core_arch::hexagon::scalarQ6_R_mask_IIfunction
2703core::core_arch::hexagon::scalarQ6_R_max_RRfunction
2704core::core_arch::hexagon::scalarQ6_R_maxu_RRfunction
2705core::core_arch::hexagon::scalarQ6_R_min_RRfunction
2706core::core_arch::hexagon::scalarQ6_R_minu_RRfunction
2707core::core_arch::hexagon::scalarQ6_R_modwrap_RRfunction
2708core::core_arch::hexagon::scalarQ6_R_mpy_RRfunction
2709core::core_arch::hexagon::scalarQ6_R_mpy_RR_rndfunction
2710core::core_arch::hexagon::scalarQ6_R_mpy_RR_s1function
2711core::core_arch::hexagon::scalarQ6_R_mpy_RR_s1_satfunction
2712core::core_arch::hexagon::scalarQ6_R_mpy_RRh_s1_rnd_satfunction
2713core::core_arch::hexagon::scalarQ6_R_mpy_RRh_s1_satfunction
2714core::core_arch::hexagon::scalarQ6_R_mpy_RRl_s1_rnd_satfunction
2715core::core_arch::hexagon::scalarQ6_R_mpy_RRl_s1_satfunction
2716core::core_arch::hexagon::scalarQ6_R_mpy_RhRhfunction
2717core::core_arch::hexagon::scalarQ6_R_mpy_RhRh_rndfunction
2718core::core_arch::hexagon::scalarQ6_R_mpy_RhRh_rnd_satfunction
2719core::core_arch::hexagon::scalarQ6_R_mpy_RhRh_s1function
2720core::core_arch::hexagon::scalarQ6_R_mpy_RhRh_s1_rndfunction
2721core::core_arch::hexagon::scalarQ6_R_mpy_RhRh_s1_rnd_satfunction
2722core::core_arch::hexagon::scalarQ6_R_mpy_RhRh_s1_satfunction
2723core::core_arch::hexagon::scalarQ6_R_mpy_RhRh_satfunction
2724core::core_arch::hexagon::scalarQ6_R_mpy_RhRlfunction
2725core::core_arch::hexagon::scalarQ6_R_mpy_RhRl_rndfunction
2726core::core_arch::hexagon::scalarQ6_R_mpy_RhRl_rnd_satfunction
2727core::core_arch::hexagon::scalarQ6_R_mpy_RhRl_s1function
2728core::core_arch::hexagon::scalarQ6_R_mpy_RhRl_s1_rndfunction
2729core::core_arch::hexagon::scalarQ6_R_mpy_RhRl_s1_rnd_satfunction
2730core::core_arch::hexagon::scalarQ6_R_mpy_RhRl_s1_satfunction
2731core::core_arch::hexagon::scalarQ6_R_mpy_RhRl_satfunction
2732core::core_arch::hexagon::scalarQ6_R_mpy_RlRhfunction
2733core::core_arch::hexagon::scalarQ6_R_mpy_RlRh_rndfunction
2734core::core_arch::hexagon::scalarQ6_R_mpy_RlRh_rnd_satfunction
2735core::core_arch::hexagon::scalarQ6_R_mpy_RlRh_s1function
2736core::core_arch::hexagon::scalarQ6_R_mpy_RlRh_s1_rndfunction
2737core::core_arch::hexagon::scalarQ6_R_mpy_RlRh_s1_rnd_satfunction
2738core::core_arch::hexagon::scalarQ6_R_mpy_RlRh_s1_satfunction
2739core::core_arch::hexagon::scalarQ6_R_mpy_RlRh_satfunction
2740core::core_arch::hexagon::scalarQ6_R_mpy_RlRlfunction
2741core::core_arch::hexagon::scalarQ6_R_mpy_RlRl_rndfunction
2742core::core_arch::hexagon::scalarQ6_R_mpy_RlRl_rnd_satfunction
2743core::core_arch::hexagon::scalarQ6_R_mpy_RlRl_s1function
2744core::core_arch::hexagon::scalarQ6_R_mpy_RlRl_s1_rndfunction
2745core::core_arch::hexagon::scalarQ6_R_mpy_RlRl_s1_rnd_satfunction
2746core::core_arch::hexagon::scalarQ6_R_mpy_RlRl_s1_satfunction
2747core::core_arch::hexagon::scalarQ6_R_mpy_RlRl_satfunction
2748core::core_arch::hexagon::scalarQ6_R_mpyacc_RR_s1_satfunction
2749core::core_arch::hexagon::scalarQ6_R_mpyacc_RhRhfunction
2750core::core_arch::hexagon::scalarQ6_R_mpyacc_RhRh_s1function
2751core::core_arch::hexagon::scalarQ6_R_mpyacc_RhRh_s1_satfunction
2752core::core_arch::hexagon::scalarQ6_R_mpyacc_RhRh_satfunction
2753core::core_arch::hexagon::scalarQ6_R_mpyacc_RhRlfunction
2754core::core_arch::hexagon::scalarQ6_R_mpyacc_RhRl_s1function
2755core::core_arch::hexagon::scalarQ6_R_mpyacc_RhRl_s1_satfunction
2756core::core_arch::hexagon::scalarQ6_R_mpyacc_RhRl_satfunction
2757core::core_arch::hexagon::scalarQ6_R_mpyacc_RlRhfunction
2758core::core_arch::hexagon::scalarQ6_R_mpyacc_RlRh_s1function
2759core::core_arch::hexagon::scalarQ6_R_mpyacc_RlRh_s1_satfunction
2760core::core_arch::hexagon::scalarQ6_R_mpyacc_RlRh_satfunction
2761core::core_arch::hexagon::scalarQ6_R_mpyacc_RlRlfunction
2762core::core_arch::hexagon::scalarQ6_R_mpyacc_RlRl_s1function
2763core::core_arch::hexagon::scalarQ6_R_mpyacc_RlRl_s1_satfunction
2764core::core_arch::hexagon::scalarQ6_R_mpyacc_RlRl_satfunction
2765core::core_arch::hexagon::scalarQ6_R_mpyi_RIfunction
2766core::core_arch::hexagon::scalarQ6_R_mpyi_RRfunction
2767core::core_arch::hexagon::scalarQ6_R_mpyiacc_RIfunction
2768core::core_arch::hexagon::scalarQ6_R_mpyiacc_RRfunction
2769core::core_arch::hexagon::scalarQ6_R_mpyinac_RIfunction
2770core::core_arch::hexagon::scalarQ6_R_mpyinac_RRfunction
2771core::core_arch::hexagon::scalarQ6_R_mpynac_RR_s1_satfunction
2772core::core_arch::hexagon::scalarQ6_R_mpynac_RhRhfunction
2773core::core_arch::hexagon::scalarQ6_R_mpynac_RhRh_s1function
2774core::core_arch::hexagon::scalarQ6_R_mpynac_RhRh_s1_satfunction
2775core::core_arch::hexagon::scalarQ6_R_mpynac_RhRh_satfunction
2776core::core_arch::hexagon::scalarQ6_R_mpynac_RhRlfunction
2777core::core_arch::hexagon::scalarQ6_R_mpynac_RhRl_s1function
2778core::core_arch::hexagon::scalarQ6_R_mpynac_RhRl_s1_satfunction
2779core::core_arch::hexagon::scalarQ6_R_mpynac_RhRl_satfunction
2780core::core_arch::hexagon::scalarQ6_R_mpynac_RlRhfunction
2781core::core_arch::hexagon::scalarQ6_R_mpynac_RlRh_s1function
2782core::core_arch::hexagon::scalarQ6_R_mpynac_RlRh_s1_satfunction
2783core::core_arch::hexagon::scalarQ6_R_mpynac_RlRh_satfunction
2784core::core_arch::hexagon::scalarQ6_R_mpynac_RlRlfunction
2785core::core_arch::hexagon::scalarQ6_R_mpynac_RlRl_s1function
2786core::core_arch::hexagon::scalarQ6_R_mpynac_RlRl_s1_satfunction
2787core::core_arch::hexagon::scalarQ6_R_mpynac_RlRl_satfunction
2788core::core_arch::hexagon::scalarQ6_R_mpysu_RRfunction
2789core::core_arch::hexagon::scalarQ6_R_mpyu_RRfunction
2790core::core_arch::hexagon::scalarQ6_R_mpyu_RhRhfunction
2791core::core_arch::hexagon::scalarQ6_R_mpyu_RhRh_s1function
2792core::core_arch::hexagon::scalarQ6_R_mpyu_RhRlfunction
2793core::core_arch::hexagon::scalarQ6_R_mpyu_RhRl_s1function
2794core::core_arch::hexagon::scalarQ6_R_mpyu_RlRhfunction
2795core::core_arch::hexagon::scalarQ6_R_mpyu_RlRh_s1function
2796core::core_arch::hexagon::scalarQ6_R_mpyu_RlRlfunction
2797core::core_arch::hexagon::scalarQ6_R_mpyu_RlRl_s1function
2798core::core_arch::hexagon::scalarQ6_R_mpyuacc_RhRhfunction
2799core::core_arch::hexagon::scalarQ6_R_mpyuacc_RhRh_s1function
2800core::core_arch::hexagon::scalarQ6_R_mpyuacc_RhRlfunction
2801core::core_arch::hexagon::scalarQ6_R_mpyuacc_RhRl_s1function
2802core::core_arch::hexagon::scalarQ6_R_mpyuacc_RlRhfunction
2803core::core_arch::hexagon::scalarQ6_R_mpyuacc_RlRh_s1function
2804core::core_arch::hexagon::scalarQ6_R_mpyuacc_RlRlfunction
2805core::core_arch::hexagon::scalarQ6_R_mpyuacc_RlRl_s1function
2806core::core_arch::hexagon::scalarQ6_R_mpyui_RRfunction
2807core::core_arch::hexagon::scalarQ6_R_mpyunac_RhRhfunction
2808core::core_arch::hexagon::scalarQ6_R_mpyunac_RhRh_s1function
2809core::core_arch::hexagon::scalarQ6_R_mpyunac_RhRlfunction
2810core::core_arch::hexagon::scalarQ6_R_mpyunac_RhRl_s1function
2811core::core_arch::hexagon::scalarQ6_R_mpyunac_RlRhfunction
2812core::core_arch::hexagon::scalarQ6_R_mpyunac_RlRh_s1function
2813core::core_arch::hexagon::scalarQ6_R_mpyunac_RlRlfunction
2814core::core_arch::hexagon::scalarQ6_R_mpyunac_RlRl_s1function
2815core::core_arch::hexagon::scalarQ6_R_mux_pIIfunction
2816core::core_arch::hexagon::scalarQ6_R_mux_pIRfunction
2817core::core_arch::hexagon::scalarQ6_R_mux_pRIfunction
2818core::core_arch::hexagon::scalarQ6_R_mux_pRRfunction
2819core::core_arch::hexagon::scalarQ6_R_neg_Rfunction
2820core::core_arch::hexagon::scalarQ6_R_neg_R_satfunction
2821core::core_arch::hexagon::scalarQ6_R_normamt_Pfunction
2822core::core_arch::hexagon::scalarQ6_R_normamt_Rfunction
2823core::core_arch::hexagon::scalarQ6_R_not_Rfunction
2824core::core_arch::hexagon::scalarQ6_R_not_cmp_eq_RIfunction
2825core::core_arch::hexagon::scalarQ6_R_not_cmp_eq_RRfunction
2826core::core_arch::hexagon::scalarQ6_R_or_RIfunction
2827core::core_arch::hexagon::scalarQ6_R_or_RRfunction
2828core::core_arch::hexagon::scalarQ6_R_or_RnRfunction
2829core::core_arch::hexagon::scalarQ6_R_or_and_RRIfunction
2830core::core_arch::hexagon::scalarQ6_R_or_asl_IRIfunction
2831core::core_arch::hexagon::scalarQ6_R_or_lsr_IRIfunction
2832core::core_arch::hexagon::scalarQ6_R_orand_RRfunction
2833core::core_arch::hexagon::scalarQ6_R_oror_RIfunction
2834core::core_arch::hexagon::scalarQ6_R_oror_RRfunction
2835core::core_arch::hexagon::scalarQ6_R_orxacc_RRfunction
2836core::core_arch::hexagon::scalarQ6_R_parity_PPfunction
2837core::core_arch::hexagon::scalarQ6_R_parity_RRfunction
2838core::core_arch::hexagon::scalarQ6_R_popcount_Pfunction
2839core::core_arch::hexagon::scalarQ6_R_rol_RIfunction
2840core::core_arch::hexagon::scalarQ6_R_rolacc_RIfunction
2841core::core_arch::hexagon::scalarQ6_R_roland_RIfunction
2842core::core_arch::hexagon::scalarQ6_R_rolnac_RIfunction
2843core::core_arch::hexagon::scalarQ6_R_rolor_RIfunction
2844core::core_arch::hexagon::scalarQ6_R_rolxacc_RIfunction
2845core::core_arch::hexagon::scalarQ6_R_round_P_satfunction
2846core::core_arch::hexagon::scalarQ6_R_round_RIfunction
2847core::core_arch::hexagon::scalarQ6_R_round_RI_satfunction
2848core::core_arch::hexagon::scalarQ6_R_round_RRfunction
2849core::core_arch::hexagon::scalarQ6_R_round_RR_satfunction
2850core::core_arch::hexagon::scalarQ6_R_sat_Pfunction
2851core::core_arch::hexagon::scalarQ6_R_satb_Rfunction
2852core::core_arch::hexagon::scalarQ6_R_sath_Rfunction
2853core::core_arch::hexagon::scalarQ6_R_satub_Rfunction
2854core::core_arch::hexagon::scalarQ6_R_satuh_Rfunction
2855core::core_arch::hexagon::scalarQ6_R_setbit_RIfunction
2856core::core_arch::hexagon::scalarQ6_R_setbit_RRfunction
2857core::core_arch::hexagon::scalarQ6_R_sfadd_RRfunction
2858core::core_arch::hexagon::scalarQ6_R_sffixupd_RRfunction
2859core::core_arch::hexagon::scalarQ6_R_sffixupn_RRfunction
2860core::core_arch::hexagon::scalarQ6_R_sffixupr_Rfunction
2861core::core_arch::hexagon::scalarQ6_R_sfmake_I_negfunction
2862core::core_arch::hexagon::scalarQ6_R_sfmake_I_posfunction
2863core::core_arch::hexagon::scalarQ6_R_sfmax_RRfunction
2864core::core_arch::hexagon::scalarQ6_R_sfmin_RRfunction
2865core::core_arch::hexagon::scalarQ6_R_sfmpy_RRfunction
2866core::core_arch::hexagon::scalarQ6_R_sfmpyacc_RRfunction
2867core::core_arch::hexagon::scalarQ6_R_sfmpyacc_RR_libfunction
2868core::core_arch::hexagon::scalarQ6_R_sfmpyacc_RRp_scalefunction
2869core::core_arch::hexagon::scalarQ6_R_sfmpynac_RRfunction
2870core::core_arch::hexagon::scalarQ6_R_sfmpynac_RR_libfunction
2871core::core_arch::hexagon::scalarQ6_R_sfsub_RRfunction
2872core::core_arch::hexagon::scalarQ6_R_sub_IRfunction
2873core::core_arch::hexagon::scalarQ6_R_sub_RRfunction
2874core::core_arch::hexagon::scalarQ6_R_sub_RR_satfunction
2875core::core_arch::hexagon::scalarQ6_R_sub_RhRh_s16function
2876core::core_arch::hexagon::scalarQ6_R_sub_RhRh_sat_s16function
2877core::core_arch::hexagon::scalarQ6_R_sub_RhRl_s16function
2878core::core_arch::hexagon::scalarQ6_R_sub_RhRl_sat_s16function
2879core::core_arch::hexagon::scalarQ6_R_sub_RlRhfunction
2880core::core_arch::hexagon::scalarQ6_R_sub_RlRh_s16function
2881core::core_arch::hexagon::scalarQ6_R_sub_RlRh_satfunction
2882core::core_arch::hexagon::scalarQ6_R_sub_RlRh_sat_s16function
2883core::core_arch::hexagon::scalarQ6_R_sub_RlRlfunction
2884core::core_arch::hexagon::scalarQ6_R_sub_RlRl_s16function
2885core::core_arch::hexagon::scalarQ6_R_sub_RlRl_satfunction
2886core::core_arch::hexagon::scalarQ6_R_sub_RlRl_sat_s16function
2887core::core_arch::hexagon::scalarQ6_R_sub_asl_IRIfunction
2888core::core_arch::hexagon::scalarQ6_R_sub_lsr_IRIfunction
2889core::core_arch::hexagon::scalarQ6_R_subacc_RRfunction
2890core::core_arch::hexagon::scalarQ6_R_swiz_Rfunction
2891core::core_arch::hexagon::scalarQ6_R_sxtb_Rfunction
2892core::core_arch::hexagon::scalarQ6_R_sxth_Rfunction
2893core::core_arch::hexagon::scalarQ6_R_tableidxb_RIIfunction
2894core::core_arch::hexagon::scalarQ6_R_tableidxd_RIIfunction
2895core::core_arch::hexagon::scalarQ6_R_tableidxh_RIIfunction
2896core::core_arch::hexagon::scalarQ6_R_tableidxw_RIIfunction
2897core::core_arch::hexagon::scalarQ6_R_togglebit_RIfunction
2898core::core_arch::hexagon::scalarQ6_R_togglebit_RRfunction
2899core::core_arch::hexagon::scalarQ6_R_vaddh_RRfunction
2900core::core_arch::hexagon::scalarQ6_R_vaddh_RR_satfunction
2901core::core_arch::hexagon::scalarQ6_R_vaddhub_PP_satfunction
2902core::core_arch::hexagon::scalarQ6_R_vadduh_RR_satfunction
2903core::core_arch::hexagon::scalarQ6_R_vasrhub_PI_rnd_satfunction
2904core::core_arch::hexagon::scalarQ6_R_vasrhub_PI_satfunction
2905core::core_arch::hexagon::scalarQ6_R_vasrw_PIfunction
2906core::core_arch::hexagon::scalarQ6_R_vasrw_PRfunction
2907core::core_arch::hexagon::scalarQ6_R_vavgh_RRfunction
2908core::core_arch::hexagon::scalarQ6_R_vavgh_RR_rndfunction
2909core::core_arch::hexagon::scalarQ6_R_vdmpy_PP_rnd_satfunction
2910core::core_arch::hexagon::scalarQ6_R_vdmpy_PP_s1_rnd_satfunction
2911core::core_arch::hexagon::scalarQ6_R_vitpack_ppfunction
2912core::core_arch::hexagon::scalarQ6_R_vmpyh_RR_rnd_satfunction
2913core::core_arch::hexagon::scalarQ6_R_vmpyh_RR_s1_rnd_satfunction
2914core::core_arch::hexagon::scalarQ6_R_vnavgh_RRfunction
2915core::core_arch::hexagon::scalarQ6_R_vraddh_PPfunction
2916core::core_arch::hexagon::scalarQ6_R_vradduh_PPfunction
2917core::core_arch::hexagon::scalarQ6_R_vrcmpys_PR_s1_rnd_satfunction
2918core::core_arch::hexagon::scalarQ6_R_vrndwh_Pfunction
2919core::core_arch::hexagon::scalarQ6_R_vrndwh_P_satfunction
2920core::core_arch::hexagon::scalarQ6_R_vsathb_Pfunction
2921core::core_arch::hexagon::scalarQ6_R_vsathb_Rfunction
2922core::core_arch::hexagon::scalarQ6_R_vsathub_Pfunction
2923core::core_arch::hexagon::scalarQ6_R_vsathub_Rfunction
2924core::core_arch::hexagon::scalarQ6_R_vsatwh_Pfunction
2925core::core_arch::hexagon::scalarQ6_R_vsatwuh_Pfunction
2926core::core_arch::hexagon::scalarQ6_R_vsplatb_Rfunction
2927core::core_arch::hexagon::scalarQ6_R_vsubh_RRfunction
2928core::core_arch::hexagon::scalarQ6_R_vsubh_RR_satfunction
2929core::core_arch::hexagon::scalarQ6_R_vsubuh_RR_satfunction
2930core::core_arch::hexagon::scalarQ6_R_vtrunehb_Pfunction
2931core::core_arch::hexagon::scalarQ6_R_vtrunohb_Pfunction
2932core::core_arch::hexagon::scalarQ6_R_xor_RRfunction
2933core::core_arch::hexagon::scalarQ6_R_xorand_RRfunction
2934core::core_arch::hexagon::scalarQ6_R_xoror_RRfunction
2935core::core_arch::hexagon::scalarQ6_R_xorxacc_RRfunction
2936core::core_arch::hexagon::scalarQ6_R_zxtb_Rfunction
2937core::core_arch::hexagon::scalarQ6_R_zxth_Rfunction
2938core::core_arch::hexagon::scalarQ6_Rh_equals_Ifunction
2939core::core_arch::hexagon::scalarQ6_Rl_equals_Ifunction
2940core::core_arch::hexagon::scalarQ6_dccleana_Afunction
2941core::core_arch::hexagon::scalarQ6_dccleaninva_Afunction
2942core::core_arch::hexagon::scalarQ6_dcfetch_Afunction
2943core::core_arch::hexagon::scalarQ6_dcinva_Afunction
2944core::core_arch::hexagon::scalarQ6_dczeroa_Afunction
2945core::core_arch::hexagon::scalarQ6_dmlink_AAfunction
2946core::core_arch::hexagon::scalarQ6_dmresume_Afunction
2947core::core_arch::hexagon::scalarQ6_dmstart_Afunction
2948core::core_arch::hexagon::scalarQ6_l2fetch_APfunction
2949core::core_arch::hexagon::scalarQ6_l2fetch_ARfunction
2950core::core_arch::hexagon::scalarQ6_p_all8_pfunction
2951core::core_arch::hexagon::scalarQ6_p_and_and_ppnpfunction
2952core::core_arch::hexagon::scalarQ6_p_and_and_pppfunction
2953core::core_arch::hexagon::scalarQ6_p_and_or_ppnpfunction
2954core::core_arch::hexagon::scalarQ6_p_and_or_pppfunction
2955core::core_arch::hexagon::scalarQ6_p_and_pnpfunction
2956core::core_arch::hexagon::scalarQ6_p_and_ppfunction
2957core::core_arch::hexagon::scalarQ6_p_any8_pfunction
2958core::core_arch::hexagon::scalarQ6_p_any8_vcmpb_eq_PPfunction
2959core::core_arch::hexagon::scalarQ6_p_bitsclr_RIfunction
2960core::core_arch::hexagon::scalarQ6_p_bitsclr_RRfunction
2961core::core_arch::hexagon::scalarQ6_p_bitsset_RRfunction
2962core::core_arch::hexagon::scalarQ6_p_boundscheck_RPfunction
2963core::core_arch::hexagon::scalarQ6_p_cmp_eq_PPfunction
2964core::core_arch::hexagon::scalarQ6_p_cmp_eq_RIfunction
2965core::core_arch::hexagon::scalarQ6_p_cmp_eq_RRfunction
2966core::core_arch::hexagon::scalarQ6_p_cmp_ge_RIfunction
2967core::core_arch::hexagon::scalarQ6_p_cmp_geu_RIfunction
2968core::core_arch::hexagon::scalarQ6_p_cmp_gt_PPfunction
2969core::core_arch::hexagon::scalarQ6_p_cmp_gt_RIfunction
2970core::core_arch::hexagon::scalarQ6_p_cmp_gt_RRfunction
2971core::core_arch::hexagon::scalarQ6_p_cmp_gtu_PPfunction
2972core::core_arch::hexagon::scalarQ6_p_cmp_gtu_RIfunction
2973core::core_arch::hexagon::scalarQ6_p_cmp_gtu_RRfunction
2974core::core_arch::hexagon::scalarQ6_p_cmp_lt_RRfunction
2975core::core_arch::hexagon::scalarQ6_p_cmp_ltu_RRfunction
2976core::core_arch::hexagon::scalarQ6_p_cmpb_eq_RIfunction
2977core::core_arch::hexagon::scalarQ6_p_cmpb_eq_RRfunction
2978core::core_arch::hexagon::scalarQ6_p_cmpb_gt_RIfunction
2979core::core_arch::hexagon::scalarQ6_p_cmpb_gt_RRfunction
2980core::core_arch::hexagon::scalarQ6_p_cmpb_gtu_RIfunction
2981core::core_arch::hexagon::scalarQ6_p_cmpb_gtu_RRfunction
2982core::core_arch::hexagon::scalarQ6_p_cmph_eq_RIfunction
2983core::core_arch::hexagon::scalarQ6_p_cmph_eq_RRfunction
2984core::core_arch::hexagon::scalarQ6_p_cmph_gt_RIfunction
2985core::core_arch::hexagon::scalarQ6_p_cmph_gt_RRfunction
2986core::core_arch::hexagon::scalarQ6_p_cmph_gtu_RIfunction
2987core::core_arch::hexagon::scalarQ6_p_cmph_gtu_RRfunction
2988core::core_arch::hexagon::scalarQ6_p_dfclass_PIfunction
2989core::core_arch::hexagon::scalarQ6_p_dfcmp_eq_PPfunction
2990core::core_arch::hexagon::scalarQ6_p_dfcmp_ge_PPfunction
2991core::core_arch::hexagon::scalarQ6_p_dfcmp_gt_PPfunction
2992core::core_arch::hexagon::scalarQ6_p_dfcmp_uo_PPfunction
2993core::core_arch::hexagon::scalarQ6_p_equals_Rfunction
2994core::core_arch::hexagon::scalarQ6_p_equals_pfunction
2995core::core_arch::hexagon::scalarQ6_p_fastcorner9_ppfunction
2996core::core_arch::hexagon::scalarQ6_p_not_any8_vcmpb_eq_PPfunction
2997core::core_arch::hexagon::scalarQ6_p_not_bitsclr_RIfunction
2998core::core_arch::hexagon::scalarQ6_p_not_bitsclr_RRfunction
2999core::core_arch::hexagon::scalarQ6_p_not_bitsset_RRfunction
3000core::core_arch::hexagon::scalarQ6_p_not_cmp_eq_RIfunction
3001core::core_arch::hexagon::scalarQ6_p_not_cmp_eq_RRfunction
3002core::core_arch::hexagon::scalarQ6_p_not_cmp_gt_RIfunction
3003core::core_arch::hexagon::scalarQ6_p_not_cmp_gt_RRfunction
3004core::core_arch::hexagon::scalarQ6_p_not_cmp_gtu_RIfunction
3005core::core_arch::hexagon::scalarQ6_p_not_cmp_gtu_RRfunction
3006core::core_arch::hexagon::scalarQ6_p_not_fastcorner9_ppfunction
3007core::core_arch::hexagon::scalarQ6_p_not_pfunction
3008core::core_arch::hexagon::scalarQ6_p_not_tstbit_RIfunction
3009core::core_arch::hexagon::scalarQ6_p_not_tstbit_RRfunction
3010core::core_arch::hexagon::scalarQ6_p_or_and_ppnpfunction
3011core::core_arch::hexagon::scalarQ6_p_or_and_pppfunction
3012core::core_arch::hexagon::scalarQ6_p_or_or_ppnpfunction
3013core::core_arch::hexagon::scalarQ6_p_or_or_pppfunction
3014core::core_arch::hexagon::scalarQ6_p_or_pnpfunction
3015core::core_arch::hexagon::scalarQ6_p_or_ppfunction
3016core::core_arch::hexagon::scalarQ6_p_sfclass_RIfunction
3017core::core_arch::hexagon::scalarQ6_p_sfcmp_eq_RRfunction
3018core::core_arch::hexagon::scalarQ6_p_sfcmp_ge_RRfunction
3019core::core_arch::hexagon::scalarQ6_p_sfcmp_gt_RRfunction
3020core::core_arch::hexagon::scalarQ6_p_sfcmp_uo_RRfunction
3021core::core_arch::hexagon::scalarQ6_p_tlbmatch_PRfunction
3022core::core_arch::hexagon::scalarQ6_p_tstbit_RIfunction
3023core::core_arch::hexagon::scalarQ6_p_tstbit_RRfunction
3024core::core_arch::hexagon::scalarQ6_p_vcmpb_eq_PIfunction
3025core::core_arch::hexagon::scalarQ6_p_vcmpb_eq_PPfunction
3026core::core_arch::hexagon::scalarQ6_p_vcmpb_gt_PIfunction
3027core::core_arch::hexagon::scalarQ6_p_vcmpb_gt_PPfunction
3028core::core_arch::hexagon::scalarQ6_p_vcmpb_gtu_PIfunction
3029core::core_arch::hexagon::scalarQ6_p_vcmpb_gtu_PPfunction
3030core::core_arch::hexagon::scalarQ6_p_vcmph_eq_PIfunction
3031core::core_arch::hexagon::scalarQ6_p_vcmph_eq_PPfunction
3032core::core_arch::hexagon::scalarQ6_p_vcmph_gt_PIfunction
3033core::core_arch::hexagon::scalarQ6_p_vcmph_gt_PPfunction
3034core::core_arch::hexagon::scalarQ6_p_vcmph_gtu_PIfunction
3035core::core_arch::hexagon::scalarQ6_p_vcmph_gtu_PPfunction
3036core::core_arch::hexagon::scalarQ6_p_vcmpw_eq_PIfunction
3037core::core_arch::hexagon::scalarQ6_p_vcmpw_eq_PPfunction
3038core::core_arch::hexagon::scalarQ6_p_vcmpw_gt_PIfunction
3039core::core_arch::hexagon::scalarQ6_p_vcmpw_gt_PPfunction
3040core::core_arch::hexagon::scalarQ6_p_vcmpw_gtu_PIfunction
3041core::core_arch::hexagon::scalarQ6_p_vcmpw_gtu_PPfunction
3042core::core_arch::hexagon::scalarQ6_p_xor_ppfunction
3043core::core_arch::hexagon::v128Q6_Q_and_QQfunction
3044core::core_arch::hexagon::v128Q6_Q_and_QQnfunction
3045core::core_arch::hexagon::v128Q6_Q_not_Qfunction
3046core::core_arch::hexagon::v128Q6_Q_or_QQfunction
3047core::core_arch::hexagon::v128Q6_Q_or_QQnfunction
3048core::core_arch::hexagon::v128Q6_Q_vand_VRfunction
3049core::core_arch::hexagon::v128Q6_Q_vandor_QVRfunction
3050core::core_arch::hexagon::v128Q6_Q_vcmp_eq_VbVbfunction
3051core::core_arch::hexagon::v128Q6_Q_vcmp_eq_VhVhfunction
3052core::core_arch::hexagon::v128Q6_Q_vcmp_eq_VwVwfunction
3053core::core_arch::hexagon::v128Q6_Q_vcmp_eqand_QVbVbfunction
3054core::core_arch::hexagon::v128Q6_Q_vcmp_eqand_QVhVhfunction
3055core::core_arch::hexagon::v128Q6_Q_vcmp_eqand_QVwVwfunction
3056core::core_arch::hexagon::v128Q6_Q_vcmp_eqor_QVbVbfunction
3057core::core_arch::hexagon::v128Q6_Q_vcmp_eqor_QVhVhfunction
3058core::core_arch::hexagon::v128Q6_Q_vcmp_eqor_QVwVwfunction
3059core::core_arch::hexagon::v128Q6_Q_vcmp_eqxacc_QVbVbfunction
3060core::core_arch::hexagon::v128Q6_Q_vcmp_eqxacc_QVhVhfunction
3061core::core_arch::hexagon::v128Q6_Q_vcmp_eqxacc_QVwVwfunction
3062core::core_arch::hexagon::v128Q6_Q_vcmp_gt_VbVbfunction
3063core::core_arch::hexagon::v128Q6_Q_vcmp_gt_VhVhfunction
3064core::core_arch::hexagon::v128Q6_Q_vcmp_gt_VhfVhffunction
3065core::core_arch::hexagon::v128Q6_Q_vcmp_gt_VsfVsffunction
3066core::core_arch::hexagon::v128Q6_Q_vcmp_gt_VubVubfunction
3067core::core_arch::hexagon::v128Q6_Q_vcmp_gt_VuhVuhfunction
3068core::core_arch::hexagon::v128Q6_Q_vcmp_gt_VuwVuwfunction
3069core::core_arch::hexagon::v128Q6_Q_vcmp_gt_VwVwfunction
3070core::core_arch::hexagon::v128Q6_Q_vcmp_gtand_QVbVbfunction
3071core::core_arch::hexagon::v128Q6_Q_vcmp_gtand_QVhVhfunction
3072core::core_arch::hexagon::v128Q6_Q_vcmp_gtand_QVhfVhffunction
3073core::core_arch::hexagon::v128Q6_Q_vcmp_gtand_QVsfVsffunction
3074core::core_arch::hexagon::v128Q6_Q_vcmp_gtand_QVubVubfunction
3075core::core_arch::hexagon::v128Q6_Q_vcmp_gtand_QVuhVuhfunction
3076core::core_arch::hexagon::v128Q6_Q_vcmp_gtand_QVuwVuwfunction
3077core::core_arch::hexagon::v128Q6_Q_vcmp_gtand_QVwVwfunction
3078core::core_arch::hexagon::v128Q6_Q_vcmp_gtor_QVbVbfunction
3079core::core_arch::hexagon::v128Q6_Q_vcmp_gtor_QVhVhfunction
3080core::core_arch::hexagon::v128Q6_Q_vcmp_gtor_QVhfVhffunction
3081core::core_arch::hexagon::v128Q6_Q_vcmp_gtor_QVsfVsffunction
3082core::core_arch::hexagon::v128Q6_Q_vcmp_gtor_QVubVubfunction
3083core::core_arch::hexagon::v128Q6_Q_vcmp_gtor_QVuhVuhfunction
3084core::core_arch::hexagon::v128Q6_Q_vcmp_gtor_QVuwVuwfunction
3085core::core_arch::hexagon::v128Q6_Q_vcmp_gtor_QVwVwfunction
3086core::core_arch::hexagon::v128Q6_Q_vcmp_gtxacc_QVbVbfunction
3087core::core_arch::hexagon::v128Q6_Q_vcmp_gtxacc_QVhVhfunction
3088core::core_arch::hexagon::v128Q6_Q_vcmp_gtxacc_QVhfVhffunction
3089core::core_arch::hexagon::v128Q6_Q_vcmp_gtxacc_QVsfVsffunction
3090core::core_arch::hexagon::v128Q6_Q_vcmp_gtxacc_QVubVubfunction
3091core::core_arch::hexagon::v128Q6_Q_vcmp_gtxacc_QVuhVuhfunction
3092core::core_arch::hexagon::v128Q6_Q_vcmp_gtxacc_QVuwVuwfunction
3093core::core_arch::hexagon::v128Q6_Q_vcmp_gtxacc_QVwVwfunction
3094core::core_arch::hexagon::v128Q6_Q_vsetq2_Rfunction
3095core::core_arch::hexagon::v128Q6_Q_vsetq_Rfunction
3096core::core_arch::hexagon::v128Q6_Q_xor_QQfunction
3097core::core_arch::hexagon::v128Q6_Qb_vshuffe_QhQhfunction
3098core::core_arch::hexagon::v128Q6_Qh_vshuffe_QwQwfunction
3099core::core_arch::hexagon::v128Q6_R_vextract_VRfunction
3100core::core_arch::hexagon::v128Q6_V_equals_Vfunction
3101core::core_arch::hexagon::v128Q6_V_hi_Wfunction
3102core::core_arch::hexagon::v128Q6_V_lo_Wfunction
3103core::core_arch::hexagon::v128Q6_V_vabs_Vfunction
3104core::core_arch::hexagon::v128Q6_V_valign_VVIfunction
3105core::core_arch::hexagon::v128Q6_V_valign_VVRfunction
3106core::core_arch::hexagon::v128Q6_V_vand_QRfunction
3107core::core_arch::hexagon::v128Q6_V_vand_QVfunction
3108core::core_arch::hexagon::v128Q6_V_vand_QnRfunction
3109core::core_arch::hexagon::v128Q6_V_vand_QnVfunction
3110core::core_arch::hexagon::v128Q6_V_vand_VVfunction
3111core::core_arch::hexagon::v128Q6_V_vandor_VQRfunction
3112core::core_arch::hexagon::v128Q6_V_vandor_VQnRfunction
3113core::core_arch::hexagon::v128Q6_V_vdelta_VVfunction
3114core::core_arch::hexagon::v128Q6_V_vfmax_VVfunction
3115core::core_arch::hexagon::v128Q6_V_vfmin_VVfunction
3116core::core_arch::hexagon::v128Q6_V_vfneg_Vfunction
3117core::core_arch::hexagon::v128Q6_V_vgetqfext_VRfunction
3118core::core_arch::hexagon::v128Q6_V_vlalign_VVIfunction
3119core::core_arch::hexagon::v128Q6_V_vlalign_VVRfunction
3120core::core_arch::hexagon::v128Q6_V_vmux_QVVfunction
3121core::core_arch::hexagon::v128Q6_V_vnot_Vfunction
3122core::core_arch::hexagon::v128Q6_V_vor_VVfunction
3123core::core_arch::hexagon::v128Q6_V_vrdelta_VVfunction
3124core::core_arch::hexagon::v128Q6_V_vror_VRfunction
3125core::core_arch::hexagon::v128Q6_V_vsetqfext_VRfunction
3126core::core_arch::hexagon::v128Q6_V_vsplat_Rfunction
3127core::core_arch::hexagon::v128Q6_V_vxor_VVfunction
3128core::core_arch::hexagon::v128Q6_V_vzerofunction
3129core::core_arch::hexagon::v128Q6_Vb_condacc_QVbVbfunction
3130core::core_arch::hexagon::v128Q6_Vb_condacc_QnVbVbfunction
3131core::core_arch::hexagon::v128Q6_Vb_condnac_QVbVbfunction
3132core::core_arch::hexagon::v128Q6_Vb_condnac_QnVbVbfunction
3133core::core_arch::hexagon::v128Q6_Vb_prefixsum_Qfunction
3134core::core_arch::hexagon::v128Q6_Vb_vabs_Vbfunction
3135core::core_arch::hexagon::v128Q6_Vb_vabs_Vb_satfunction
3136core::core_arch::hexagon::v128Q6_Vb_vadd_VbVbfunction
3137core::core_arch::hexagon::v128Q6_Vb_vadd_VbVb_satfunction
3138core::core_arch::hexagon::v128Q6_Vb_vasr_VhVhR_rnd_satfunction
3139core::core_arch::hexagon::v128Q6_Vb_vasr_VhVhR_satfunction
3140core::core_arch::hexagon::v128Q6_Vb_vavg_VbVbfunction
3141core::core_arch::hexagon::v128Q6_Vb_vavg_VbVb_rndfunction
3142core::core_arch::hexagon::v128Q6_Vb_vcvt_VhfVhffunction
3143core::core_arch::hexagon::v128Q6_Vb_vdeal_Vbfunction
3144core::core_arch::hexagon::v128Q6_Vb_vdeale_VbVbfunction
3145core::core_arch::hexagon::v128Q6_Vb_vlut32_VbVbIfunction
3146core::core_arch::hexagon::v128Q6_Vb_vlut32_VbVbRfunction
3147core::core_arch::hexagon::v128Q6_Vb_vlut32_VbVbR_nomatchfunction
3148core::core_arch::hexagon::v128Q6_Vb_vlut32or_VbVbVbIfunction
3149core::core_arch::hexagon::v128Q6_Vb_vlut32or_VbVbVbRfunction
3150core::core_arch::hexagon::v128Q6_Vb_vmax_VbVbfunction
3151core::core_arch::hexagon::v128Q6_Vb_vmin_VbVbfunction
3152core::core_arch::hexagon::v128Q6_Vb_vnavg_VbVbfunction
3153core::core_arch::hexagon::v128Q6_Vb_vnavg_VubVubfunction
3154core::core_arch::hexagon::v128Q6_Vb_vpack_VhVh_satfunction
3155core::core_arch::hexagon::v128Q6_Vb_vpacke_VhVhfunction
3156core::core_arch::hexagon::v128Q6_Vb_vpacko_VhVhfunction
3157core::core_arch::hexagon::v128Q6_Vb_vround_VhVh_satfunction
3158core::core_arch::hexagon::v128Q6_Vb_vshuff_Vbfunction
3159core::core_arch::hexagon::v128Q6_Vb_vshuffe_VbVbfunction
3160core::core_arch::hexagon::v128Q6_Vb_vshuffo_VbVbfunction
3161core::core_arch::hexagon::v128Q6_Vb_vsplat_Rfunction
3162core::core_arch::hexagon::v128Q6_Vb_vsub_VbVbfunction
3163core::core_arch::hexagon::v128Q6_Vb_vsub_VbVb_satfunction
3164core::core_arch::hexagon::v128Q6_Vh_condacc_QVhVhfunction
3165core::core_arch::hexagon::v128Q6_Vh_condacc_QnVhVhfunction
3166core::core_arch::hexagon::v128Q6_Vh_condnac_QVhVhfunction
3167core::core_arch::hexagon::v128Q6_Vh_condnac_QnVhVhfunction
3168core::core_arch::hexagon::v128Q6_Vh_equals_Vhffunction
3169core::core_arch::hexagon::v128Q6_Vh_prefixsum_Qfunction
3170core::core_arch::hexagon::v128Q6_Vh_vabs_Vhfunction
3171core::core_arch::hexagon::v128Q6_Vh_vabs_Vh_satfunction
3172core::core_arch::hexagon::v128Q6_Vh_vadd_VhVhfunction
3173core::core_arch::hexagon::v128Q6_Vh_vadd_VhVh_satfunction
3174core::core_arch::hexagon::v128Q6_Vh_vadd_vclb_VhVhfunction
3175core::core_arch::hexagon::v128Q6_Vh_vasl_VhRfunction
3176core::core_arch::hexagon::v128Q6_Vh_vasl_VhVhfunction
3177core::core_arch::hexagon::v128Q6_Vh_vaslacc_VhVhRfunction
3178core::core_arch::hexagon::v128Q6_Vh_vasr_VhRfunction
3179core::core_arch::hexagon::v128Q6_Vh_vasr_VhVhfunction
3180core::core_arch::hexagon::v128Q6_Vh_vasr_VwVwRfunction
3181core::core_arch::hexagon::v128Q6_Vh_vasr_VwVwR_rnd_satfunction
3182core::core_arch::hexagon::v128Q6_Vh_vasr_VwVwR_satfunction
3183core::core_arch::hexagon::v128Q6_Vh_vasracc_VhVhRfunction
3184core::core_arch::hexagon::v128Q6_Vh_vavg_VhVhfunction
3185core::core_arch::hexagon::v128Q6_Vh_vavg_VhVh_rndfunction
3186core::core_arch::hexagon::v128Q6_Vh_vcvt_Vhffunction
3187core::core_arch::hexagon::v128Q6_Vh_vdeal_Vhfunction
3188core::core_arch::hexagon::v128Q6_Vh_vdmpy_VubRbfunction
3189core::core_arch::hexagon::v128Q6_Vh_vdmpyacc_VhVubRbfunction
3190core::core_arch::hexagon::v128Q6_Vh_vlsr_VhVhfunction
3191core::core_arch::hexagon::v128Q6_Vh_vmax_VhVhfunction
3192core::core_arch::hexagon::v128Q6_Vh_vmin_VhVhfunction
3193core::core_arch::hexagon::v128Q6_Vh_vmpy_VhRh_s1_rnd_satfunction
3194core::core_arch::hexagon::v128Q6_Vh_vmpy_VhRh_s1_satfunction
3195core::core_arch::hexagon::v128Q6_Vh_vmpy_VhVh_s1_rnd_satfunction
3196core::core_arch::hexagon::v128Q6_Vh_vmpyi_VhRbfunction
3197core::core_arch::hexagon::v128Q6_Vh_vmpyi_VhVhfunction
3198core::core_arch::hexagon::v128Q6_Vh_vmpyiacc_VhVhRbfunction
3199core::core_arch::hexagon::v128Q6_Vh_vmpyiacc_VhVhVhfunction
3200core::core_arch::hexagon::v128Q6_Vh_vnavg_VhVhfunction
3201core::core_arch::hexagon::v128Q6_Vh_vnormamt_Vhfunction
3202core::core_arch::hexagon::v128Q6_Vh_vpack_VwVw_satfunction
3203core::core_arch::hexagon::v128Q6_Vh_vpacke_VwVwfunction
3204core::core_arch::hexagon::v128Q6_Vh_vpacko_VwVwfunction
3205core::core_arch::hexagon::v128Q6_Vh_vpopcount_Vhfunction
3206core::core_arch::hexagon::v128Q6_Vh_vround_VwVw_satfunction
3207core::core_arch::hexagon::v128Q6_Vh_vsat_VwVwfunction
3208core::core_arch::hexagon::v128Q6_Vh_vshuff_Vhfunction
3209core::core_arch::hexagon::v128Q6_Vh_vshuffe_VhVhfunction
3210core::core_arch::hexagon::v128Q6_Vh_vshuffo_VhVhfunction
3211core::core_arch::hexagon::v128Q6_Vh_vsplat_Rfunction
3212core::core_arch::hexagon::v128Q6_Vh_vsub_VhVhfunction
3213core::core_arch::hexagon::v128Q6_Vh_vsub_VhVh_satfunction
3214core::core_arch::hexagon::v128Q6_Vhf_equals_Vhfunction
3215core::core_arch::hexagon::v128Q6_Vhf_equals_Vqf16function
3216core::core_arch::hexagon::v128Q6_Vhf_equals_Wqf32function
3217core::core_arch::hexagon::v128Q6_Vhf_vabs_Vhffunction
3218core::core_arch::hexagon::v128Q6_Vhf_vadd_VhfVhffunction
3219core::core_arch::hexagon::v128Q6_Vhf_vcvt_Vhfunction
3220core::core_arch::hexagon::v128Q6_Vhf_vcvt_VsfVsffunction
3221core::core_arch::hexagon::v128Q6_Vhf_vcvt_Vuhfunction
3222core::core_arch::hexagon::v128Q6_Vhf_vfmax_VhfVhffunction
3223core::core_arch::hexagon::v128Q6_Vhf_vfmin_VhfVhffunction
3224core::core_arch::hexagon::v128Q6_Vhf_vfneg_Vhffunction
3225core::core_arch::hexagon::v128Q6_Vhf_vmax_VhfVhffunction
3226core::core_arch::hexagon::v128Q6_Vhf_vmin_VhfVhffunction
3227core::core_arch::hexagon::v128Q6_Vhf_vmpy_VhfVhffunction
3228core::core_arch::hexagon::v128Q6_Vhf_vmpyacc_VhfVhfVhffunction
3229core::core_arch::hexagon::v128Q6_Vhf_vsub_VhfVhffunction
3230core::core_arch::hexagon::v128Q6_Vqf16_vadd_VhfVhffunction
3231core::core_arch::hexagon::v128Q6_Vqf16_vadd_Vqf16Vhffunction
3232core::core_arch::hexagon::v128Q6_Vqf16_vadd_Vqf16Vqf16function
3233core::core_arch::hexagon::v128Q6_Vqf16_vmpy_VhfVhffunction
3234core::core_arch::hexagon::v128Q6_Vqf16_vmpy_Vqf16Vhffunction
3235core::core_arch::hexagon::v128Q6_Vqf16_vmpy_Vqf16Vqf16function
3236core::core_arch::hexagon::v128Q6_Vqf16_vsub_VhfVhffunction
3237core::core_arch::hexagon::v128Q6_Vqf16_vsub_Vqf16Vhffunction
3238core::core_arch::hexagon::v128Q6_Vqf16_vsub_Vqf16Vqf16function
3239core::core_arch::hexagon::v128Q6_Vqf32_vadd_Vqf32Vqf32function
3240core::core_arch::hexagon::v128Q6_Vqf32_vadd_Vqf32Vsffunction
3241core::core_arch::hexagon::v128Q6_Vqf32_vadd_VsfVsffunction
3242core::core_arch::hexagon::v128Q6_Vqf32_vmpy_Vqf32Vqf32function
3243core::core_arch::hexagon::v128Q6_Vqf32_vmpy_VsfVsffunction
3244core::core_arch::hexagon::v128Q6_Vqf32_vsub_Vqf32Vqf32function
3245core::core_arch::hexagon::v128Q6_Vqf32_vsub_Vqf32Vsffunction
3246core::core_arch::hexagon::v128Q6_Vqf32_vsub_VsfVsffunction
3247core::core_arch::hexagon::v128Q6_Vsf_equals_Vqf32function
3248core::core_arch::hexagon::v128Q6_Vsf_equals_Vwfunction
3249core::core_arch::hexagon::v128Q6_Vsf_vabs_Vsffunction
3250core::core_arch::hexagon::v128Q6_Vsf_vadd_VsfVsffunction
3251core::core_arch::hexagon::v128Q6_Vsf_vdmpy_VhfVhffunction
3252core::core_arch::hexagon::v128Q6_Vsf_vdmpyacc_VsfVhfVhffunction
3253core::core_arch::hexagon::v128Q6_Vsf_vfmax_VsfVsffunction
3254core::core_arch::hexagon::v128Q6_Vsf_vfmin_VsfVsffunction
3255core::core_arch::hexagon::v128Q6_Vsf_vfneg_Vsffunction
3256core::core_arch::hexagon::v128Q6_Vsf_vmax_VsfVsffunction
3257core::core_arch::hexagon::v128Q6_Vsf_vmin_VsfVsffunction
3258core::core_arch::hexagon::v128Q6_Vsf_vmpy_VsfVsffunction
3259core::core_arch::hexagon::v128Q6_Vsf_vsub_VsfVsffunction
3260core::core_arch::hexagon::v128Q6_Vub_vabsdiff_VubVubfunction
3261core::core_arch::hexagon::v128Q6_Vub_vadd_VubVb_satfunction
3262core::core_arch::hexagon::v128Q6_Vub_vadd_VubVub_satfunction
3263core::core_arch::hexagon::v128Q6_Vub_vasr_VhVhR_rnd_satfunction
3264core::core_arch::hexagon::v128Q6_Vub_vasr_VhVhR_satfunction
3265core::core_arch::hexagon::v128Q6_Vub_vasr_VuhVuhR_rnd_satfunction
3266core::core_arch::hexagon::v128Q6_Vub_vasr_VuhVuhR_satfunction
3267core::core_arch::hexagon::v128Q6_Vub_vasr_WuhVub_rnd_satfunction
3268core::core_arch::hexagon::v128Q6_Vub_vasr_WuhVub_satfunction
3269core::core_arch::hexagon::v128Q6_Vub_vavg_VubVubfunction
3270core::core_arch::hexagon::v128Q6_Vub_vavg_VubVub_rndfunction
3271core::core_arch::hexagon::v128Q6_Vub_vcvt_VhfVhffunction
3272core::core_arch::hexagon::v128Q6_Vub_vlsr_VubRfunction
3273core::core_arch::hexagon::v128Q6_Vub_vmax_VubVubfunction
3274core::core_arch::hexagon::v128Q6_Vub_vmin_VubVubfunction
3275core::core_arch::hexagon::v128Q6_Vub_vpack_VhVh_satfunction
3276core::core_arch::hexagon::v128Q6_Vub_vround_VhVh_satfunction
3277core::core_arch::hexagon::v128Q6_Vub_vround_VuhVuh_satfunction
3278core::core_arch::hexagon::v128Q6_Vub_vsat_VhVhfunction
3279core::core_arch::hexagon::v128Q6_Vub_vsub_VubVb_satfunction
3280core::core_arch::hexagon::v128Q6_Vub_vsub_VubVub_satfunction
3281core::core_arch::hexagon::v128Q6_Vuh_vabsdiff_VhVhfunction
3282core::core_arch::hexagon::v128Q6_Vuh_vabsdiff_VuhVuhfunction
3283core::core_arch::hexagon::v128Q6_Vuh_vadd_VuhVuh_satfunction
3284core::core_arch::hexagon::v128Q6_Vuh_vasr_VuwVuwR_rnd_satfunction
3285core::core_arch::hexagon::v128Q6_Vuh_vasr_VuwVuwR_satfunction
3286core::core_arch::hexagon::v128Q6_Vuh_vasr_VwVwR_rnd_satfunction
3287core::core_arch::hexagon::v128Q6_Vuh_vasr_VwVwR_satfunction
3288core::core_arch::hexagon::v128Q6_Vuh_vasr_WwVuh_rnd_satfunction
3289core::core_arch::hexagon::v128Q6_Vuh_vasr_WwVuh_satfunction
3290core::core_arch::hexagon::v128Q6_Vuh_vavg_VuhVuhfunction
3291core::core_arch::hexagon::v128Q6_Vuh_vavg_VuhVuh_rndfunction
3292core::core_arch::hexagon::v128Q6_Vuh_vcl0_Vuhfunction
3293core::core_arch::hexagon::v128Q6_Vuh_vcvt_Vhffunction
3294core::core_arch::hexagon::v128Q6_Vuh_vlsr_VuhRfunction
3295core::core_arch::hexagon::v128Q6_Vuh_vmax_VuhVuhfunction
3296core::core_arch::hexagon::v128Q6_Vuh_vmin_VuhVuhfunction
3297core::core_arch::hexagon::v128Q6_Vuh_vmpy_VuhVuh_rs16function
3298core::core_arch::hexagon::v128Q6_Vuh_vpack_VwVw_satfunction
3299core::core_arch::hexagon::v128Q6_Vuh_vround_VuwVuw_satfunction
3300core::core_arch::hexagon::v128Q6_Vuh_vround_VwVw_satfunction
3301core::core_arch::hexagon::v128Q6_Vuh_vsat_VuwVuwfunction
3302core::core_arch::hexagon::v128Q6_Vuh_vsub_VuhVuh_satfunction
3303core::core_arch::hexagon::v128Q6_Vuw_vabsdiff_VwVwfunction
3304core::core_arch::hexagon::v128Q6_Vuw_vadd_VuwVuw_satfunction
3305core::core_arch::hexagon::v128Q6_Vuw_vavg_VuwVuwfunction
3306core::core_arch::hexagon::v128Q6_Vuw_vavg_VuwVuw_rndfunction
3307core::core_arch::hexagon::v128Q6_Vuw_vcl0_Vuwfunction
3308core::core_arch::hexagon::v128Q6_Vuw_vlsr_VuwRfunction
3309core::core_arch::hexagon::v128Q6_Vuw_vmpye_VuhRuhfunction
3310core::core_arch::hexagon::v128Q6_Vuw_vmpyeacc_VuwVuhRuhfunction
3311core::core_arch::hexagon::v128Q6_Vuw_vrmpy_VubRubfunction
3312core::core_arch::hexagon::v128Q6_Vuw_vrmpy_VubVubfunction
3313core::core_arch::hexagon::v128Q6_Vuw_vrmpyacc_VuwVubRubfunction
3314core::core_arch::hexagon::v128Q6_Vuw_vrmpyacc_VuwVubVubfunction
3315core::core_arch::hexagon::v128Q6_Vuw_vrotr_VuwVuwfunction
3316core::core_arch::hexagon::v128Q6_Vuw_vsub_VuwVuw_satfunction
3317core::core_arch::hexagon::v128Q6_Vw_condacc_QVwVwfunction
3318core::core_arch::hexagon::v128Q6_Vw_condacc_QnVwVwfunction
3319core::core_arch::hexagon::v128Q6_Vw_condnac_QVwVwfunction
3320core::core_arch::hexagon::v128Q6_Vw_condnac_QnVwVwfunction
3321core::core_arch::hexagon::v128Q6_Vw_equals_Vsffunction
3322core::core_arch::hexagon::v128Q6_Vw_prefixsum_Qfunction
3323core::core_arch::hexagon::v128Q6_Vw_vabs_Vwfunction
3324core::core_arch::hexagon::v128Q6_Vw_vabs_Vw_satfunction
3325core::core_arch::hexagon::v128Q6_Vw_vadd_VwVwfunction
3326core::core_arch::hexagon::v128Q6_Vw_vadd_VwVwQ_carry_satfunction
3327core::core_arch::hexagon::v128Q6_Vw_vadd_VwVw_satfunction
3328core::core_arch::hexagon::v128Q6_Vw_vadd_vclb_VwVwfunction
3329core::core_arch::hexagon::v128Q6_Vw_vasl_VwRfunction
3330core::core_arch::hexagon::v128Q6_Vw_vasl_VwVwfunction
3331core::core_arch::hexagon::v128Q6_Vw_vaslacc_VwVwRfunction
3332core::core_arch::hexagon::v128Q6_Vw_vasr_VwRfunction
3333core::core_arch::hexagon::v128Q6_Vw_vasr_VwVwfunction
3334core::core_arch::hexagon::v128Q6_Vw_vasracc_VwVwRfunction
3335core::core_arch::hexagon::v128Q6_Vw_vavg_VwVwfunction
3336core::core_arch::hexagon::v128Q6_Vw_vavg_VwVw_rndfunction
3337core::core_arch::hexagon::v128Q6_Vw_vdmpy_VhRbfunction
3338core::core_arch::hexagon::v128Q6_Vw_vdmpy_VhRh_satfunction
3339core::core_arch::hexagon::v128Q6_Vw_vdmpy_VhRuh_satfunction
3340core::core_arch::hexagon::v128Q6_Vw_vdmpy_VhVh_satfunction
3341core::core_arch::hexagon::v128Q6_Vw_vdmpy_WhRh_satfunction
3342core::core_arch::hexagon::v128Q6_Vw_vdmpy_WhRuh_satfunction
3343core::core_arch::hexagon::v128Q6_Vw_vdmpyacc_VwVhRbfunction
3344core::core_arch::hexagon::v128Q6_Vw_vdmpyacc_VwVhRh_satfunction
3345core::core_arch::hexagon::v128Q6_Vw_vdmpyacc_VwVhRuh_satfunction
3346core::core_arch::hexagon::v128Q6_Vw_vdmpyacc_VwVhVh_satfunction
3347core::core_arch::hexagon::v128Q6_Vw_vdmpyacc_VwWhRh_satfunction
3348core::core_arch::hexagon::v128Q6_Vw_vdmpyacc_VwWhRuh_satfunction
3349core::core_arch::hexagon::v128Q6_Vw_vfmv_Vwfunction
3350core::core_arch::hexagon::v128Q6_Vw_vinsert_VwRfunction
3351core::core_arch::hexagon::v128Q6_Vw_vlsr_VwVwfunction
3352core::core_arch::hexagon::v128Q6_Vw_vmax_VwVwfunction
3353core::core_arch::hexagon::v128Q6_Vw_vmin_VwVwfunction
3354core::core_arch::hexagon::v128Q6_Vw_vmpye_VwVuhfunction
3355core::core_arch::hexagon::v128Q6_Vw_vmpyi_VwRbfunction
3356core::core_arch::hexagon::v128Q6_Vw_vmpyi_VwRhfunction
3357core::core_arch::hexagon::v128Q6_Vw_vmpyi_VwRubfunction
3358core::core_arch::hexagon::v128Q6_Vw_vmpyiacc_VwVwRbfunction
3359core::core_arch::hexagon::v128Q6_Vw_vmpyiacc_VwVwRhfunction
3360core::core_arch::hexagon::v128Q6_Vw_vmpyiacc_VwVwRubfunction
3361core::core_arch::hexagon::v128Q6_Vw_vmpyie_VwVuhfunction
3362core::core_arch::hexagon::v128Q6_Vw_vmpyieacc_VwVwVhfunction
3363core::core_arch::hexagon::v128Q6_Vw_vmpyieacc_VwVwVuhfunction
3364core::core_arch::hexagon::v128Q6_Vw_vmpyieo_VhVhfunction
3365core::core_arch::hexagon::v128Q6_Vw_vmpyio_VwVhfunction
3366core::core_arch::hexagon::v128Q6_Vw_vmpyo_VwVh_s1_rnd_satfunction
3367core::core_arch::hexagon::v128Q6_Vw_vmpyo_VwVh_s1_satfunction
3368core::core_arch::hexagon::v128Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shiftfunction
3369core::core_arch::hexagon::v128Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shiftfunction
3370core::core_arch::hexagon::v128Q6_Vw_vnavg_VwVwfunction
3371core::core_arch::hexagon::v128Q6_Vw_vnormamt_Vwfunction
3372core::core_arch::hexagon::v128Q6_Vw_vrmpy_VbVbfunction
3373core::core_arch::hexagon::v128Q6_Vw_vrmpy_VubRbfunction
3374core::core_arch::hexagon::v128Q6_Vw_vrmpy_VubVbfunction
3375core::core_arch::hexagon::v128Q6_Vw_vrmpyacc_VwVbVbfunction
3376core::core_arch::hexagon::v128Q6_Vw_vrmpyacc_VwVubRbfunction
3377core::core_arch::hexagon::v128Q6_Vw_vrmpyacc_VwVubVbfunction
3378core::core_arch::hexagon::v128Q6_Vw_vsatdw_VwVwfunction
3379core::core_arch::hexagon::v128Q6_Vw_vsub_VwVwfunction
3380core::core_arch::hexagon::v128Q6_Vw_vsub_VwVw_satfunction
3381core::core_arch::hexagon::v128Q6_W_equals_Wfunction
3382core::core_arch::hexagon::v128Q6_W_vcombine_VVfunction
3383core::core_arch::hexagon::v128Q6_W_vdeal_VVRfunction
3384core::core_arch::hexagon::v128Q6_W_vmpye_VwVuhfunction
3385core::core_arch::hexagon::v128Q6_W_vmpyoacc_WVwVhfunction
3386core::core_arch::hexagon::v128Q6_W_vshuff_VVRfunction
3387core::core_arch::hexagon::v128Q6_W_vswap_QVVfunction
3388core::core_arch::hexagon::v128Q6_W_vzerofunction
3389core::core_arch::hexagon::v128Q6_Wb_vadd_WbWbfunction
3390core::core_arch::hexagon::v128Q6_Wb_vadd_WbWb_satfunction
3391core::core_arch::hexagon::v128Q6_Wb_vshuffoe_VbVbfunction
3392core::core_arch::hexagon::v128Q6_Wb_vsub_WbWbfunction
3393core::core_arch::hexagon::v128Q6_Wb_vsub_WbWb_satfunction
3394core::core_arch::hexagon::v128Q6_Wh_vadd_VubVubfunction
3395core::core_arch::hexagon::v128Q6_Wh_vadd_WhWhfunction
3396core::core_arch::hexagon::v128Q6_Wh_vadd_WhWh_satfunction
3397core::core_arch::hexagon::v128Q6_Wh_vaddacc_WhVubVubfunction
3398core::core_arch::hexagon::v128Q6_Wh_vdmpy_WubRbfunction
3399core::core_arch::hexagon::v128Q6_Wh_vdmpyacc_WhWubRbfunction
3400core::core_arch::hexagon::v128Q6_Wh_vlut16_VbVhIfunction
3401core::core_arch::hexagon::v128Q6_Wh_vlut16_VbVhRfunction
3402core::core_arch::hexagon::v128Q6_Wh_vlut16_VbVhR_nomatchfunction
3403core::core_arch::hexagon::v128Q6_Wh_vlut16or_WhVbVhIfunction
3404core::core_arch::hexagon::v128Q6_Wh_vlut16or_WhVbVhRfunction
3405core::core_arch::hexagon::v128Q6_Wh_vmpa_WubRbfunction
3406core::core_arch::hexagon::v128Q6_Wh_vmpa_WubRubfunction
3407core::core_arch::hexagon::v128Q6_Wh_vmpa_WubWbfunction
3408core::core_arch::hexagon::v128Q6_Wh_vmpa_WubWubfunction
3409core::core_arch::hexagon::v128Q6_Wh_vmpaacc_WhWubRbfunction
3410core::core_arch::hexagon::v128Q6_Wh_vmpaacc_WhWubRubfunction
3411core::core_arch::hexagon::v128Q6_Wh_vmpy_VbVbfunction
3412core::core_arch::hexagon::v128Q6_Wh_vmpy_VubRbfunction
3413core::core_arch::hexagon::v128Q6_Wh_vmpy_VubVbfunction
3414core::core_arch::hexagon::v128Q6_Wh_vmpyacc_WhVbVbfunction
3415core::core_arch::hexagon::v128Q6_Wh_vmpyacc_WhVubRbfunction
3416core::core_arch::hexagon::v128Q6_Wh_vmpyacc_WhVubVbfunction
3417core::core_arch::hexagon::v128Q6_Wh_vshuffoe_VhVhfunction
3418core::core_arch::hexagon::v128Q6_Wh_vsub_VubVubfunction
3419core::core_arch::hexagon::v128Q6_Wh_vsub_WhWhfunction
3420core::core_arch::hexagon::v128Q6_Wh_vsub_WhWh_satfunction
3421core::core_arch::hexagon::v128Q6_Wh_vsxt_Vbfunction
3422core::core_arch::hexagon::v128Q6_Wh_vtmpy_WbRbfunction
3423core::core_arch::hexagon::v128Q6_Wh_vtmpy_WubRbfunction
3424core::core_arch::hexagon::v128Q6_Wh_vtmpyacc_WhWbRbfunction
3425core::core_arch::hexagon::v128Q6_Wh_vtmpyacc_WhWubRbfunction
3426core::core_arch::hexagon::v128Q6_Wh_vunpack_Vbfunction
3427core::core_arch::hexagon::v128Q6_Wh_vunpackoor_WhVbfunction
3428core::core_arch::hexagon::v128Q6_Whf_vcvt2_Vbfunction
3429core::core_arch::hexagon::v128Q6_Whf_vcvt2_Vubfunction
3430core::core_arch::hexagon::v128Q6_Whf_vcvt_Vfunction
3431core::core_arch::hexagon::v128Q6_Whf_vcvt_Vbfunction
3432core::core_arch::hexagon::v128Q6_Whf_vcvt_Vubfunction
3433core::core_arch::hexagon::v128Q6_Wqf32_vmpy_VhfVhffunction
3434core::core_arch::hexagon::v128Q6_Wqf32_vmpy_Vqf16Vhffunction
3435core::core_arch::hexagon::v128Q6_Wqf32_vmpy_Vqf16Vqf16function
3436core::core_arch::hexagon::v128Q6_Wsf_vadd_VhfVhffunction
3437core::core_arch::hexagon::v128Q6_Wsf_vcvt_Vhffunction
3438core::core_arch::hexagon::v128Q6_Wsf_vmpy_VhfVhffunction
3439core::core_arch::hexagon::v128Q6_Wsf_vmpyacc_WsfVhfVhffunction
3440core::core_arch::hexagon::v128Q6_Wsf_vsub_VhfVhffunction
3441core::core_arch::hexagon::v128Q6_Wub_vadd_WubWub_satfunction
3442core::core_arch::hexagon::v128Q6_Wub_vsub_WubWub_satfunction
3443core::core_arch::hexagon::v128Q6_Wuh_vadd_WuhWuh_satfunction
3444core::core_arch::hexagon::v128Q6_Wuh_vmpy_VubRubfunction
3445core::core_arch::hexagon::v128Q6_Wuh_vmpy_VubVubfunction
3446core::core_arch::hexagon::v128Q6_Wuh_vmpyacc_WuhVubRubfunction
3447core::core_arch::hexagon::v128Q6_Wuh_vmpyacc_WuhVubVubfunction
3448core::core_arch::hexagon::v128Q6_Wuh_vsub_WuhWuh_satfunction
3449core::core_arch::hexagon::v128Q6_Wuh_vunpack_Vubfunction
3450core::core_arch::hexagon::v128Q6_Wuh_vzxt_Vubfunction
3451core::core_arch::hexagon::v128Q6_Wuw_vadd_WuwWuw_satfunction
3452core::core_arch::hexagon::v128Q6_Wuw_vdsad_WuhRuhfunction
3453core::core_arch::hexagon::v128Q6_Wuw_vdsadacc_WuwWuhRuhfunction
3454core::core_arch::hexagon::v128Q6_Wuw_vmpy_VuhRuhfunction
3455core::core_arch::hexagon::v128Q6_Wuw_vmpy_VuhVuhfunction
3456core::core_arch::hexagon::v128Q6_Wuw_vmpyacc_WuwVuhRuhfunction
3457core::core_arch::hexagon::v128Q6_Wuw_vmpyacc_WuwVuhVuhfunction
3458core::core_arch::hexagon::v128Q6_Wuw_vrmpy_WubRubIfunction
3459core::core_arch::hexagon::v128Q6_Wuw_vrmpyacc_WuwWubRubIfunction
3460core::core_arch::hexagon::v128Q6_Wuw_vrsad_WubRubIfunction
3461core::core_arch::hexagon::v128Q6_Wuw_vrsadacc_WuwWubRubIfunction
3462core::core_arch::hexagon::v128Q6_Wuw_vsub_WuwWuw_satfunction
3463core::core_arch::hexagon::v128Q6_Wuw_vunpack_Vuhfunction
3464core::core_arch::hexagon::v128Q6_Wuw_vzxt_Vuhfunction
3465core::core_arch::hexagon::v128Q6_Ww_v6mpy_WubWbI_hfunction
3466core::core_arch::hexagon::v128Q6_Ww_v6mpy_WubWbI_vfunction
3467core::core_arch::hexagon::v128Q6_Ww_v6mpyacc_WwWubWbI_hfunction
3468core::core_arch::hexagon::v128Q6_Ww_v6mpyacc_WwWubWbI_vfunction
3469core::core_arch::hexagon::v128Q6_Ww_vadd_VhVhfunction
3470core::core_arch::hexagon::v128Q6_Ww_vadd_VuhVuhfunction
3471core::core_arch::hexagon::v128Q6_Ww_vadd_WwWwfunction
3472core::core_arch::hexagon::v128Q6_Ww_vadd_WwWw_satfunction
3473core::core_arch::hexagon::v128Q6_Ww_vaddacc_WwVhVhfunction
3474core::core_arch::hexagon::v128Q6_Ww_vaddacc_WwVuhVuhfunction
3475core::core_arch::hexagon::v128Q6_Ww_vasrinto_WwVwVwfunction
3476core::core_arch::hexagon::v128Q6_Ww_vdmpy_WhRbfunction
3477core::core_arch::hexagon::v128Q6_Ww_vdmpyacc_WwWhRbfunction
3478core::core_arch::hexagon::v128Q6_Ww_vmpa_WhRbfunction
3479core::core_arch::hexagon::v128Q6_Ww_vmpa_WuhRbfunction
3480core::core_arch::hexagon::v128Q6_Ww_vmpaacc_WwWhRbfunction
3481core::core_arch::hexagon::v128Q6_Ww_vmpaacc_WwWuhRbfunction
3482core::core_arch::hexagon::v128Q6_Ww_vmpy_VhRhfunction
3483core::core_arch::hexagon::v128Q6_Ww_vmpy_VhVhfunction
3484core::core_arch::hexagon::v128Q6_Ww_vmpy_VhVuhfunction
3485core::core_arch::hexagon::v128Q6_Ww_vmpyacc_WwVhRhfunction
3486core::core_arch::hexagon::v128Q6_Ww_vmpyacc_WwVhRh_satfunction
3487core::core_arch::hexagon::v128Q6_Ww_vmpyacc_WwVhVhfunction
3488core::core_arch::hexagon::v128Q6_Ww_vmpyacc_WwVhVuhfunction
3489core::core_arch::hexagon::v128Q6_Ww_vrmpy_WubRbIfunction
3490core::core_arch::hexagon::v128Q6_Ww_vrmpyacc_WwWubRbIfunction
3491core::core_arch::hexagon::v128Q6_Ww_vsub_VhVhfunction
3492core::core_arch::hexagon::v128Q6_Ww_vsub_VuhVuhfunction
3493core::core_arch::hexagon::v128Q6_Ww_vsub_WwWwfunction
3494core::core_arch::hexagon::v128Q6_Ww_vsub_WwWw_satfunction
3495core::core_arch::hexagon::v128Q6_Ww_vsxt_Vhfunction
3496core::core_arch::hexagon::v128Q6_Ww_vtmpy_WhRbfunction
3497core::core_arch::hexagon::v128Q6_Ww_vtmpyacc_WwWhRbfunction
3498core::core_arch::hexagon::v128Q6_Ww_vunpack_Vhfunction
3499core::core_arch::hexagon::v128Q6_Ww_vunpackoor_WwVhfunction
3500core::core_arch::hexagon::v128Q6_vgather_AQRMVhfunction
3501core::core_arch::hexagon::v128Q6_vgather_AQRMVwfunction
3502core::core_arch::hexagon::v128Q6_vgather_AQRMWwfunction
3503core::core_arch::hexagon::v128Q6_vgather_ARMVhfunction
3504core::core_arch::hexagon::v128Q6_vgather_ARMVwfunction
3505core::core_arch::hexagon::v128Q6_vgather_ARMWwfunction
3506core::core_arch::hexagon::v128Q6_vmem_QRIVfunction
3507core::core_arch::hexagon::v128Q6_vmem_QRIV_ntfunction
3508core::core_arch::hexagon::v128Q6_vmem_QnRIVfunction
3509core::core_arch::hexagon::v128Q6_vmem_QnRIV_ntfunction
3510core::core_arch::hexagon::v128Q6_vscatter_QRMVhVfunction
3511core::core_arch::hexagon::v128Q6_vscatter_QRMVwVfunction
3512core::core_arch::hexagon::v128Q6_vscatter_QRMWwVfunction
3513core::core_arch::hexagon::v128Q6_vscatter_RMVhVfunction
3514core::core_arch::hexagon::v128Q6_vscatter_RMVwVfunction
3515core::core_arch::hexagon::v128Q6_vscatter_RMWwVfunction
3516core::core_arch::hexagon::v128Q6_vscatteracc_RMVhVfunction
3517core::core_arch::hexagon::v128Q6_vscatteracc_RMVwVfunction
3518core::core_arch::hexagon::v128Q6_vscatteracc_RMWwVfunction
3519core::core_arch::hexagon::v64Q6_Q_and_QQfunction
3520core::core_arch::hexagon::v64Q6_Q_and_QQnfunction
3521core::core_arch::hexagon::v64Q6_Q_not_Qfunction
3522core::core_arch::hexagon::v64Q6_Q_or_QQfunction
3523core::core_arch::hexagon::v64Q6_Q_or_QQnfunction
3524core::core_arch::hexagon::v64Q6_Q_vand_VRfunction
3525core::core_arch::hexagon::v64Q6_Q_vandor_QVRfunction
3526core::core_arch::hexagon::v64Q6_Q_vcmp_eq_VbVbfunction
3527core::core_arch::hexagon::v64Q6_Q_vcmp_eq_VhVhfunction
3528core::core_arch::hexagon::v64Q6_Q_vcmp_eq_VwVwfunction
3529core::core_arch::hexagon::v64Q6_Q_vcmp_eqand_QVbVbfunction
3530core::core_arch::hexagon::v64Q6_Q_vcmp_eqand_QVhVhfunction
3531core::core_arch::hexagon::v64Q6_Q_vcmp_eqand_QVwVwfunction
3532core::core_arch::hexagon::v64Q6_Q_vcmp_eqor_QVbVbfunction
3533core::core_arch::hexagon::v64Q6_Q_vcmp_eqor_QVhVhfunction
3534core::core_arch::hexagon::v64Q6_Q_vcmp_eqor_QVwVwfunction
3535core::core_arch::hexagon::v64Q6_Q_vcmp_eqxacc_QVbVbfunction
3536core::core_arch::hexagon::v64Q6_Q_vcmp_eqxacc_QVhVhfunction
3537core::core_arch::hexagon::v64Q6_Q_vcmp_eqxacc_QVwVwfunction
3538core::core_arch::hexagon::v64Q6_Q_vcmp_gt_VbVbfunction
3539core::core_arch::hexagon::v64Q6_Q_vcmp_gt_VhVhfunction
3540core::core_arch::hexagon::v64Q6_Q_vcmp_gt_VhfVhffunction
3541core::core_arch::hexagon::v64Q6_Q_vcmp_gt_VsfVsffunction
3542core::core_arch::hexagon::v64Q6_Q_vcmp_gt_VubVubfunction
3543core::core_arch::hexagon::v64Q6_Q_vcmp_gt_VuhVuhfunction
3544core::core_arch::hexagon::v64Q6_Q_vcmp_gt_VuwVuwfunction
3545core::core_arch::hexagon::v64Q6_Q_vcmp_gt_VwVwfunction
3546core::core_arch::hexagon::v64Q6_Q_vcmp_gtand_QVbVbfunction
3547core::core_arch::hexagon::v64Q6_Q_vcmp_gtand_QVhVhfunction
3548core::core_arch::hexagon::v64Q6_Q_vcmp_gtand_QVhfVhffunction
3549core::core_arch::hexagon::v64Q6_Q_vcmp_gtand_QVsfVsffunction
3550core::core_arch::hexagon::v64Q6_Q_vcmp_gtand_QVubVubfunction
3551core::core_arch::hexagon::v64Q6_Q_vcmp_gtand_QVuhVuhfunction
3552core::core_arch::hexagon::v64Q6_Q_vcmp_gtand_QVuwVuwfunction
3553core::core_arch::hexagon::v64Q6_Q_vcmp_gtand_QVwVwfunction
3554core::core_arch::hexagon::v64Q6_Q_vcmp_gtor_QVbVbfunction
3555core::core_arch::hexagon::v64Q6_Q_vcmp_gtor_QVhVhfunction
3556core::core_arch::hexagon::v64Q6_Q_vcmp_gtor_QVhfVhffunction
3557core::core_arch::hexagon::v64Q6_Q_vcmp_gtor_QVsfVsffunction
3558core::core_arch::hexagon::v64Q6_Q_vcmp_gtor_QVubVubfunction
3559core::core_arch::hexagon::v64Q6_Q_vcmp_gtor_QVuhVuhfunction
3560core::core_arch::hexagon::v64Q6_Q_vcmp_gtor_QVuwVuwfunction
3561core::core_arch::hexagon::v64Q6_Q_vcmp_gtor_QVwVwfunction
3562core::core_arch::hexagon::v64Q6_Q_vcmp_gtxacc_QVbVbfunction
3563core::core_arch::hexagon::v64Q6_Q_vcmp_gtxacc_QVhVhfunction
3564core::core_arch::hexagon::v64Q6_Q_vcmp_gtxacc_QVhfVhffunction
3565core::core_arch::hexagon::v64Q6_Q_vcmp_gtxacc_QVsfVsffunction
3566core::core_arch::hexagon::v64Q6_Q_vcmp_gtxacc_QVubVubfunction
3567core::core_arch::hexagon::v64Q6_Q_vcmp_gtxacc_QVuhVuhfunction
3568core::core_arch::hexagon::v64Q6_Q_vcmp_gtxacc_QVuwVuwfunction
3569core::core_arch::hexagon::v64Q6_Q_vcmp_gtxacc_QVwVwfunction
3570core::core_arch::hexagon::v64Q6_Q_vsetq2_Rfunction
3571core::core_arch::hexagon::v64Q6_Q_vsetq_Rfunction
3572core::core_arch::hexagon::v64Q6_Q_xor_QQfunction
3573core::core_arch::hexagon::v64Q6_Qb_vshuffe_QhQhfunction
3574core::core_arch::hexagon::v64Q6_Qh_vshuffe_QwQwfunction
3575core::core_arch::hexagon::v64Q6_R_vextract_VRfunction
3576core::core_arch::hexagon::v64Q6_V_equals_Vfunction
3577core::core_arch::hexagon::v64Q6_V_hi_Wfunction
3578core::core_arch::hexagon::v64Q6_V_lo_Wfunction
3579core::core_arch::hexagon::v64Q6_V_vabs_Vfunction
3580core::core_arch::hexagon::v64Q6_V_valign_VVIfunction
3581core::core_arch::hexagon::v64Q6_V_valign_VVRfunction
3582core::core_arch::hexagon::v64Q6_V_vand_QRfunction
3583core::core_arch::hexagon::v64Q6_V_vand_QVfunction
3584core::core_arch::hexagon::v64Q6_V_vand_QnRfunction
3585core::core_arch::hexagon::v64Q6_V_vand_QnVfunction
3586core::core_arch::hexagon::v64Q6_V_vand_VVfunction
3587core::core_arch::hexagon::v64Q6_V_vandor_VQRfunction
3588core::core_arch::hexagon::v64Q6_V_vandor_VQnRfunction
3589core::core_arch::hexagon::v64Q6_V_vdelta_VVfunction
3590core::core_arch::hexagon::v64Q6_V_vfmax_VVfunction
3591core::core_arch::hexagon::v64Q6_V_vfmin_VVfunction
3592core::core_arch::hexagon::v64Q6_V_vfneg_Vfunction
3593core::core_arch::hexagon::v64Q6_V_vgetqfext_VRfunction
3594core::core_arch::hexagon::v64Q6_V_vlalign_VVIfunction
3595core::core_arch::hexagon::v64Q6_V_vlalign_VVRfunction
3596core::core_arch::hexagon::v64Q6_V_vmux_QVVfunction
3597core::core_arch::hexagon::v64Q6_V_vnot_Vfunction
3598core::core_arch::hexagon::v64Q6_V_vor_VVfunction
3599core::core_arch::hexagon::v64Q6_V_vrdelta_VVfunction
3600core::core_arch::hexagon::v64Q6_V_vror_VRfunction
3601core::core_arch::hexagon::v64Q6_V_vsetqfext_VRfunction
3602core::core_arch::hexagon::v64Q6_V_vsplat_Rfunction
3603core::core_arch::hexagon::v64Q6_V_vxor_VVfunction
3604core::core_arch::hexagon::v64Q6_V_vzerofunction
3605core::core_arch::hexagon::v64Q6_Vb_condacc_QVbVbfunction
3606core::core_arch::hexagon::v64Q6_Vb_condacc_QnVbVbfunction
3607core::core_arch::hexagon::v64Q6_Vb_condnac_QVbVbfunction
3608core::core_arch::hexagon::v64Q6_Vb_condnac_QnVbVbfunction
3609core::core_arch::hexagon::v64Q6_Vb_prefixsum_Qfunction
3610core::core_arch::hexagon::v64Q6_Vb_vabs_Vbfunction
3611core::core_arch::hexagon::v64Q6_Vb_vabs_Vb_satfunction
3612core::core_arch::hexagon::v64Q6_Vb_vadd_VbVbfunction
3613core::core_arch::hexagon::v64Q6_Vb_vadd_VbVb_satfunction
3614core::core_arch::hexagon::v64Q6_Vb_vasr_VhVhR_rnd_satfunction
3615core::core_arch::hexagon::v64Q6_Vb_vasr_VhVhR_satfunction
3616core::core_arch::hexagon::v64Q6_Vb_vavg_VbVbfunction
3617core::core_arch::hexagon::v64Q6_Vb_vavg_VbVb_rndfunction
3618core::core_arch::hexagon::v64Q6_Vb_vcvt_VhfVhffunction
3619core::core_arch::hexagon::v64Q6_Vb_vdeal_Vbfunction
3620core::core_arch::hexagon::v64Q6_Vb_vdeale_VbVbfunction
3621core::core_arch::hexagon::v64Q6_Vb_vlut32_VbVbIfunction
3622core::core_arch::hexagon::v64Q6_Vb_vlut32_VbVbRfunction
3623core::core_arch::hexagon::v64Q6_Vb_vlut32_VbVbR_nomatchfunction
3624core::core_arch::hexagon::v64Q6_Vb_vlut32or_VbVbVbIfunction
3625core::core_arch::hexagon::v64Q6_Vb_vlut32or_VbVbVbRfunction
3626core::core_arch::hexagon::v64Q6_Vb_vmax_VbVbfunction
3627core::core_arch::hexagon::v64Q6_Vb_vmin_VbVbfunction
3628core::core_arch::hexagon::v64Q6_Vb_vnavg_VbVbfunction
3629core::core_arch::hexagon::v64Q6_Vb_vnavg_VubVubfunction
3630core::core_arch::hexagon::v64Q6_Vb_vpack_VhVh_satfunction
3631core::core_arch::hexagon::v64Q6_Vb_vpacke_VhVhfunction
3632core::core_arch::hexagon::v64Q6_Vb_vpacko_VhVhfunction
3633core::core_arch::hexagon::v64Q6_Vb_vround_VhVh_satfunction
3634core::core_arch::hexagon::v64Q6_Vb_vshuff_Vbfunction
3635core::core_arch::hexagon::v64Q6_Vb_vshuffe_VbVbfunction
3636core::core_arch::hexagon::v64Q6_Vb_vshuffo_VbVbfunction
3637core::core_arch::hexagon::v64Q6_Vb_vsplat_Rfunction
3638core::core_arch::hexagon::v64Q6_Vb_vsub_VbVbfunction
3639core::core_arch::hexagon::v64Q6_Vb_vsub_VbVb_satfunction
3640core::core_arch::hexagon::v64Q6_Vh_condacc_QVhVhfunction
3641core::core_arch::hexagon::v64Q6_Vh_condacc_QnVhVhfunction
3642core::core_arch::hexagon::v64Q6_Vh_condnac_QVhVhfunction
3643core::core_arch::hexagon::v64Q6_Vh_condnac_QnVhVhfunction
3644core::core_arch::hexagon::v64Q6_Vh_equals_Vhffunction
3645core::core_arch::hexagon::v64Q6_Vh_prefixsum_Qfunction
3646core::core_arch::hexagon::v64Q6_Vh_vabs_Vhfunction
3647core::core_arch::hexagon::v64Q6_Vh_vabs_Vh_satfunction
3648core::core_arch::hexagon::v64Q6_Vh_vadd_VhVhfunction
3649core::core_arch::hexagon::v64Q6_Vh_vadd_VhVh_satfunction
3650core::core_arch::hexagon::v64Q6_Vh_vadd_vclb_VhVhfunction
3651core::core_arch::hexagon::v64Q6_Vh_vasl_VhRfunction
3652core::core_arch::hexagon::v64Q6_Vh_vasl_VhVhfunction
3653core::core_arch::hexagon::v64Q6_Vh_vaslacc_VhVhRfunction
3654core::core_arch::hexagon::v64Q6_Vh_vasr_VhRfunction
3655core::core_arch::hexagon::v64Q6_Vh_vasr_VhVhfunction
3656core::core_arch::hexagon::v64Q6_Vh_vasr_VwVwRfunction
3657core::core_arch::hexagon::v64Q6_Vh_vasr_VwVwR_rnd_satfunction
3658core::core_arch::hexagon::v64Q6_Vh_vasr_VwVwR_satfunction
3659core::core_arch::hexagon::v64Q6_Vh_vasracc_VhVhRfunction
3660core::core_arch::hexagon::v64Q6_Vh_vavg_VhVhfunction
3661core::core_arch::hexagon::v64Q6_Vh_vavg_VhVh_rndfunction
3662core::core_arch::hexagon::v64Q6_Vh_vcvt_Vhffunction
3663core::core_arch::hexagon::v64Q6_Vh_vdeal_Vhfunction
3664core::core_arch::hexagon::v64Q6_Vh_vdmpy_VubRbfunction
3665core::core_arch::hexagon::v64Q6_Vh_vdmpyacc_VhVubRbfunction
3666core::core_arch::hexagon::v64Q6_Vh_vlsr_VhVhfunction
3667core::core_arch::hexagon::v64Q6_Vh_vmax_VhVhfunction
3668core::core_arch::hexagon::v64Q6_Vh_vmin_VhVhfunction
3669core::core_arch::hexagon::v64Q6_Vh_vmpy_VhRh_s1_rnd_satfunction
3670core::core_arch::hexagon::v64Q6_Vh_vmpy_VhRh_s1_satfunction
3671core::core_arch::hexagon::v64Q6_Vh_vmpy_VhVh_s1_rnd_satfunction
3672core::core_arch::hexagon::v64Q6_Vh_vmpyi_VhRbfunction
3673core::core_arch::hexagon::v64Q6_Vh_vmpyi_VhVhfunction
3674core::core_arch::hexagon::v64Q6_Vh_vmpyiacc_VhVhRbfunction
3675core::core_arch::hexagon::v64Q6_Vh_vmpyiacc_VhVhVhfunction
3676core::core_arch::hexagon::v64Q6_Vh_vnavg_VhVhfunction
3677core::core_arch::hexagon::v64Q6_Vh_vnormamt_Vhfunction
3678core::core_arch::hexagon::v64Q6_Vh_vpack_VwVw_satfunction
3679core::core_arch::hexagon::v64Q6_Vh_vpacke_VwVwfunction
3680core::core_arch::hexagon::v64Q6_Vh_vpacko_VwVwfunction
3681core::core_arch::hexagon::v64Q6_Vh_vpopcount_Vhfunction
3682core::core_arch::hexagon::v64Q6_Vh_vround_VwVw_satfunction
3683core::core_arch::hexagon::v64Q6_Vh_vsat_VwVwfunction
3684core::core_arch::hexagon::v64Q6_Vh_vshuff_Vhfunction
3685core::core_arch::hexagon::v64Q6_Vh_vshuffe_VhVhfunction
3686core::core_arch::hexagon::v64Q6_Vh_vshuffo_VhVhfunction
3687core::core_arch::hexagon::v64Q6_Vh_vsplat_Rfunction
3688core::core_arch::hexagon::v64Q6_Vh_vsub_VhVhfunction
3689core::core_arch::hexagon::v64Q6_Vh_vsub_VhVh_satfunction
3690core::core_arch::hexagon::v64Q6_Vhf_equals_Vhfunction
3691core::core_arch::hexagon::v64Q6_Vhf_equals_Vqf16function
3692core::core_arch::hexagon::v64Q6_Vhf_equals_Wqf32function
3693core::core_arch::hexagon::v64Q6_Vhf_vabs_Vhffunction
3694core::core_arch::hexagon::v64Q6_Vhf_vadd_VhfVhffunction
3695core::core_arch::hexagon::v64Q6_Vhf_vcvt_Vhfunction
3696core::core_arch::hexagon::v64Q6_Vhf_vcvt_VsfVsffunction
3697core::core_arch::hexagon::v64Q6_Vhf_vcvt_Vuhfunction
3698core::core_arch::hexagon::v64Q6_Vhf_vfmax_VhfVhffunction
3699core::core_arch::hexagon::v64Q6_Vhf_vfmin_VhfVhffunction
3700core::core_arch::hexagon::v64Q6_Vhf_vfneg_Vhffunction
3701core::core_arch::hexagon::v64Q6_Vhf_vmax_VhfVhffunction
3702core::core_arch::hexagon::v64Q6_Vhf_vmin_VhfVhffunction
3703core::core_arch::hexagon::v64Q6_Vhf_vmpy_VhfVhffunction
3704core::core_arch::hexagon::v64Q6_Vhf_vmpyacc_VhfVhfVhffunction
3705core::core_arch::hexagon::v64Q6_Vhf_vsub_VhfVhffunction
3706core::core_arch::hexagon::v64Q6_Vqf16_vadd_VhfVhffunction
3707core::core_arch::hexagon::v64Q6_Vqf16_vadd_Vqf16Vhffunction
3708core::core_arch::hexagon::v64Q6_Vqf16_vadd_Vqf16Vqf16function
3709core::core_arch::hexagon::v64Q6_Vqf16_vmpy_VhfVhffunction
3710core::core_arch::hexagon::v64Q6_Vqf16_vmpy_Vqf16Vhffunction
3711core::core_arch::hexagon::v64Q6_Vqf16_vmpy_Vqf16Vqf16function
3712core::core_arch::hexagon::v64Q6_Vqf16_vsub_VhfVhffunction
3713core::core_arch::hexagon::v64Q6_Vqf16_vsub_Vqf16Vhffunction
3714core::core_arch::hexagon::v64Q6_Vqf16_vsub_Vqf16Vqf16function
3715core::core_arch::hexagon::v64Q6_Vqf32_vadd_Vqf32Vqf32function
3716core::core_arch::hexagon::v64Q6_Vqf32_vadd_Vqf32Vsffunction
3717core::core_arch::hexagon::v64Q6_Vqf32_vadd_VsfVsffunction
3718core::core_arch::hexagon::v64Q6_Vqf32_vmpy_Vqf32Vqf32function
3719core::core_arch::hexagon::v64Q6_Vqf32_vmpy_VsfVsffunction
3720core::core_arch::hexagon::v64Q6_Vqf32_vsub_Vqf32Vqf32function
3721core::core_arch::hexagon::v64Q6_Vqf32_vsub_Vqf32Vsffunction
3722core::core_arch::hexagon::v64Q6_Vqf32_vsub_VsfVsffunction
3723core::core_arch::hexagon::v64Q6_Vsf_equals_Vqf32function
3724core::core_arch::hexagon::v64Q6_Vsf_equals_Vwfunction
3725core::core_arch::hexagon::v64Q6_Vsf_vabs_Vsffunction
3726core::core_arch::hexagon::v64Q6_Vsf_vadd_VsfVsffunction
3727core::core_arch::hexagon::v64Q6_Vsf_vdmpy_VhfVhffunction
3728core::core_arch::hexagon::v64Q6_Vsf_vdmpyacc_VsfVhfVhffunction
3729core::core_arch::hexagon::v64Q6_Vsf_vfmax_VsfVsffunction
3730core::core_arch::hexagon::v64Q6_Vsf_vfmin_VsfVsffunction
3731core::core_arch::hexagon::v64Q6_Vsf_vfneg_Vsffunction
3732core::core_arch::hexagon::v64Q6_Vsf_vmax_VsfVsffunction
3733core::core_arch::hexagon::v64Q6_Vsf_vmin_VsfVsffunction
3734core::core_arch::hexagon::v64Q6_Vsf_vmpy_VsfVsffunction
3735core::core_arch::hexagon::v64Q6_Vsf_vsub_VsfVsffunction
3736core::core_arch::hexagon::v64Q6_Vub_vabsdiff_VubVubfunction
3737core::core_arch::hexagon::v64Q6_Vub_vadd_VubVb_satfunction
3738core::core_arch::hexagon::v64Q6_Vub_vadd_VubVub_satfunction
3739core::core_arch::hexagon::v64Q6_Vub_vasr_VhVhR_rnd_satfunction
3740core::core_arch::hexagon::v64Q6_Vub_vasr_VhVhR_satfunction
3741core::core_arch::hexagon::v64Q6_Vub_vasr_VuhVuhR_rnd_satfunction
3742core::core_arch::hexagon::v64Q6_Vub_vasr_VuhVuhR_satfunction
3743core::core_arch::hexagon::v64Q6_Vub_vasr_WuhVub_rnd_satfunction
3744core::core_arch::hexagon::v64Q6_Vub_vasr_WuhVub_satfunction
3745core::core_arch::hexagon::v64Q6_Vub_vavg_VubVubfunction
3746core::core_arch::hexagon::v64Q6_Vub_vavg_VubVub_rndfunction
3747core::core_arch::hexagon::v64Q6_Vub_vcvt_VhfVhffunction
3748core::core_arch::hexagon::v64Q6_Vub_vlsr_VubRfunction
3749core::core_arch::hexagon::v64Q6_Vub_vmax_VubVubfunction
3750core::core_arch::hexagon::v64Q6_Vub_vmin_VubVubfunction
3751core::core_arch::hexagon::v64Q6_Vub_vpack_VhVh_satfunction
3752core::core_arch::hexagon::v64Q6_Vub_vround_VhVh_satfunction
3753core::core_arch::hexagon::v64Q6_Vub_vround_VuhVuh_satfunction
3754core::core_arch::hexagon::v64Q6_Vub_vsat_VhVhfunction
3755core::core_arch::hexagon::v64Q6_Vub_vsub_VubVb_satfunction
3756core::core_arch::hexagon::v64Q6_Vub_vsub_VubVub_satfunction
3757core::core_arch::hexagon::v64Q6_Vuh_vabsdiff_VhVhfunction
3758core::core_arch::hexagon::v64Q6_Vuh_vabsdiff_VuhVuhfunction
3759core::core_arch::hexagon::v64Q6_Vuh_vadd_VuhVuh_satfunction
3760core::core_arch::hexagon::v64Q6_Vuh_vasr_VuwVuwR_rnd_satfunction
3761core::core_arch::hexagon::v64Q6_Vuh_vasr_VuwVuwR_satfunction
3762core::core_arch::hexagon::v64Q6_Vuh_vasr_VwVwR_rnd_satfunction
3763core::core_arch::hexagon::v64Q6_Vuh_vasr_VwVwR_satfunction
3764core::core_arch::hexagon::v64Q6_Vuh_vasr_WwVuh_rnd_satfunction
3765core::core_arch::hexagon::v64Q6_Vuh_vasr_WwVuh_satfunction
3766core::core_arch::hexagon::v64Q6_Vuh_vavg_VuhVuhfunction
3767core::core_arch::hexagon::v64Q6_Vuh_vavg_VuhVuh_rndfunction
3768core::core_arch::hexagon::v64Q6_Vuh_vcl0_Vuhfunction
3769core::core_arch::hexagon::v64Q6_Vuh_vcvt_Vhffunction
3770core::core_arch::hexagon::v64Q6_Vuh_vlsr_VuhRfunction
3771core::core_arch::hexagon::v64Q6_Vuh_vmax_VuhVuhfunction
3772core::core_arch::hexagon::v64Q6_Vuh_vmin_VuhVuhfunction
3773core::core_arch::hexagon::v64Q6_Vuh_vmpy_VuhVuh_rs16function
3774core::core_arch::hexagon::v64Q6_Vuh_vpack_VwVw_satfunction
3775core::core_arch::hexagon::v64Q6_Vuh_vround_VuwVuw_satfunction
3776core::core_arch::hexagon::v64Q6_Vuh_vround_VwVw_satfunction
3777core::core_arch::hexagon::v64Q6_Vuh_vsat_VuwVuwfunction
3778core::core_arch::hexagon::v64Q6_Vuh_vsub_VuhVuh_satfunction
3779core::core_arch::hexagon::v64Q6_Vuw_vabsdiff_VwVwfunction
3780core::core_arch::hexagon::v64Q6_Vuw_vadd_VuwVuw_satfunction
3781core::core_arch::hexagon::v64Q6_Vuw_vavg_VuwVuwfunction
3782core::core_arch::hexagon::v64Q6_Vuw_vavg_VuwVuw_rndfunction
3783core::core_arch::hexagon::v64Q6_Vuw_vcl0_Vuwfunction
3784core::core_arch::hexagon::v64Q6_Vuw_vlsr_VuwRfunction
3785core::core_arch::hexagon::v64Q6_Vuw_vmpye_VuhRuhfunction
3786core::core_arch::hexagon::v64Q6_Vuw_vmpyeacc_VuwVuhRuhfunction
3787core::core_arch::hexagon::v64Q6_Vuw_vrmpy_VubRubfunction
3788core::core_arch::hexagon::v64Q6_Vuw_vrmpy_VubVubfunction
3789core::core_arch::hexagon::v64Q6_Vuw_vrmpyacc_VuwVubRubfunction
3790core::core_arch::hexagon::v64Q6_Vuw_vrmpyacc_VuwVubVubfunction
3791core::core_arch::hexagon::v64Q6_Vuw_vrotr_VuwVuwfunction
3792core::core_arch::hexagon::v64Q6_Vuw_vsub_VuwVuw_satfunction
3793core::core_arch::hexagon::v64Q6_Vw_condacc_QVwVwfunction
3794core::core_arch::hexagon::v64Q6_Vw_condacc_QnVwVwfunction
3795core::core_arch::hexagon::v64Q6_Vw_condnac_QVwVwfunction
3796core::core_arch::hexagon::v64Q6_Vw_condnac_QnVwVwfunction
3797core::core_arch::hexagon::v64Q6_Vw_equals_Vsffunction
3798core::core_arch::hexagon::v64Q6_Vw_prefixsum_Qfunction
3799core::core_arch::hexagon::v64Q6_Vw_vabs_Vwfunction
3800core::core_arch::hexagon::v64Q6_Vw_vabs_Vw_satfunction
3801core::core_arch::hexagon::v64Q6_Vw_vadd_VwVwfunction
3802core::core_arch::hexagon::v64Q6_Vw_vadd_VwVwQ_carry_satfunction
3803core::core_arch::hexagon::v64Q6_Vw_vadd_VwVw_satfunction
3804core::core_arch::hexagon::v64Q6_Vw_vadd_vclb_VwVwfunction
3805core::core_arch::hexagon::v64Q6_Vw_vasl_VwRfunction
3806core::core_arch::hexagon::v64Q6_Vw_vasl_VwVwfunction
3807core::core_arch::hexagon::v64Q6_Vw_vaslacc_VwVwRfunction
3808core::core_arch::hexagon::v64Q6_Vw_vasr_VwRfunction
3809core::core_arch::hexagon::v64Q6_Vw_vasr_VwVwfunction
3810core::core_arch::hexagon::v64Q6_Vw_vasracc_VwVwRfunction
3811core::core_arch::hexagon::v64Q6_Vw_vavg_VwVwfunction
3812core::core_arch::hexagon::v64Q6_Vw_vavg_VwVw_rndfunction
3813core::core_arch::hexagon::v64Q6_Vw_vdmpy_VhRbfunction
3814core::core_arch::hexagon::v64Q6_Vw_vdmpy_VhRh_satfunction
3815core::core_arch::hexagon::v64Q6_Vw_vdmpy_VhRuh_satfunction
3816core::core_arch::hexagon::v64Q6_Vw_vdmpy_VhVh_satfunction
3817core::core_arch::hexagon::v64Q6_Vw_vdmpy_WhRh_satfunction
3818core::core_arch::hexagon::v64Q6_Vw_vdmpy_WhRuh_satfunction
3819core::core_arch::hexagon::v64Q6_Vw_vdmpyacc_VwVhRbfunction
3820core::core_arch::hexagon::v64Q6_Vw_vdmpyacc_VwVhRh_satfunction
3821core::core_arch::hexagon::v64Q6_Vw_vdmpyacc_VwVhRuh_satfunction
3822core::core_arch::hexagon::v64Q6_Vw_vdmpyacc_VwVhVh_satfunction
3823core::core_arch::hexagon::v64Q6_Vw_vdmpyacc_VwWhRh_satfunction
3824core::core_arch::hexagon::v64Q6_Vw_vdmpyacc_VwWhRuh_satfunction
3825core::core_arch::hexagon::v64Q6_Vw_vfmv_Vwfunction
3826core::core_arch::hexagon::v64Q6_Vw_vinsert_VwRfunction
3827core::core_arch::hexagon::v64Q6_Vw_vlsr_VwVwfunction
3828core::core_arch::hexagon::v64Q6_Vw_vmax_VwVwfunction
3829core::core_arch::hexagon::v64Q6_Vw_vmin_VwVwfunction
3830core::core_arch::hexagon::v64Q6_Vw_vmpye_VwVuhfunction
3831core::core_arch::hexagon::v64Q6_Vw_vmpyi_VwRbfunction
3832core::core_arch::hexagon::v64Q6_Vw_vmpyi_VwRhfunction
3833core::core_arch::hexagon::v64Q6_Vw_vmpyi_VwRubfunction
3834core::core_arch::hexagon::v64Q6_Vw_vmpyiacc_VwVwRbfunction
3835core::core_arch::hexagon::v64Q6_Vw_vmpyiacc_VwVwRhfunction
3836core::core_arch::hexagon::v64Q6_Vw_vmpyiacc_VwVwRubfunction
3837core::core_arch::hexagon::v64Q6_Vw_vmpyie_VwVuhfunction
3838core::core_arch::hexagon::v64Q6_Vw_vmpyieacc_VwVwVhfunction
3839core::core_arch::hexagon::v64Q6_Vw_vmpyieacc_VwVwVuhfunction
3840core::core_arch::hexagon::v64Q6_Vw_vmpyieo_VhVhfunction
3841core::core_arch::hexagon::v64Q6_Vw_vmpyio_VwVhfunction
3842core::core_arch::hexagon::v64Q6_Vw_vmpyo_VwVh_s1_rnd_satfunction
3843core::core_arch::hexagon::v64Q6_Vw_vmpyo_VwVh_s1_satfunction
3844core::core_arch::hexagon::v64Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shiftfunction
3845core::core_arch::hexagon::v64Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shiftfunction
3846core::core_arch::hexagon::v64Q6_Vw_vnavg_VwVwfunction
3847core::core_arch::hexagon::v64Q6_Vw_vnormamt_Vwfunction
3848core::core_arch::hexagon::v64Q6_Vw_vrmpy_VbVbfunction
3849core::core_arch::hexagon::v64Q6_Vw_vrmpy_VubRbfunction
3850core::core_arch::hexagon::v64Q6_Vw_vrmpy_VubVbfunction
3851core::core_arch::hexagon::v64Q6_Vw_vrmpyacc_VwVbVbfunction
3852core::core_arch::hexagon::v64Q6_Vw_vrmpyacc_VwVubRbfunction
3853core::core_arch::hexagon::v64Q6_Vw_vrmpyacc_VwVubVbfunction
3854core::core_arch::hexagon::v64Q6_Vw_vsatdw_VwVwfunction
3855core::core_arch::hexagon::v64Q6_Vw_vsub_VwVwfunction
3856core::core_arch::hexagon::v64Q6_Vw_vsub_VwVw_satfunction
3857core::core_arch::hexagon::v64Q6_W_equals_Wfunction
3858core::core_arch::hexagon::v64Q6_W_vcombine_VVfunction
3859core::core_arch::hexagon::v64Q6_W_vdeal_VVRfunction
3860core::core_arch::hexagon::v64Q6_W_vmpye_VwVuhfunction
3861core::core_arch::hexagon::v64Q6_W_vmpyoacc_WVwVhfunction
3862core::core_arch::hexagon::v64Q6_W_vshuff_VVRfunction
3863core::core_arch::hexagon::v64Q6_W_vswap_QVVfunction
3864core::core_arch::hexagon::v64Q6_W_vzerofunction
3865core::core_arch::hexagon::v64Q6_Wb_vadd_WbWbfunction
3866core::core_arch::hexagon::v64Q6_Wb_vadd_WbWb_satfunction
3867core::core_arch::hexagon::v64Q6_Wb_vshuffoe_VbVbfunction
3868core::core_arch::hexagon::v64Q6_Wb_vsub_WbWbfunction
3869core::core_arch::hexagon::v64Q6_Wb_vsub_WbWb_satfunction
3870core::core_arch::hexagon::v64Q6_Wh_vadd_VubVubfunction
3871core::core_arch::hexagon::v64Q6_Wh_vadd_WhWhfunction
3872core::core_arch::hexagon::v64Q6_Wh_vadd_WhWh_satfunction
3873core::core_arch::hexagon::v64Q6_Wh_vaddacc_WhVubVubfunction
3874core::core_arch::hexagon::v64Q6_Wh_vdmpy_WubRbfunction
3875core::core_arch::hexagon::v64Q6_Wh_vdmpyacc_WhWubRbfunction
3876core::core_arch::hexagon::v64Q6_Wh_vlut16_VbVhIfunction
3877core::core_arch::hexagon::v64Q6_Wh_vlut16_VbVhRfunction
3878core::core_arch::hexagon::v64Q6_Wh_vlut16_VbVhR_nomatchfunction
3879core::core_arch::hexagon::v64Q6_Wh_vlut16or_WhVbVhIfunction
3880core::core_arch::hexagon::v64Q6_Wh_vlut16or_WhVbVhRfunction
3881core::core_arch::hexagon::v64Q6_Wh_vmpa_WubRbfunction
3882core::core_arch::hexagon::v64Q6_Wh_vmpa_WubRubfunction
3883core::core_arch::hexagon::v64Q6_Wh_vmpa_WubWbfunction
3884core::core_arch::hexagon::v64Q6_Wh_vmpa_WubWubfunction
3885core::core_arch::hexagon::v64Q6_Wh_vmpaacc_WhWubRbfunction
3886core::core_arch::hexagon::v64Q6_Wh_vmpaacc_WhWubRubfunction
3887core::core_arch::hexagon::v64Q6_Wh_vmpy_VbVbfunction
3888core::core_arch::hexagon::v64Q6_Wh_vmpy_VubRbfunction
3889core::core_arch::hexagon::v64Q6_Wh_vmpy_VubVbfunction
3890core::core_arch::hexagon::v64Q6_Wh_vmpyacc_WhVbVbfunction
3891core::core_arch::hexagon::v64Q6_Wh_vmpyacc_WhVubRbfunction
3892core::core_arch::hexagon::v64Q6_Wh_vmpyacc_WhVubVbfunction
3893core::core_arch::hexagon::v64Q6_Wh_vshuffoe_VhVhfunction
3894core::core_arch::hexagon::v64Q6_Wh_vsub_VubVubfunction
3895core::core_arch::hexagon::v64Q6_Wh_vsub_WhWhfunction
3896core::core_arch::hexagon::v64Q6_Wh_vsub_WhWh_satfunction
3897core::core_arch::hexagon::v64Q6_Wh_vsxt_Vbfunction
3898core::core_arch::hexagon::v64Q6_Wh_vtmpy_WbRbfunction
3899core::core_arch::hexagon::v64Q6_Wh_vtmpy_WubRbfunction
3900core::core_arch::hexagon::v64Q6_Wh_vtmpyacc_WhWbRbfunction
3901core::core_arch::hexagon::v64Q6_Wh_vtmpyacc_WhWubRbfunction
3902core::core_arch::hexagon::v64Q6_Wh_vunpack_Vbfunction
3903core::core_arch::hexagon::v64Q6_Wh_vunpackoor_WhVbfunction
3904core::core_arch::hexagon::v64Q6_Whf_vcvt2_Vbfunction
3905core::core_arch::hexagon::v64Q6_Whf_vcvt2_Vubfunction
3906core::core_arch::hexagon::v64Q6_Whf_vcvt_Vfunction
3907core::core_arch::hexagon::v64Q6_Whf_vcvt_Vbfunction
3908core::core_arch::hexagon::v64Q6_Whf_vcvt_Vubfunction
3909core::core_arch::hexagon::v64Q6_Wqf32_vmpy_VhfVhffunction
3910core::core_arch::hexagon::v64Q6_Wqf32_vmpy_Vqf16Vhffunction
3911core::core_arch::hexagon::v64Q6_Wqf32_vmpy_Vqf16Vqf16function
3912core::core_arch::hexagon::v64Q6_Wsf_vadd_VhfVhffunction
3913core::core_arch::hexagon::v64Q6_Wsf_vcvt_Vhffunction
3914core::core_arch::hexagon::v64Q6_Wsf_vmpy_VhfVhffunction
3915core::core_arch::hexagon::v64Q6_Wsf_vmpyacc_WsfVhfVhffunction
3916core::core_arch::hexagon::v64Q6_Wsf_vsub_VhfVhffunction
3917core::core_arch::hexagon::v64Q6_Wub_vadd_WubWub_satfunction
3918core::core_arch::hexagon::v64Q6_Wub_vsub_WubWub_satfunction
3919core::core_arch::hexagon::v64Q6_Wuh_vadd_WuhWuh_satfunction
3920core::core_arch::hexagon::v64Q6_Wuh_vmpy_VubRubfunction
3921core::core_arch::hexagon::v64Q6_Wuh_vmpy_VubVubfunction
3922core::core_arch::hexagon::v64Q6_Wuh_vmpyacc_WuhVubRubfunction
3923core::core_arch::hexagon::v64Q6_Wuh_vmpyacc_WuhVubVubfunction
3924core::core_arch::hexagon::v64Q6_Wuh_vsub_WuhWuh_satfunction
3925core::core_arch::hexagon::v64Q6_Wuh_vunpack_Vubfunction
3926core::core_arch::hexagon::v64Q6_Wuh_vzxt_Vubfunction
3927core::core_arch::hexagon::v64Q6_Wuw_vadd_WuwWuw_satfunction
3928core::core_arch::hexagon::v64Q6_Wuw_vdsad_WuhRuhfunction
3929core::core_arch::hexagon::v64Q6_Wuw_vdsadacc_WuwWuhRuhfunction
3930core::core_arch::hexagon::v64Q6_Wuw_vmpy_VuhRuhfunction
3931core::core_arch::hexagon::v64Q6_Wuw_vmpy_VuhVuhfunction
3932core::core_arch::hexagon::v64Q6_Wuw_vmpyacc_WuwVuhRuhfunction
3933core::core_arch::hexagon::v64Q6_Wuw_vmpyacc_WuwVuhVuhfunction
3934core::core_arch::hexagon::v64Q6_Wuw_vrmpy_WubRubIfunction
3935core::core_arch::hexagon::v64Q6_Wuw_vrmpyacc_WuwWubRubIfunction
3936core::core_arch::hexagon::v64Q6_Wuw_vrsad_WubRubIfunction
3937core::core_arch::hexagon::v64Q6_Wuw_vrsadacc_WuwWubRubIfunction
3938core::core_arch::hexagon::v64Q6_Wuw_vsub_WuwWuw_satfunction
3939core::core_arch::hexagon::v64Q6_Wuw_vunpack_Vuhfunction
3940core::core_arch::hexagon::v64Q6_Wuw_vzxt_Vuhfunction
3941core::core_arch::hexagon::v64Q6_Ww_v6mpy_WubWbI_hfunction
3942core::core_arch::hexagon::v64Q6_Ww_v6mpy_WubWbI_vfunction
3943core::core_arch::hexagon::v64Q6_Ww_v6mpyacc_WwWubWbI_hfunction
3944core::core_arch::hexagon::v64Q6_Ww_v6mpyacc_WwWubWbI_vfunction
3945core::core_arch::hexagon::v64Q6_Ww_vadd_VhVhfunction
3946core::core_arch::hexagon::v64Q6_Ww_vadd_VuhVuhfunction
3947core::core_arch::hexagon::v64Q6_Ww_vadd_WwWwfunction
3948core::core_arch::hexagon::v64Q6_Ww_vadd_WwWw_satfunction
3949core::core_arch::hexagon::v64Q6_Ww_vaddacc_WwVhVhfunction
3950core::core_arch::hexagon::v64Q6_Ww_vaddacc_WwVuhVuhfunction
3951core::core_arch::hexagon::v64Q6_Ww_vasrinto_WwVwVwfunction
3952core::core_arch::hexagon::v64Q6_Ww_vdmpy_WhRbfunction
3953core::core_arch::hexagon::v64Q6_Ww_vdmpyacc_WwWhRbfunction
3954core::core_arch::hexagon::v64Q6_Ww_vmpa_WhRbfunction
3955core::core_arch::hexagon::v64Q6_Ww_vmpa_WuhRbfunction
3956core::core_arch::hexagon::v64Q6_Ww_vmpaacc_WwWhRbfunction
3957core::core_arch::hexagon::v64Q6_Ww_vmpaacc_WwWuhRbfunction
3958core::core_arch::hexagon::v64Q6_Ww_vmpy_VhRhfunction
3959core::core_arch::hexagon::v64Q6_Ww_vmpy_VhVhfunction
3960core::core_arch::hexagon::v64Q6_Ww_vmpy_VhVuhfunction
3961core::core_arch::hexagon::v64Q6_Ww_vmpyacc_WwVhRhfunction
3962core::core_arch::hexagon::v64Q6_Ww_vmpyacc_WwVhRh_satfunction
3963core::core_arch::hexagon::v64Q6_Ww_vmpyacc_WwVhVhfunction
3964core::core_arch::hexagon::v64Q6_Ww_vmpyacc_WwVhVuhfunction
3965core::core_arch::hexagon::v64Q6_Ww_vrmpy_WubRbIfunction
3966core::core_arch::hexagon::v64Q6_Ww_vrmpyacc_WwWubRbIfunction
3967core::core_arch::hexagon::v64Q6_Ww_vsub_VhVhfunction
3968core::core_arch::hexagon::v64Q6_Ww_vsub_VuhVuhfunction
3969core::core_arch::hexagon::v64Q6_Ww_vsub_WwWwfunction
3970core::core_arch::hexagon::v64Q6_Ww_vsub_WwWw_satfunction
3971core::core_arch::hexagon::v64Q6_Ww_vsxt_Vhfunction
3972core::core_arch::hexagon::v64Q6_Ww_vtmpy_WhRbfunction
3973core::core_arch::hexagon::v64Q6_Ww_vtmpyacc_WwWhRbfunction
3974core::core_arch::hexagon::v64Q6_Ww_vunpack_Vhfunction
3975core::core_arch::hexagon::v64Q6_Ww_vunpackoor_WwVhfunction
3976core::core_arch::hexagon::v64Q6_vgather_AQRMVhfunction
3977core::core_arch::hexagon::v64Q6_vgather_AQRMVwfunction
3978core::core_arch::hexagon::v64Q6_vgather_AQRMWwfunction
3979core::core_arch::hexagon::v64Q6_vgather_ARMVhfunction
3980core::core_arch::hexagon::v64Q6_vgather_ARMVwfunction
3981core::core_arch::hexagon::v64Q6_vgather_ARMWwfunction
3982core::core_arch::hexagon::v64Q6_vmem_QRIVfunction
3983core::core_arch::hexagon::v64Q6_vmem_QRIV_ntfunction
3984core::core_arch::hexagon::v64Q6_vmem_QnRIVfunction
3985core::core_arch::hexagon::v64Q6_vmem_QnRIV_ntfunction
3986core::core_arch::hexagon::v64Q6_vscatter_QRMVhVfunction
3987core::core_arch::hexagon::v64Q6_vscatter_QRMVwVfunction
3988core::core_arch::hexagon::v64Q6_vscatter_QRMWwVfunction
3989core::core_arch::hexagon::v64Q6_vscatter_RMVhVfunction
3990core::core_arch::hexagon::v64Q6_vscatter_RMVwVfunction
3991core::core_arch::hexagon::v64Q6_vscatter_RMWwVfunction
3992core::core_arch::hexagon::v64Q6_vscatteracc_RMVhVfunction
3993core::core_arch::hexagon::v64Q6_vscatteracc_RMVwVfunction
3994core::core_arch::hexagon::v64Q6_vscatteracc_RMWwVfunction
3995core::core_arch::loongarch32cacopfunction
3996core::core_arch::loongarch32csrrdfunction
3997core::core_arch::loongarch32csrwrfunction
3998core::core_arch::loongarch32csrxchgfunction
3999core::core_arch::loongarch64asrtgtfunction
4000core::core_arch::loongarch64asrtlefunction
4001core::core_arch::loongarch64cacopfunction
4002core::core_arch::loongarch64csrrdfunction
4003core::core_arch::loongarch64csrwrfunction
4004core::core_arch::loongarch64csrxchgfunction
4005core::core_arch::loongarch64iocsrrd_dfunction
4006core::core_arch::loongarch64iocsrwr_dfunction
4007core::core_arch::loongarch64lddirfunction
4008core::core_arch::loongarch64ldptefunction
4009core::core_arch::loongarch64::lasx::generatedlasx_xvldrepl_bfunction
4010core::core_arch::loongarch64::lasx::generatedlasx_xvldrepl_dfunction
4011core::core_arch::loongarch64::lasx::generatedlasx_xvldrepl_hfunction
4012core::core_arch::loongarch64::lasx::generatedlasx_xvldrepl_wfunction
4013core::core_arch::loongarch64::lasx::generatedlasx_xvstelm_bfunction
4014core::core_arch::loongarch64::lasx::generatedlasx_xvstelm_dfunction
4015core::core_arch::loongarch64::lasx::generatedlasx_xvstelm_hfunction
4016core::core_arch::loongarch64::lasx::generatedlasx_xvstelm_wfunction
4017core::core_arch::loongarch64::lasx::portablelasx_xvldfunction
4018core::core_arch::loongarch64::lasx::portablelasx_xvldxfunction
4019core::core_arch::loongarch64::lasx::portablelasx_xvstfunction
4020core::core_arch::loongarch64::lasx::portablelasx_xvstxfunction
4021core::core_arch::loongarch64::lsx::generatedlsx_vldrepl_bfunction
4022core::core_arch::loongarch64::lsx::generatedlsx_vldrepl_dfunction
4023core::core_arch::loongarch64::lsx::generatedlsx_vldrepl_hfunction
4024core::core_arch::loongarch64::lsx::generatedlsx_vldrepl_wfunction
4025core::core_arch::loongarch64::lsx::generatedlsx_vstelm_bfunction
4026core::core_arch::loongarch64::lsx::generatedlsx_vstelm_dfunction
4027core::core_arch::loongarch64::lsx::generatedlsx_vstelm_hfunction
4028core::core_arch::loongarch64::lsx::generatedlsx_vstelm_wfunction
4029core::core_arch::loongarch64::lsx::portablelsx_vldfunction
4030core::core_arch::loongarch64::lsx::portablelsx_vldxfunction
4031core::core_arch::loongarch64::lsx::portablelsx_vstfunction
4032core::core_arch::loongarch64::lsx::portablelsx_vstxfunction
4033core::core_arch::loongarch_sharedbrkfunction
4034core::core_arch::loongarch_sharediocsrrd_bfunction
4035core::core_arch::loongarch_sharediocsrrd_hfunction
4036core::core_arch::loongarch_sharediocsrrd_wfunction
4037core::core_arch::loongarch_sharediocsrwr_bfunction
4038core::core_arch::loongarch_sharediocsrwr_hfunction
4039core::core_arch::loongarch_sharediocsrwr_wfunction
4040core::core_arch::loongarch_sharedmovgr2fcsrfunction
4041core::core_arch::loongarch_sharedsyscallfunction
4042core::core_arch::mipsbreak_function
4043core::core_arch::nvptx__assert_failfunction
4044core::core_arch::nvptx_block_dim_xfunction
4045core::core_arch::nvptx_block_dim_yfunction
4046core::core_arch::nvptx_block_dim_zfunction
4047core::core_arch::nvptx_block_idx_xfunction
4048core::core_arch::nvptx_block_idx_yfunction
4049core::core_arch::nvptx_block_idx_zfunction
4050core::core_arch::nvptx_grid_dim_xfunction
4051core::core_arch::nvptx_grid_dim_yfunction
4052core::core_arch::nvptx_grid_dim_zfunction
4053core::core_arch::nvptx_syncthreadsfunction
4054core::core_arch::nvptx_thread_idx_xfunction
4055core::core_arch::nvptx_thread_idx_yfunction
4056core::core_arch::nvptx_thread_idx_zfunction
4057core::core_arch::nvptxfreefunction
4058core::core_arch::nvptxmallocfunction
4059core::core_arch::nvptxtrapfunction
4060core::core_arch::nvptxvprintffunction
4061core::core_arch::nvptx::packedf16x2_addfunction
4062core::core_arch::nvptx::packedf16x2_fmafunction
4063core::core_arch::nvptx::packedf16x2_maxfunction
4064core::core_arch::nvptx::packedf16x2_max_nanfunction
4065core::core_arch::nvptx::packedf16x2_minfunction
4066core::core_arch::nvptx::packedf16x2_min_nanfunction
4067core::core_arch::nvptx::packedf16x2_mulfunction
4068core::core_arch::nvptx::packedf16x2_negfunction
4069core::core_arch::nvptx::packedf16x2_subfunction
4070core::core_arch::powerpctrapfunction
4071core::core_arch::powerpc64::vsxvec_xl_lenfunction
4072core::core_arch::powerpc64::vsxvec_xst_lenfunction
4073core::core_arch::powerpc64::vsx::sealed::VectorXloadsvec_xl_lentrait_method
4074core::core_arch::powerpc64::vsx::sealed::VectorXstoresvec_xst_lentrait_method
4075core::core_arch::powerpc::altivecvec_absfunction
4076core::core_arch::powerpc::altivecvec_abssfunction
4077core::core_arch::powerpc::altivecvec_addfunction
4078core::core_arch::powerpc::altivecvec_addcfunction
4079core::core_arch::powerpc::altivecvec_addefunction
4080core::core_arch::powerpc::altivecvec_addsfunction
4081core::core_arch::powerpc::altivecvec_all_eqfunction
4082core::core_arch::powerpc::altivecvec_all_gefunction
4083core::core_arch::powerpc::altivecvec_all_gtfunction
4084core::core_arch::powerpc::altivecvec_all_infunction
4085core::core_arch::powerpc::altivecvec_all_lefunction
4086core::core_arch::powerpc::altivecvec_all_ltfunction
4087core::core_arch::powerpc::altivecvec_all_nanfunction
4088core::core_arch::powerpc::altivecvec_all_nefunction
4089core::core_arch::powerpc::altivecvec_all_ngefunction
4090core::core_arch::powerpc::altivecvec_all_ngtfunction
4091core::core_arch::powerpc::altivecvec_all_nlefunction
4092core::core_arch::powerpc::altivecvec_all_nltfunction
4093core::core_arch::powerpc::altivecvec_all_numericfunction
4094core::core_arch::powerpc::altivecvec_andfunction
4095core::core_arch::powerpc::altivecvec_andcfunction
4096core::core_arch::powerpc::altivecvec_any_eqfunction
4097core::core_arch::powerpc::altivecvec_any_gefunction
4098core::core_arch::powerpc::altivecvec_any_gtfunction
4099core::core_arch::powerpc::altivecvec_any_lefunction
4100core::core_arch::powerpc::altivecvec_any_ltfunction
4101core::core_arch::powerpc::altivecvec_any_nanfunction
4102core::core_arch::powerpc::altivecvec_any_nefunction
4103core::core_arch::powerpc::altivecvec_any_ngefunction
4104core::core_arch::powerpc::altivecvec_any_ngtfunction
4105core::core_arch::powerpc::altivecvec_any_nlefunction
4106core::core_arch::powerpc::altivecvec_any_nltfunction
4107core::core_arch::powerpc::altivecvec_any_numericfunction
4108core::core_arch::powerpc::altivecvec_any_outfunction
4109core::core_arch::powerpc::altivecvec_avgfunction
4110core::core_arch::powerpc::altivecvec_ceilfunction
4111core::core_arch::powerpc::altivecvec_cmpbfunction
4112core::core_arch::powerpc::altivecvec_cmpeqfunction
4113core::core_arch::powerpc::altivecvec_cmpgefunction
4114core::core_arch::powerpc::altivecvec_cmpgtfunction
4115core::core_arch::powerpc::altivecvec_cmplefunction
4116core::core_arch::powerpc::altivecvec_cmpltfunction
4117core::core_arch::powerpc::altivecvec_cmpnefunction
4118core::core_arch::powerpc::altivecvec_cntlzfunction
4119core::core_arch::powerpc::altivecvec_ctffunction
4120core::core_arch::powerpc::altivecvec_ctsfunction
4121core::core_arch::powerpc::altivecvec_ctufunction
4122core::core_arch::powerpc::altivecvec_exptefunction
4123core::core_arch::powerpc::altivecvec_extractfunction
4124core::core_arch::powerpc::altivecvec_floorfunction
4125core::core_arch::powerpc::altivecvec_insertfunction
4126core::core_arch::powerpc::altivecvec_ldfunction
4127core::core_arch::powerpc::altivecvec_ldefunction
4128core::core_arch::powerpc::altivecvec_ldlfunction
4129core::core_arch::powerpc::altivecvec_logefunction
4130core::core_arch::powerpc::altivecvec_maddfunction
4131core::core_arch::powerpc::altivecvec_maddsfunction
4132core::core_arch::powerpc::altivecvec_maxfunction
4133core::core_arch::powerpc::altivecvec_mergehfunction
4134core::core_arch::powerpc::altivecvec_mergelfunction
4135core::core_arch::powerpc::altivecvec_mfvscrfunction
4136core::core_arch::powerpc::altivecvec_minfunction
4137core::core_arch::powerpc::altivecvec_mladdfunction
4138core::core_arch::powerpc::altivecvec_mraddsfunction
4139core::core_arch::powerpc::altivecvec_msumfunction
4140core::core_arch::powerpc::altivecvec_msumsfunction
4141core::core_arch::powerpc::altivecvec_mulfunction
4142core::core_arch::powerpc::altivecvec_nandfunction
4143core::core_arch::powerpc::altivecvec_negfunction
4144core::core_arch::powerpc::altivecvec_nmsubfunction
4145core::core_arch::powerpc::altivecvec_norfunction
4146core::core_arch::powerpc::altivecvec_orfunction
4147core::core_arch::powerpc::altivecvec_orcfunction
4148core::core_arch::powerpc::altivecvec_packfunction
4149core::core_arch::powerpc::altivecvec_packsfunction
4150core::core_arch::powerpc::altivecvec_packsufunction
4151core::core_arch::powerpc::altivecvec_rlfunction
4152core::core_arch::powerpc::altivecvec_roundfunction
4153core::core_arch::powerpc::altivecvec_selfunction
4154core::core_arch::powerpc::altivecvec_slfunction
4155core::core_arch::powerpc::altivecvec_sldfunction
4156core::core_arch::powerpc::altivecvec_sldwfunction
4157core::core_arch::powerpc::altivecvec_sllfunction
4158core::core_arch::powerpc::altivecvec_slofunction
4159core::core_arch::powerpc::altivecvec_slvfunction
4160core::core_arch::powerpc::altivecvec_splatfunction
4161core::core_arch::powerpc::altivecvec_splat_s16function
4162core::core_arch::powerpc::altivecvec_splat_s32function
4163core::core_arch::powerpc::altivecvec_splat_s8function
4164core::core_arch::powerpc::altivecvec_splat_u16function
4165core::core_arch::powerpc::altivecvec_splat_u32function
4166core::core_arch::powerpc::altivecvec_splat_u8function
4167core::core_arch::powerpc::altivecvec_splatsfunction
4168core::core_arch::powerpc::altivecvec_srfunction
4169core::core_arch::powerpc::altivecvec_srafunction
4170core::core_arch::powerpc::altivecvec_srlfunction
4171core::core_arch::powerpc::altivecvec_srofunction
4172core::core_arch::powerpc::altivecvec_srvfunction
4173core::core_arch::powerpc::altivecvec_stfunction
4174core::core_arch::powerpc::altivecvec_stefunction
4175core::core_arch::powerpc::altivecvec_stlfunction
4176core::core_arch::powerpc::altivecvec_subfunction
4177core::core_arch::powerpc::altivecvec_subcfunction
4178core::core_arch::powerpc::altivecvec_subsfunction
4179core::core_arch::powerpc::altivecvec_sum4sfunction
4180core::core_arch::powerpc::altivecvec_unpackhfunction
4181core::core_arch::powerpc::altivecvec_unpacklfunction
4182core::core_arch::powerpc::altivecvec_xlfunction
4183core::core_arch::powerpc::altivecvec_xorfunction
4184core::core_arch::powerpc::altivecvec_xstfunction
4185core::core_arch::powerpc::altivec::endianvec_mulefunction
4186core::core_arch::powerpc::altivec::endianvec_mulofunction
4187core::core_arch::powerpc::altivec::endianvec_permfunction
4188core::core_arch::powerpc::altivec::endianvec_sum2sfunction
4189core::core_arch::powerpc::altivec::sealed::VectorAbsvec_abstrait_method
4190core::core_arch::powerpc::altivec::sealed::VectorAbssvec_absstrait_method
4191core::core_arch::powerpc::altivec::sealed::VectorAddvec_addtrait_method
4192core::core_arch::powerpc::altivec::sealed::VectorAddevec_addetrait_method
4193core::core_arch::powerpc::altivec::sealed::VectorAddsvec_addstrait_method
4194core::core_arch::powerpc::altivec::sealed::VectorAllEqvec_all_eqtrait_method
4195core::core_arch::powerpc::altivec::sealed::VectorAllGevec_all_getrait_method
4196core::core_arch::powerpc::altivec::sealed::VectorAllGtvec_all_gttrait_method
4197core::core_arch::powerpc::altivec::sealed::VectorAllNevec_all_netrait_method
4198core::core_arch::powerpc::altivec::sealed::VectorAndvec_andtrait_method
4199core::core_arch::powerpc::altivec::sealed::VectorAndcvec_andctrait_method
4200core::core_arch::powerpc::altivec::sealed::VectorAnyEqvec_any_eqtrait_method
4201core::core_arch::powerpc::altivec::sealed::VectorAnyGevec_any_getrait_method
4202core::core_arch::powerpc::altivec::sealed::VectorAnyGtvec_any_gttrait_method
4203core::core_arch::powerpc::altivec::sealed::VectorAnyNevec_any_netrait_method
4204core::core_arch::powerpc::altivec::sealed::VectorAvgvec_avgtrait_method
4205core::core_arch::powerpc::altivec::sealed::VectorCmpEqvec_cmpeqtrait_method
4206core::core_arch::powerpc::altivec::sealed::VectorCmpGtvec_cmpgttrait_method
4207core::core_arch::powerpc::altivec::sealed::VectorCmpNevec_cmpnetrait_method
4208core::core_arch::powerpc::altivec::sealed::VectorCntlzvec_cntlztrait_method
4209core::core_arch::powerpc::altivec::sealed::VectorCtfvec_ctftrait_method
4210core::core_arch::powerpc::altivec::sealed::VectorExtractvec_extracttrait_method
4211core::core_arch::powerpc::altivec::sealed::VectorInsertvec_inserttrait_method
4212core::core_arch::powerpc::altivec::sealed::VectorLdvec_ldtrait_method
4213core::core_arch::powerpc::altivec::sealed::VectorLdvec_ldltrait_method
4214core::core_arch::powerpc::altivec::sealed::VectorLdevec_ldetrait_method
4215core::core_arch::powerpc::altivec::sealed::VectorMaxvec_maxtrait_method
4216core::core_arch::powerpc::altivec::sealed::VectorMergehvec_mergehtrait_method
4217core::core_arch::powerpc::altivec::sealed::VectorMergelvec_mergeltrait_method
4218core::core_arch::powerpc::altivec::sealed::VectorMinvec_mintrait_method
4219core::core_arch::powerpc::altivec::sealed::VectorMladdvec_mladdtrait_method
4220core::core_arch::powerpc::altivec::sealed::VectorMsumvec_msumtrait_method
4221core::core_arch::powerpc::altivec::sealed::VectorMsumsvec_msumstrait_method
4222core::core_arch::powerpc::altivec::sealed::VectorMulvec_multrait_method
4223core::core_arch::powerpc::altivec::sealed::VectorMulevec_muletrait_method
4224core::core_arch::powerpc::altivec::sealed::VectorMulovec_mulotrait_method
4225core::core_arch::powerpc::altivec::sealed::VectorNandvec_nandtrait_method
4226core::core_arch::powerpc::altivec::sealed::VectorNegvec_negtrait_method
4227core::core_arch::powerpc::altivec::sealed::VectorNorvec_nortrait_method
4228core::core_arch::powerpc::altivec::sealed::VectorOrvec_ortrait_method
4229core::core_arch::powerpc::altivec::sealed::VectorOrcvec_orctrait_method
4230core::core_arch::powerpc::altivec::sealed::VectorPackvec_packtrait_method
4231core::core_arch::powerpc::altivec::sealed::VectorPacksvec_packstrait_method
4232core::core_arch::powerpc::altivec::sealed::VectorPacksuvec_packsutrait_method
4233core::core_arch::powerpc::altivec::sealed::VectorPermvec_vpermtrait_method
4234core::core_arch::powerpc::altivec::sealed::VectorRlvec_rltrait_method
4235core::core_arch::powerpc::altivec::sealed::VectorRoundvec_roundtrait_method
4236core::core_arch::powerpc::altivec::sealed::VectorSelvec_seltrait_method
4237core::core_arch::powerpc::altivec::sealed::VectorSlvec_sltrait_method
4238core::core_arch::powerpc::altivec::sealed::VectorSldvec_sldtrait_method
4239core::core_arch::powerpc::altivec::sealed::VectorSldvec_sldwtrait_method
4240core::core_arch::powerpc::altivec::sealed::VectorSllvec_slltrait_method
4241core::core_arch::powerpc::altivec::sealed::VectorSlovec_slotrait_method
4242core::core_arch::powerpc::altivec::sealed::VectorSplatvec_splattrait_method
4243core::core_arch::powerpc::altivec::sealed::VectorSplatsvec_splatstrait_method
4244core::core_arch::powerpc::altivec::sealed::VectorSrvec_srtrait_method
4245core::core_arch::powerpc::altivec::sealed::VectorSravec_sratrait_method
4246core::core_arch::powerpc::altivec::sealed::VectorSrlvec_srltrait_method
4247core::core_arch::powerpc::altivec::sealed::VectorSrovec_srotrait_method
4248core::core_arch::powerpc::altivec::sealed::VectorStvec_sttrait_method
4249core::core_arch::powerpc::altivec::sealed::VectorStvec_stltrait_method
4250core::core_arch::powerpc::altivec::sealed::VectorStevec_stetrait_method
4251core::core_arch::powerpc::altivec::sealed::VectorSubvec_subtrait_method
4252core::core_arch::powerpc::altivec::sealed::VectorSubcvec_subctrait_method
4253core::core_arch::powerpc::altivec::sealed::VectorSubsvec_substrait_method
4254core::core_arch::powerpc::altivec::sealed::VectorSum4svec_sum4strait_method
4255core::core_arch::powerpc::altivec::sealed::VectorUnpackhvec_unpackhtrait_method
4256core::core_arch::powerpc::altivec::sealed::VectorUnpacklvec_unpackltrait_method
4257core::core_arch::powerpc::altivec::sealed::VectorXlvec_xltrait_method
4258core::core_arch::powerpc::altivec::sealed::VectorXorvec_xortrait_method
4259core::core_arch::powerpc::altivec::sealed::VectorXstvec_xsttrait_method
4260core::core_arch::powerpc::vsxvec_mergeefunction
4261core::core_arch::powerpc::vsxvec_mergeofunction
4262core::core_arch::powerpc::vsxvec_xxpermdifunction
4263core::core_arch::powerpc::vsx::sealed::VectorMergeEovec_mergeetrait_method
4264core::core_arch::powerpc::vsx::sealed::VectorMergeEovec_mergeotrait_method
4265core::core_arch::powerpc::vsx::sealed::VectorPermDIvec_xxpermditrait_method
4266core::core_arch::riscv64hlv_dfunction
4267core::core_arch::riscv64hlv_wufunction
4268core::core_arch::riscv64hsv_dfunction
4269core::core_arch::riscv_sharedfence_ifunction
4270core::core_arch::riscv_sharedhfence_gvmafunction
4271core::core_arch::riscv_sharedhfence_gvma_allfunction
4272core::core_arch::riscv_sharedhfence_gvma_gaddrfunction
4273core::core_arch::riscv_sharedhfence_gvma_vmidfunction
4274core::core_arch::riscv_sharedhfence_vvmafunction
4275core::core_arch::riscv_sharedhfence_vvma_allfunction
4276core::core_arch::riscv_sharedhfence_vvma_asidfunction
4277core::core_arch::riscv_sharedhfence_vvma_vaddrfunction
4278core::core_arch::riscv_sharedhinval_gvmafunction
4279core::core_arch::riscv_sharedhinval_gvma_allfunction
4280core::core_arch::riscv_sharedhinval_gvma_gaddrfunction
4281core::core_arch::riscv_sharedhinval_gvma_vmidfunction
4282core::core_arch::riscv_sharedhinval_vvmafunction
4283core::core_arch::riscv_sharedhinval_vvma_allfunction
4284core::core_arch::riscv_sharedhinval_vvma_asidfunction
4285core::core_arch::riscv_sharedhinval_vvma_vaddrfunction
4286core::core_arch::riscv_sharedhlv_bfunction
4287core::core_arch::riscv_sharedhlv_bufunction
4288core::core_arch::riscv_sharedhlv_hfunction
4289core::core_arch::riscv_sharedhlv_hufunction
4290core::core_arch::riscv_sharedhlv_wfunction
4291core::core_arch::riscv_sharedhlvx_hufunction
4292core::core_arch::riscv_sharedhlvx_wufunction
4293core::core_arch::riscv_sharedhsv_bfunction
4294core::core_arch::riscv_sharedhsv_hfunction
4295core::core_arch::riscv_sharedhsv_wfunction
4296core::core_arch::riscv_sharedsfence_inval_irfunction
4297core::core_arch::riscv_sharedsfence_vmafunction
4298core::core_arch::riscv_sharedsfence_vma_allfunction
4299core::core_arch::riscv_sharedsfence_vma_asidfunction
4300core::core_arch::riscv_sharedsfence_vma_vaddrfunction
4301core::core_arch::riscv_sharedsfence_w_invalfunction
4302core::core_arch::riscv_sharedsinval_vmafunction
4303core::core_arch::riscv_sharedsinval_vma_allfunction
4304core::core_arch::riscv_sharedsinval_vma_asidfunction
4305core::core_arch::riscv_sharedsinval_vma_vaddrfunction
4306core::core_arch::riscv_sharedwfifunction
4307core::core_arch::s390x::vectorvec_absfunction
4308core::core_arch::s390x::vectorvec_addfunction
4309core::core_arch::s390x::vectorvec_add_u128function
4310core::core_arch::s390x::vectorvec_addc_u128function
4311core::core_arch::s390x::vectorvec_adde_u128function
4312core::core_arch::s390x::vectorvec_addec_u128function
4313core::core_arch::s390x::vectorvec_all_eqfunction
4314core::core_arch::s390x::vectorvec_all_gefunction
4315core::core_arch::s390x::vectorvec_all_gtfunction
4316core::core_arch::s390x::vectorvec_all_lefunction
4317core::core_arch::s390x::vectorvec_all_ltfunction
4318core::core_arch::s390x::vectorvec_all_nanfunction
4319core::core_arch::s390x::vectorvec_all_nefunction
4320core::core_arch::s390x::vectorvec_all_ngefunction
4321core::core_arch::s390x::vectorvec_all_ngtfunction
4322core::core_arch::s390x::vectorvec_all_nlefunction
4323core::core_arch::s390x::vectorvec_all_nltfunction
4324core::core_arch::s390x::vectorvec_all_numericfunction
4325core::core_arch::s390x::vectorvec_andfunction
4326core::core_arch::s390x::vectorvec_andcfunction
4327core::core_arch::s390x::vectorvec_any_eqfunction
4328core::core_arch::s390x::vectorvec_any_gefunction
4329core::core_arch::s390x::vectorvec_any_gtfunction
4330core::core_arch::s390x::vectorvec_any_lefunction
4331core::core_arch::s390x::vectorvec_any_ltfunction
4332core::core_arch::s390x::vectorvec_any_nanfunction
4333core::core_arch::s390x::vectorvec_any_nefunction
4334core::core_arch::s390x::vectorvec_any_ngefunction
4335core::core_arch::s390x::vectorvec_any_ngtfunction
4336core::core_arch::s390x::vectorvec_any_nlefunction
4337core::core_arch::s390x::vectorvec_any_nltfunction
4338core::core_arch::s390x::vectorvec_any_numericfunction
4339core::core_arch::s390x::vectorvec_avgfunction
4340core::core_arch::s390x::vectorvec_bperm_u128function
4341core::core_arch::s390x::vectorvec_ceilfunction
4342core::core_arch::s390x::vectorvec_checksumfunction
4343core::core_arch::s390x::vectorvec_cmpeqfunction
4344core::core_arch::s390x::vectorvec_cmpeq_idxfunction
4345core::core_arch::s390x::vectorvec_cmpeq_idx_ccfunction
4346core::core_arch::s390x::vectorvec_cmpeq_or_0_idxfunction
4347core::core_arch::s390x::vectorvec_cmpeq_or_0_idx_ccfunction
4348core::core_arch::s390x::vectorvec_cmpgefunction
4349core::core_arch::s390x::vectorvec_cmpgtfunction
4350core::core_arch::s390x::vectorvec_cmplefunction
4351core::core_arch::s390x::vectorvec_cmpltfunction
4352core::core_arch::s390x::vectorvec_cmpnefunction
4353core::core_arch::s390x::vectorvec_cmpne_idxfunction
4354core::core_arch::s390x::vectorvec_cmpne_idx_ccfunction
4355core::core_arch::s390x::vectorvec_cmpne_or_0_idxfunction
4356core::core_arch::s390x::vectorvec_cmpne_or_0_idx_ccfunction
4357core::core_arch::s390x::vectorvec_cmpnrgfunction
4358core::core_arch::s390x::vectorvec_cmpnrg_ccfunction
4359core::core_arch::s390x::vectorvec_cmpnrg_idxfunction
4360core::core_arch::s390x::vectorvec_cmpnrg_idx_ccfunction
4361core::core_arch::s390x::vectorvec_cmpnrg_or_0_idxfunction
4362core::core_arch::s390x::vectorvec_cmpnrg_or_0_idx_ccfunction
4363core::core_arch::s390x::vectorvec_cmprgfunction
4364core::core_arch::s390x::vectorvec_cmprg_ccfunction
4365core::core_arch::s390x::vectorvec_cmprg_idxfunction
4366core::core_arch::s390x::vectorvec_cmprg_idx_ccfunction
4367core::core_arch::s390x::vectorvec_cmprg_or_0_idxfunction
4368core::core_arch::s390x::vectorvec_cmprg_or_0_idx_ccfunction
4369core::core_arch::s390x::vectorvec_cntlzfunction
4370core::core_arch::s390x::vectorvec_cnttzfunction
4371core::core_arch::s390x::vectorvec_convert_from_fp16function
4372core::core_arch::s390x::vectorvec_convert_to_fp16function
4373core::core_arch::s390x::vectorvec_cp_until_zerofunction
4374core::core_arch::s390x::vectorvec_cp_until_zero_ccfunction
4375core::core_arch::s390x::vectorvec_doublefunction
4376core::core_arch::s390x::vectorvec_doubleefunction
4377core::core_arch::s390x::vectorvec_eqvfunction
4378core::core_arch::s390x::vectorvec_extend_s64function
4379core::core_arch::s390x::vectorvec_extend_to_fp32_hifunction
4380core::core_arch::s390x::vectorvec_extend_to_fp32_lofunction
4381core::core_arch::s390x::vectorvec_extractfunction
4382core::core_arch::s390x::vectorvec_find_any_eqfunction
4383core::core_arch::s390x::vectorvec_find_any_eq_ccfunction
4384core::core_arch::s390x::vectorvec_find_any_eq_idxfunction
4385core::core_arch::s390x::vectorvec_find_any_eq_idx_ccfunction
4386core::core_arch::s390x::vectorvec_find_any_eq_or_0_idxfunction
4387core::core_arch::s390x::vectorvec_find_any_eq_or_0_idx_ccfunction
4388core::core_arch::s390x::vectorvec_find_any_nefunction
4389core::core_arch::s390x::vectorvec_find_any_ne_ccfunction
4390core::core_arch::s390x::vectorvec_find_any_ne_idxfunction
4391core::core_arch::s390x::vectorvec_find_any_ne_idx_ccfunction
4392core::core_arch::s390x::vectorvec_find_any_ne_or_0_idxfunction
4393core::core_arch::s390x::vectorvec_find_any_ne_or_0_idx_ccfunction
4394core::core_arch::s390x::vectorvec_floatfunction
4395core::core_arch::s390x::vectorvec_floatefunction
4396core::core_arch::s390x::vectorvec_floorfunction
4397core::core_arch::s390x::vectorvec_fp_test_data_classfunction
4398core::core_arch::s390x::vectorvec_gather_elementfunction
4399core::core_arch::s390x::vectorvec_genmaskfunction
4400core::core_arch::s390x::vectorvec_genmasks_16function
4401core::core_arch::s390x::vectorvec_genmasks_32function
4402core::core_arch::s390x::vectorvec_genmasks_64function
4403core::core_arch::s390x::vectorvec_genmasks_8function
4404core::core_arch::s390x::vectorvec_gfmsumfunction
4405core::core_arch::s390x::vectorvec_gfmsum_128function
4406core::core_arch::s390x::vectorvec_gfmsum_accumfunction
4407core::core_arch::s390x::vectorvec_gfmsum_accum_128function
4408core::core_arch::s390x::vectorvec_insertfunction
4409core::core_arch::s390x::vectorvec_insert_and_zerofunction
4410core::core_arch::s390x::vectorvec_load_bndryfunction
4411core::core_arch::s390x::vectorvec_load_lenfunction
4412core::core_arch::s390x::vectorvec_load_len_rfunction
4413core::core_arch::s390x::vectorvec_load_pairfunction
4414core::core_arch::s390x::vectorvec_maddfunction
4415core::core_arch::s390x::vectorvec_maxfunction
4416core::core_arch::s390x::vectorvec_meaddfunction
4417core::core_arch::s390x::vectorvec_mergehfunction
4418core::core_arch::s390x::vectorvec_mergelfunction
4419core::core_arch::s390x::vectorvec_mhaddfunction
4420core::core_arch::s390x::vectorvec_minfunction
4421core::core_arch::s390x::vectorvec_mladdfunction
4422core::core_arch::s390x::vectorvec_moaddfunction
4423core::core_arch::s390x::vectorvec_msubfunction
4424core::core_arch::s390x::vectorvec_msum_u128function
4425core::core_arch::s390x::vectorvec_mulfunction
4426core::core_arch::s390x::vectorvec_mulefunction
4427core::core_arch::s390x::vectorvec_mulhfunction
4428core::core_arch::s390x::vectorvec_mulofunction
4429core::core_arch::s390x::vectorvec_nabsfunction
4430core::core_arch::s390x::vectorvec_nandfunction
4431core::core_arch::s390x::vectorvec_negfunction
4432core::core_arch::s390x::vectorvec_nmaddfunction
4433core::core_arch::s390x::vectorvec_nmsubfunction
4434core::core_arch::s390x::vectorvec_norfunction
4435core::core_arch::s390x::vectorvec_orfunction
4436core::core_arch::s390x::vectorvec_orcfunction
4437core::core_arch::s390x::vectorvec_packfunction
4438core::core_arch::s390x::vectorvec_packsfunction
4439core::core_arch::s390x::vectorvec_packs_ccfunction
4440core::core_arch::s390x::vectorvec_packsufunction
4441core::core_arch::s390x::vectorvec_packsu_ccfunction
4442core::core_arch::s390x::vectorvec_permfunction
4443core::core_arch::s390x::vectorvec_popcntfunction
4444core::core_arch::s390x::vectorvec_promotefunction
4445core::core_arch::s390x::vectorvec_revbfunction
4446core::core_arch::s390x::vectorvec_revefunction
4447core::core_arch::s390x::vectorvec_rintfunction
4448core::core_arch::s390x::vectorvec_rlfunction
4449core::core_arch::s390x::vectorvec_rlifunction
4450core::core_arch::s390x::vectorvec_roundfunction
4451core::core_arch::s390x::vectorvec_round_from_fp32function
4452core::core_arch::s390x::vectorvec_roundcfunction
4453core::core_arch::s390x::vectorvec_roundmfunction
4454core::core_arch::s390x::vectorvec_roundpfunction
4455core::core_arch::s390x::vectorvec_roundzfunction
4456core::core_arch::s390x::vectorvec_search_string_ccfunction
4457core::core_arch::s390x::vectorvec_search_string_until_zero_ccfunction
4458core::core_arch::s390x::vectorvec_selfunction
4459core::core_arch::s390x::vectorvec_signedfunction
4460core::core_arch::s390x::vectorvec_slfunction
4461core::core_arch::s390x::vectorvec_slbfunction
4462core::core_arch::s390x::vectorvec_sldfunction
4463core::core_arch::s390x::vectorvec_sldbfunction
4464core::core_arch::s390x::vectorvec_sldwfunction
4465core::core_arch::s390x::vectorvec_sllfunction
4466core::core_arch::s390x::vectorvec_splatfunction
4467core::core_arch::s390x::vectorvec_splat_s16function
4468core::core_arch::s390x::vectorvec_splat_s32function
4469core::core_arch::s390x::vectorvec_splat_s64function
4470core::core_arch::s390x::vectorvec_splat_s8function
4471core::core_arch::s390x::vectorvec_splat_u16function
4472core::core_arch::s390x::vectorvec_splat_u32function
4473core::core_arch::s390x::vectorvec_splat_u64function
4474core::core_arch::s390x::vectorvec_splat_u8function
4475core::core_arch::s390x::vectorvec_splatsfunction
4476core::core_arch::s390x::vectorvec_sqrtfunction
4477core::core_arch::s390x::vectorvec_srfunction
4478core::core_arch::s390x::vectorvec_srafunction
4479core::core_arch::s390x::vectorvec_srabfunction
4480core::core_arch::s390x::vectorvec_sralfunction
4481core::core_arch::s390x::vectorvec_srbfunction
4482core::core_arch::s390x::vectorvec_srdbfunction
4483core::core_arch::s390x::vectorvec_srlfunction
4484core::core_arch::s390x::vectorvec_store_lenfunction
4485core::core_arch::s390x::vectorvec_store_len_rfunction
4486core::core_arch::s390x::vectorvec_subfunction
4487core::core_arch::s390x::vectorvec_sub_u128function
4488core::core_arch::s390x::vectorvec_subcfunction
4489core::core_arch::s390x::vectorvec_subc_u128function
4490core::core_arch::s390x::vectorvec_sube_u128function
4491core::core_arch::s390x::vectorvec_subec_u128function
4492core::core_arch::s390x::vectorvec_sum2function
4493core::core_arch::s390x::vectorvec_sum4function
4494core::core_arch::s390x::vectorvec_sum_u128function
4495core::core_arch::s390x::vectorvec_test_maskfunction
4496core::core_arch::s390x::vectorvec_truncfunction
4497core::core_arch::s390x::vectorvec_unpackhfunction
4498core::core_arch::s390x::vectorvec_unpacklfunction
4499core::core_arch::s390x::vectorvec_unsignedfunction
4500core::core_arch::s390x::vectorvec_xlfunction
4501core::core_arch::s390x::vectorvec_xorfunction
4502core::core_arch::s390x::vectorvec_xstfunction
4503core::core_arch::s390x::vector::sealed::CountBitsvec_cntlztrait_method
4504core::core_arch::s390x::vector::sealed::CountBitsvec_cnttztrait_method
4505core::core_arch::s390x::vector::sealed::CountBitsvec_popcnttrait_method
4506core::core_arch::s390x::vector::sealed::VectorAbsvec_abstrait_method
4507core::core_arch::s390x::vector::sealed::VectorAddvec_addtrait_method
4508core::core_arch::s390x::vector::sealed::VectorAndvec_andtrait_method
4509core::core_arch::s390x::vector::sealed::VectorAndcvec_andctrait_method
4510core::core_arch::s390x::vector::sealed::VectorAvgvec_avgtrait_method
4511core::core_arch::s390x::vector::sealed::VectorCeilvec_ceiltrait_method
4512core::core_arch::s390x::vector::sealed::VectorComparevec_all_getrait_method
4513core::core_arch::s390x::vector::sealed::VectorComparevec_all_gttrait_method
4514core::core_arch::s390x::vector::sealed::VectorComparevec_all_letrait_method
4515core::core_arch::s390x::vector::sealed::VectorComparevec_all_lttrait_method
4516core::core_arch::s390x::vector::sealed::VectorComparePredicatevec_cmpgetrait_method
4517core::core_arch::s390x::vector::sealed::VectorComparePredicatevec_cmpgttrait_method
4518core::core_arch::s390x::vector::sealed::VectorComparePredicatevec_cmpletrait_method
4519core::core_arch::s390x::vector::sealed::VectorComparePredicatevec_cmplttrait_method
4520core::core_arch::s390x::vector::sealed::VectorCompareRangevstrctrait_method
4521core::core_arch::s390x::vector::sealed::VectorCompareRangevstrcstrait_method
4522core::core_arch::s390x::vector::sealed::VectorCompareRangevstrcztrait_method
4523core::core_arch::s390x::vector::sealed::VectorCompareRangevstrczstrait_method
4524core::core_arch::s390x::vector::sealed::VectorCopyUntilZerovec_cp_until_zerotrait_method
4525core::core_arch::s390x::vector::sealed::VectorCopyUntilZeroCCvec_cp_until_zero_cctrait_method
4526core::core_arch::s390x::vector::sealed::VectorDoublevec_doubletrait_method
4527core::core_arch::s390x::vector::sealed::VectorEqualityvec_cmpeqtrait_method
4528core::core_arch::s390x::vector::sealed::VectorEqualityvec_cmpnetrait_method
4529core::core_arch::s390x::vector::sealed::VectorEqualityIdxvec_cmpeq_idxtrait_method
4530core::core_arch::s390x::vector::sealed::VectorEqualityIdxvec_cmpeq_idx_cctrait_method
4531core::core_arch::s390x::vector::sealed::VectorEqualityIdxvec_cmpeq_or_0_idxtrait_method
4532core::core_arch::s390x::vector::sealed::VectorEqualityIdxvec_cmpeq_or_0_idx_cctrait_method
4533core::core_arch::s390x::vector::sealed::VectorEqualityIdxvec_cmpne_idxtrait_method
4534core::core_arch::s390x::vector::sealed::VectorEqualityIdxvec_cmpne_idx_cctrait_method
4535core::core_arch::s390x::vector::sealed::VectorEqualityIdxvec_cmpne_or_0_idxtrait_method
4536core::core_arch::s390x::vector::sealed::VectorEqualityIdxvec_cmpne_or_0_idx_cctrait_method
4537core::core_arch::s390x::vector::sealed::VectorEqvvec_eqvtrait_method
4538core::core_arch::s390x::vector::sealed::VectorExtendSigned64vec_extend_s64trait_method
4539core::core_arch::s390x::vector::sealed::VectorExtractvec_extracttrait_method
4540core::core_arch::s390x::vector::sealed::VectorFindAnyEqvec_find_any_eqtrait_method
4541core::core_arch::s390x::vector::sealed::VectorFindAnyEqCCvec_find_any_eq_cctrait_method
4542core::core_arch::s390x::vector::sealed::VectorFindAnyEqIdxvec_find_any_eq_idxtrait_method
4543core::core_arch::s390x::vector::sealed::VectorFindAnyEqIdxCCvec_find_any_eq_idx_cctrait_method
4544core::core_arch::s390x::vector::sealed::VectorFindAnyEqOrZeroIdxvec_find_any_eq_or_0_idxtrait_method
4545core::core_arch::s390x::vector::sealed::VectorFindAnyEqOrZeroIdxCCvec_find_any_eq_or_0_idx_cctrait_method
4546core::core_arch::s390x::vector::sealed::VectorFindAnyNevec_find_any_netrait_method
4547core::core_arch::s390x::vector::sealed::VectorFindAnyNeCCvec_find_any_ne_cctrait_method
4548core::core_arch::s390x::vector::sealed::VectorFindAnyNeIdxvec_find_any_ne_idxtrait_method
4549core::core_arch::s390x::vector::sealed::VectorFindAnyNeIdxCCvec_find_any_ne_idx_cctrait_method
4550core::core_arch::s390x::vector::sealed::VectorFindAnyNeOrZeroIdxvec_find_any_ne_or_0_idxtrait_method
4551core::core_arch::s390x::vector::sealed::VectorFindAnyNeOrZeroIdxCCvec_find_any_ne_or_0_idx_cctrait_method
4552core::core_arch::s390x::vector::sealed::VectorFloatvec_floattrait_method
4553core::core_arch::s390x::vector::sealed::VectorFloorvec_floortrait_method
4554core::core_arch::s390x::vector::sealed::VectorFpTestDataClassvec_fp_test_data_classtrait_method
4555core::core_arch::s390x::vector::sealed::VectorGatherElementvec_gather_elementtrait_method
4556core::core_arch::s390x::vector::sealed::VectorGfmsumvec_gfmsumtrait_method
4557core::core_arch::s390x::vector::sealed::VectorGfmsumAccumvec_gfmsum_accumtrait_method
4558core::core_arch::s390x::vector::sealed::VectorInsertvec_inserttrait_method
4559core::core_arch::s390x::vector::sealed::VectorInsertAndZerovec_insert_and_zerotrait_method
4560core::core_arch::s390x::vector::sealed::VectorLoadvec_load_bndrytrait_method
4561core::core_arch::s390x::vector::sealed::VectorLoadvec_load_lentrait_method
4562core::core_arch::s390x::vector::sealed::VectorLoadvec_xltrait_method
4563core::core_arch::s390x::vector::sealed::VectorLoadPairvec_load_pairtrait_method
4564core::core_arch::s390x::vector::sealed::VectorMaddvec_maddtrait_method
4565core::core_arch::s390x::vector::sealed::VectorMaddvec_msubtrait_method
4566core::core_arch::s390x::vector::sealed::VectorMaxvec_maxtrait_method
4567core::core_arch::s390x::vector::sealed::VectorMeaddvec_meaddtrait_method
4568core::core_arch::s390x::vector::sealed::VectorMergehvec_mergehtrait_method
4569core::core_arch::s390x::vector::sealed::VectorMergelvec_mergeltrait_method
4570core::core_arch::s390x::vector::sealed::VectorMhaddvec_mhaddtrait_method
4571core::core_arch::s390x::vector::sealed::VectorMinvec_mintrait_method
4572core::core_arch::s390x::vector::sealed::VectorMladdvec_mladdtrait_method
4573core::core_arch::s390x::vector::sealed::VectorMoaddvec_moaddtrait_method
4574core::core_arch::s390x::vector::sealed::VectorMulvec_multrait_method
4575core::core_arch::s390x::vector::sealed::VectorMulevec_muletrait_method
4576core::core_arch::s390x::vector::sealed::VectorMulhvec_mulhtrait_method
4577core::core_arch::s390x::vector::sealed::VectorMulovec_mulotrait_method
4578core::core_arch::s390x::vector::sealed::VectorNabsvec_nabstrait_method
4579core::core_arch::s390x::vector::sealed::VectorNandvec_nandtrait_method
4580core::core_arch::s390x::vector::sealed::VectorNegvec_negtrait_method
4581core::core_arch::s390x::vector::sealed::VectorNmaddvec_nmaddtrait_method
4582core::core_arch::s390x::vector::sealed::VectorNmsubvec_nmsubtrait_method
4583core::core_arch::s390x::vector::sealed::VectorNorvec_nortrait_method
4584core::core_arch::s390x::vector::sealed::VectorOrvec_ortrait_method
4585core::core_arch::s390x::vector::sealed::VectorOrcvec_orctrait_method
4586core::core_arch::s390x::vector::sealed::VectorPackvec_packtrait_method
4587core::core_arch::s390x::vector::sealed::VectorPacksvec_packstrait_method
4588core::core_arch::s390x::vector::sealed::VectorPacksCCvec_packs_cctrait_method
4589core::core_arch::s390x::vector::sealed::VectorPacksuvec_packsutrait_method
4590core::core_arch::s390x::vector::sealed::VectorPacksuCCvec_packsu_cctrait_method
4591core::core_arch::s390x::vector::sealed::VectorPermvec_permtrait_method
4592core::core_arch::s390x::vector::sealed::VectorPromotevec_promotetrait_method
4593core::core_arch::s390x::vector::sealed::VectorRevbvec_revbtrait_method
4594core::core_arch::s390x::vector::sealed::VectorRevevec_revetrait_method
4595core::core_arch::s390x::vector::sealed::VectorRintvec_rinttrait_method
4596core::core_arch::s390x::vector::sealed::VectorRlvec_rltrait_method
4597core::core_arch::s390x::vector::sealed::VectorRlivec_rlitrait_method
4598core::core_arch::s390x::vector::sealed::VectorRoundvec_roundtrait_method
4599core::core_arch::s390x::vector::sealed::VectorRoundcvec_roundctrait_method
4600core::core_arch::s390x::vector::sealed::VectorSearchStringvec_search_string_cctrait_method
4601core::core_arch::s390x::vector::sealed::VectorSearchStringvec_search_string_until_zero_cctrait_method
4602core::core_arch::s390x::vector::sealed::VectorSelvec_seltrait_method
4603core::core_arch::s390x::vector::sealed::VectorSignedvec_signedtrait_method
4604core::core_arch::s390x::vector::sealed::VectorSlvec_sltrait_method
4605core::core_arch::s390x::vector::sealed::VectorSlbvec_slbtrait_method
4606core::core_arch::s390x::vector::sealed::VectorSldvec_sldtrait_method
4607core::core_arch::s390x::vector::sealed::VectorSldvec_sldbtrait_method
4608core::core_arch::s390x::vector::sealed::VectorSldvec_sldwtrait_method
4609core::core_arch::s390x::vector::sealed::VectorSllvec_slltrait_method
4610core::core_arch::s390x::vector::sealed::VectorSplatvec_splattrait_method
4611core::core_arch::s390x::vector::sealed::VectorSplatsvec_splatstrait_method
4612core::core_arch::s390x::vector::sealed::VectorSqrtvec_sqrttrait_method
4613core::core_arch::s390x::vector::sealed::VectorSrvec_srtrait_method
4614core::core_arch::s390x::vector::sealed::VectorSravec_sratrait_method
4615core::core_arch::s390x::vector::sealed::VectorSrabvec_srabtrait_method
4616core::core_arch::s390x::vector::sealed::VectorSralvec_sraltrait_method
4617core::core_arch::s390x::vector::sealed::VectorSrbvec_srbtrait_method
4618core::core_arch::s390x::vector::sealed::VectorSrdbvec_srdbtrait_method
4619core::core_arch::s390x::vector::sealed::VectorSrlvec_srltrait_method
4620core::core_arch::s390x::vector::sealed::VectorStorevec_store_lentrait_method
4621core::core_arch::s390x::vector::sealed::VectorStorevec_xsttrait_method
4622core::core_arch::s390x::vector::sealed::VectorSubvec_subtrait_method
4623core::core_arch::s390x::vector::sealed::VectorSubcvec_subctrait_method
4624core::core_arch::s390x::vector::sealed::VectorSum2vec_sum2trait_method
4625core::core_arch::s390x::vector::sealed::VectorSum4vec_sum4trait_method
4626core::core_arch::s390x::vector::sealed::VectorSumU128vec_sum_u128trait_method
4627core::core_arch::s390x::vector::sealed::VectorTestMaskvec_test_masktrait_method
4628core::core_arch::s390x::vector::sealed::VectorTruncvec_trunctrait_method
4629core::core_arch::s390x::vector::sealed::VectorUnpackhvec_unpackhtrait_method
4630core::core_arch::s390x::vector::sealed::VectorUnpacklvec_unpackltrait_method
4631core::core_arch::s390x::vector::sealed::VectorUnsignedvec_unsignedtrait_method
4632core::core_arch::s390x::vector::sealed::VectorXorvec_xortrait_method
4633core::core_arch::wasm32::atomicmemory_atomic_notifyfunction
4634core::core_arch::wasm32::atomicmemory_atomic_wait32function
4635core::core_arch::wasm32::atomicmemory_atomic_wait64function
4636core::core_arch::wasm32::simd128i16x8_load_extend_i8x8function
4637core::core_arch::wasm32::simd128i16x8_load_extend_u8x8function
4638core::core_arch::wasm32::simd128i32x4_load_extend_i16x4function
4639core::core_arch::wasm32::simd128i32x4_load_extend_u16x4function
4640core::core_arch::wasm32::simd128i64x2_load_extend_i32x2function
4641core::core_arch::wasm32::simd128i64x2_load_extend_u32x2function
4642core::core_arch::wasm32::simd128v128_loadfunction
4643core::core_arch::wasm32::simd128v128_load16_lanefunction
4644core::core_arch::wasm32::simd128v128_load16_splatfunction
4645core::core_arch::wasm32::simd128v128_load32_lanefunction
4646core::core_arch::wasm32::simd128v128_load32_splatfunction
4647core::core_arch::wasm32::simd128v128_load32_zerofunction
4648core::core_arch::wasm32::simd128v128_load64_lanefunction
4649core::core_arch::wasm32::simd128v128_load64_splatfunction
4650core::core_arch::wasm32::simd128v128_load64_zerofunction
4651core::core_arch::wasm32::simd128v128_load8_lanefunction
4652core::core_arch::wasm32::simd128v128_load8_splatfunction
4653core::core_arch::wasm32::simd128v128_storefunction
4654core::core_arch::wasm32::simd128v128_store16_lanefunction
4655core::core_arch::wasm32::simd128v128_store32_lanefunction
4656core::core_arch::wasm32::simd128v128_store64_lanefunction
4657core::core_arch::wasm32::simd128v128_store8_lanefunction
4658core::core_arch::x86::avx_mm256_lddqu_si256function
4659core::core_arch::x86::avx_mm256_load_pdfunction
4660core::core_arch::x86::avx_mm256_load_psfunction
4661core::core_arch::x86::avx_mm256_load_si256function
4662core::core_arch::x86::avx_mm256_loadu2_m128function
4663core::core_arch::x86::avx_mm256_loadu2_m128dfunction
4664core::core_arch::x86::avx_mm256_loadu2_m128ifunction
4665core::core_arch::x86::avx_mm256_loadu_pdfunction
4666core::core_arch::x86::avx_mm256_loadu_psfunction
4667core::core_arch::x86::avx_mm256_loadu_si256function
4668core::core_arch::x86::avx_mm256_maskload_pdfunction
4669core::core_arch::x86::avx_mm256_maskload_psfunction
4670core::core_arch::x86::avx_mm256_maskstore_pdfunction
4671core::core_arch::x86::avx_mm256_maskstore_psfunction
4672core::core_arch::x86::avx_mm256_store_pdfunction
4673core::core_arch::x86::avx_mm256_store_psfunction
4674core::core_arch::x86::avx_mm256_store_si256function
4675core::core_arch::x86::avx_mm256_storeu2_m128function
4676core::core_arch::x86::avx_mm256_storeu2_m128dfunction
4677core::core_arch::x86::avx_mm256_storeu2_m128ifunction
4678core::core_arch::x86::avx_mm256_storeu_pdfunction
4679core::core_arch::x86::avx_mm256_storeu_psfunction
4680core::core_arch::x86::avx_mm256_storeu_si256function
4681core::core_arch::x86::avx_mm256_stream_pdfunction

After using this intrinsic, but before any other access to the memory that this intrinsic mutates, a call to _mm_sfence must be performed by the thread that used the intrinsic. In particular, functions that call this intrinsic should generally call _mm_sfence before they return.

See _mm_sfence for details.

PostToFunc
4682core::core_arch::x86::avx_mm256_stream_psfunction

After using this intrinsic, but before any other access to the memory that this intrinsic mutates, a call to _mm_sfence must be performed by the thread that used the intrinsic. In particular, functions that call this intrinsic should generally call _mm_sfence before they return.

See _mm_sfence for details.

PostToFunc
4683core::core_arch::x86::avx_mm256_stream_si256function

After using this intrinsic, but before any other access to the memory that this intrinsic mutates, a call to _mm_sfence must be performed by the thread that used the intrinsic. In particular, functions that call this intrinsic should generally call _mm_sfence before they return.

See _mm_sfence for details.

PostToFunc
4684core::core_arch::x86::avx_mm_maskload_pdfunction
4685core::core_arch::x86::avx_mm_maskload_psfunction
4686core::core_arch::x86::avx_mm_maskstore_pdfunction
4687core::core_arch::x86::avx_mm_maskstore_psfunction
4688core::core_arch::x86::avx2_mm256_i32gather_epi32function
4689core::core_arch::x86::avx2_mm256_i32gather_epi64function
4690core::core_arch::x86::avx2_mm256_i32gather_pdfunction
4691core::core_arch::x86::avx2_mm256_i32gather_psfunction
4692core::core_arch::x86::avx2_mm256_i64gather_epi32function
4693core::core_arch::x86::avx2_mm256_i64gather_epi64function
4694core::core_arch::x86::avx2_mm256_i64gather_pdfunction
4695core::core_arch::x86::avx2_mm256_i64gather_psfunction
4696core::core_arch::x86::avx2_mm256_mask_i32gather_epi32function
4697core::core_arch::x86::avx2_mm256_mask_i32gather_epi64function
4698core::core_arch::x86::avx2_mm256_mask_i32gather_pdfunction
4699core::core_arch::x86::avx2_mm256_mask_i32gather_psfunction
4700core::core_arch::x86::avx2_mm256_mask_i64gather_epi32function
4701core::core_arch::x86::avx2_mm256_mask_i64gather_epi64function
4702core::core_arch::x86::avx2_mm256_mask_i64gather_pdfunction
4703core::core_arch::x86::avx2_mm256_mask_i64gather_psfunction
4704core::core_arch::x86::avx2_mm256_maskload_epi32function
4705core::core_arch::x86::avx2_mm256_maskload_epi64function
4706core::core_arch::x86::avx2_mm256_maskstore_epi32function
4707core::core_arch::x86::avx2_mm256_maskstore_epi64function
4708core::core_arch::x86::avx2_mm256_stream_load_si256function
4709core::core_arch::x86::avx2_mm_i32gather_epi32function
4710core::core_arch::x86::avx2_mm_i32gather_epi64function
4711core::core_arch::x86::avx2_mm_i32gather_pdfunction
4712core::core_arch::x86::avx2_mm_i32gather_psfunction
4713core::core_arch::x86::avx2_mm_i64gather_epi32function
4714core::core_arch::x86::avx2_mm_i64gather_epi64function
4715core::core_arch::x86::avx2_mm_i64gather_pdfunction
4716core::core_arch::x86::avx2_mm_i64gather_psfunction
4717core::core_arch::x86::avx2_mm_mask_i32gather_epi32function
4718core::core_arch::x86::avx2_mm_mask_i32gather_epi64function
4719core::core_arch::x86::avx2_mm_mask_i32gather_pdfunction
4720core::core_arch::x86::avx2_mm_mask_i32gather_psfunction
4721core::core_arch::x86::avx2_mm_mask_i64gather_epi32function
4722core::core_arch::x86::avx2_mm_mask_i64gather_epi64function
4723core::core_arch::x86::avx2_mm_mask_i64gather_pdfunction
4724core::core_arch::x86::avx2_mm_mask_i64gather_psfunction
4725core::core_arch::x86::avx2_mm_maskload_epi32function
4726core::core_arch::x86::avx2_mm_maskload_epi64function
4727core::core_arch::x86::avx2_mm_maskstore_epi32function
4728core::core_arch::x86::avx2_mm_maskstore_epi64function
4729core::core_arch::x86::avx512bw_kortest_mask32_u8function
4730core::core_arch::x86::avx512bw_kortest_mask64_u8function
4731core::core_arch::x86::avx512bw_ktest_mask32_u8function
4732core::core_arch::x86::avx512bw_ktest_mask64_u8function
4733core::core_arch::x86::avx512bw_load_mask32function
4734core::core_arch::x86::avx512bw_load_mask64function
4735core::core_arch::x86::avx512bw_mm256_loadu_epi16function
4736core::core_arch::x86::avx512bw_mm256_loadu_epi8function
4737core::core_arch::x86::avx512bw_mm256_mask_cvtepi16_storeu_epi8function
4738core::core_arch::x86::avx512bw_mm256_mask_cvtsepi16_storeu_epi8function
4739core::core_arch::x86::avx512bw_mm256_mask_cvtusepi16_storeu_epi8function
4740core::core_arch::x86::avx512bw_mm256_mask_loadu_epi16function
4741core::core_arch::x86::avx512bw_mm256_mask_loadu_epi8function
4742core::core_arch::x86::avx512bw_mm256_mask_storeu_epi16function
4743core::core_arch::x86::avx512bw_mm256_mask_storeu_epi8function
4744core::core_arch::x86::avx512bw_mm256_maskz_loadu_epi16function
4745core::core_arch::x86::avx512bw_mm256_maskz_loadu_epi8function
4746core::core_arch::x86::avx512bw_mm256_storeu_epi16function
4747core::core_arch::x86::avx512bw_mm256_storeu_epi8function
4748core::core_arch::x86::avx512bw_mm512_loadu_epi16function
4749core::core_arch::x86::avx512bw_mm512_loadu_epi8function
4750core::core_arch::x86::avx512bw_mm512_mask_cvtepi16_storeu_epi8function
4751core::core_arch::x86::avx512bw_mm512_mask_cvtsepi16_storeu_epi8function
4752core::core_arch::x86::avx512bw_mm512_mask_cvtusepi16_storeu_epi8function
4753core::core_arch::x86::avx512bw_mm512_mask_loadu_epi16function
4754core::core_arch::x86::avx512bw_mm512_mask_loadu_epi8function
4755core::core_arch::x86::avx512bw_mm512_mask_storeu_epi16function
4756core::core_arch::x86::avx512bw_mm512_mask_storeu_epi8function
4757core::core_arch::x86::avx512bw_mm512_maskz_loadu_epi16function
4758core::core_arch::x86::avx512bw_mm512_maskz_loadu_epi8function
4759core::core_arch::x86::avx512bw_mm512_storeu_epi16function
4760core::core_arch::x86::avx512bw_mm512_storeu_epi8function
4761core::core_arch::x86::avx512bw_mm_loadu_epi16function
4762core::core_arch::x86::avx512bw_mm_loadu_epi8function
4763core::core_arch::x86::avx512bw_mm_mask_cvtepi16_storeu_epi8function
4764core::core_arch::x86::avx512bw_mm_mask_cvtsepi16_storeu_epi8function
4765core::core_arch::x86::avx512bw_mm_mask_cvtusepi16_storeu_epi8function
4766core::core_arch::x86::avx512bw_mm_mask_loadu_epi16function
4767core::core_arch::x86::avx512bw_mm_mask_loadu_epi8function
4768core::core_arch::x86::avx512bw_mm_mask_storeu_epi16function
4769core::core_arch::x86::avx512bw_mm_mask_storeu_epi8function
4770core::core_arch::x86::avx512bw_mm_maskz_loadu_epi16function
4771core::core_arch::x86::avx512bw_mm_maskz_loadu_epi8function
4772core::core_arch::x86::avx512bw_mm_storeu_epi16function
4773core::core_arch::x86::avx512bw_mm_storeu_epi8function
4774core::core_arch::x86::avx512bw_store_mask32function
4775core::core_arch::x86::avx512bw_store_mask64function
4776core::core_arch::x86::avx512dq_kortest_mask8_u8function
4777core::core_arch::x86::avx512dq_ktest_mask16_u8function
4778core::core_arch::x86::avx512dq_ktest_mask8_u8function
4779core::core_arch::x86::avx512dq_load_mask8function
4780core::core_arch::x86::avx512dq_store_mask8function
4781core::core_arch::x86::avx512f_kortest_mask16_u8function
4782core::core_arch::x86::avx512f_load_mask16function
4783core::core_arch::x86::avx512f_mm256_i32scatter_epi32function
4784core::core_arch::x86::avx512f_mm256_i32scatter_epi64function
4785core::core_arch::x86::avx512f_mm256_i32scatter_pdfunction
4786core::core_arch::x86::avx512f_mm256_i32scatter_psfunction
4787core::core_arch::x86::avx512f_mm256_i64scatter_epi32function
4788core::core_arch::x86::avx512f_mm256_i64scatter_epi64function
4789core::core_arch::x86::avx512f_mm256_i64scatter_pdfunction
4790core::core_arch::x86::avx512f_mm256_i64scatter_psfunction
4791core::core_arch::x86::avx512f_mm256_load_epi32function
4792core::core_arch::x86::avx512f_mm256_load_epi64function
4793core::core_arch::x86::avx512f_mm256_loadu_epi32function
4794core::core_arch::x86::avx512f_mm256_loadu_epi64function
4795core::core_arch::x86::avx512f_mm256_mask_compressstoreu_epi32function
4796core::core_arch::x86::avx512f_mm256_mask_compressstoreu_epi64function
4797core::core_arch::x86::avx512f_mm256_mask_compressstoreu_pdfunction
4798core::core_arch::x86::avx512f_mm256_mask_compressstoreu_psfunction
4799core::core_arch::x86::avx512f_mm256_mask_cvtepi32_storeu_epi16function
4800core::core_arch::x86::avx512f_mm256_mask_cvtepi32_storeu_epi8function
4801core::core_arch::x86::avx512f_mm256_mask_cvtepi64_storeu_epi16function
4802core::core_arch::x86::avx512f_mm256_mask_cvtepi64_storeu_epi32function
4803core::core_arch::x86::avx512f_mm256_mask_cvtepi64_storeu_epi8function
4804core::core_arch::x86::avx512f_mm256_mask_cvtsepi32_storeu_epi16function
4805core::core_arch::x86::avx512f_mm256_mask_cvtsepi32_storeu_epi8function
4806core::core_arch::x86::avx512f_mm256_mask_cvtsepi64_storeu_epi16function
4807core::core_arch::x86::avx512f_mm256_mask_cvtsepi64_storeu_epi32function
4808core::core_arch::x86::avx512f_mm256_mask_cvtsepi64_storeu_epi8function
4809core::core_arch::x86::avx512f_mm256_mask_cvtusepi32_storeu_epi16function
4810core::core_arch::x86::avx512f_mm256_mask_cvtusepi32_storeu_epi8function
4811core::core_arch::x86::avx512f_mm256_mask_cvtusepi64_storeu_epi16function
4812core::core_arch::x86::avx512f_mm256_mask_cvtusepi64_storeu_epi32function
4813core::core_arch::x86::avx512f_mm256_mask_cvtusepi64_storeu_epi8function
4814core::core_arch::x86::avx512f_mm256_mask_expandloadu_epi32function
4815core::core_arch::x86::avx512f_mm256_mask_expandloadu_epi64function
4816core::core_arch::x86::avx512f_mm256_mask_expandloadu_pdfunction
4817core::core_arch::x86::avx512f_mm256_mask_expandloadu_psfunction
4818core::core_arch::x86::avx512f_mm256_mask_i32scatter_epi32function
4819core::core_arch::x86::avx512f_mm256_mask_i32scatter_epi64function
4820core::core_arch::x86::avx512f_mm256_mask_i32scatter_pdfunction
4821core::core_arch::x86::avx512f_mm256_mask_i32scatter_psfunction
4822core::core_arch::x86::avx512f_mm256_mask_i64scatter_epi32function
4823core::core_arch::x86::avx512f_mm256_mask_i64scatter_epi64function
4824core::core_arch::x86::avx512f_mm256_mask_i64scatter_pdfunction
4825core::core_arch::x86::avx512f_mm256_mask_i64scatter_psfunction
4826core::core_arch::x86::avx512f_mm256_mask_load_epi32function
4827core::core_arch::x86::avx512f_mm256_mask_load_epi64function
4828core::core_arch::x86::avx512f_mm256_mask_load_pdfunction
4829core::core_arch::x86::avx512f_mm256_mask_load_psfunction
4830core::core_arch::x86::avx512f_mm256_mask_loadu_epi32function
4831core::core_arch::x86::avx512f_mm256_mask_loadu_epi64function
4832core::core_arch::x86::avx512f_mm256_mask_loadu_pdfunction
4833core::core_arch::x86::avx512f_mm256_mask_loadu_psfunction
4834core::core_arch::x86::avx512f_mm256_mask_store_epi32function
4835core::core_arch::x86::avx512f_mm256_mask_store_epi64function
4836core::core_arch::x86::avx512f_mm256_mask_store_pdfunction
4837core::core_arch::x86::avx512f_mm256_mask_store_psfunction
4838core::core_arch::x86::avx512f_mm256_mask_storeu_epi32function
4839core::core_arch::x86::avx512f_mm256_mask_storeu_epi64function
4840core::core_arch::x86::avx512f_mm256_mask_storeu_pdfunction
4841core::core_arch::x86::avx512f_mm256_mask_storeu_psfunction
4842core::core_arch::x86::avx512f_mm256_maskz_expandloadu_epi32function
4843core::core_arch::x86::avx512f_mm256_maskz_expandloadu_epi64function
4844core::core_arch::x86::avx512f_mm256_maskz_expandloadu_pdfunction
4845core::core_arch::x86::avx512f_mm256_maskz_expandloadu_psfunction
4846core::core_arch::x86::avx512f_mm256_maskz_load_epi32function
4847core::core_arch::x86::avx512f_mm256_maskz_load_epi64function
4848core::core_arch::x86::avx512f_mm256_maskz_load_pdfunction
4849core::core_arch::x86::avx512f_mm256_maskz_load_psfunction
4850core::core_arch::x86::avx512f_mm256_maskz_loadu_epi32function
4851core::core_arch::x86::avx512f_mm256_maskz_loadu_epi64function
4852core::core_arch::x86::avx512f_mm256_maskz_loadu_pdfunction
4853core::core_arch::x86::avx512f_mm256_maskz_loadu_psfunction
4854core::core_arch::x86::avx512f_mm256_mmask_i32gather_epi32function
4855core::core_arch::x86::avx512f_mm256_mmask_i32gather_epi64function
4856core::core_arch::x86::avx512f_mm256_mmask_i32gather_pdfunction
4857core::core_arch::x86::avx512f_mm256_mmask_i32gather_psfunction
4858core::core_arch::x86::avx512f_mm256_mmask_i64gather_epi32function
4859core::core_arch::x86::avx512f_mm256_mmask_i64gather_epi64function
4860core::core_arch::x86::avx512f_mm256_mmask_i64gather_pdfunction
4861core::core_arch::x86::avx512f_mm256_mmask_i64gather_psfunction
4862core::core_arch::x86::avx512f_mm256_store_epi32function
4863core::core_arch::x86::avx512f_mm256_store_epi64function
4864core::core_arch::x86::avx512f_mm256_storeu_epi32function
4865core::core_arch::x86::avx512f_mm256_storeu_epi64function
4866core::core_arch::x86::avx512f_mm512_i32gather_epi32function
4867core::core_arch::x86::avx512f_mm512_i32gather_epi64function
4868core::core_arch::x86::avx512f_mm512_i32gather_pdfunction
4869core::core_arch::x86::avx512f_mm512_i32gather_psfunction
4870core::core_arch::x86::avx512f_mm512_i32logather_epi64function
4871core::core_arch::x86::avx512f_mm512_i32logather_pdfunction
4872core::core_arch::x86::avx512f_mm512_i32loscatter_epi64function
4873core::core_arch::x86::avx512f_mm512_i32loscatter_pdfunction
4874core::core_arch::x86::avx512f_mm512_i32scatter_epi32function
4875core::core_arch::x86::avx512f_mm512_i32scatter_epi64function
4876core::core_arch::x86::avx512f_mm512_i32scatter_pdfunction
4877core::core_arch::x86::avx512f_mm512_i32scatter_psfunction
4878core::core_arch::x86::avx512f_mm512_i64gather_epi32function
4879core::core_arch::x86::avx512f_mm512_i64gather_epi64function
4880core::core_arch::x86::avx512f_mm512_i64gather_pdfunction
4881core::core_arch::x86::avx512f_mm512_i64gather_psfunction
4882core::core_arch::x86::avx512f_mm512_i64scatter_epi32function
4883core::core_arch::x86::avx512f_mm512_i64scatter_epi64function
4884core::core_arch::x86::avx512f_mm512_i64scatter_pdfunction
4885core::core_arch::x86::avx512f_mm512_i64scatter_psfunction
4886core::core_arch::x86::avx512f_mm512_load_epi32function
4887core::core_arch::x86::avx512f_mm512_load_epi64function
4888core::core_arch::x86::avx512f_mm512_load_pdfunction
4889core::core_arch::x86::avx512f_mm512_load_psfunction
4890core::core_arch::x86::avx512f_mm512_load_si512function
4891core::core_arch::x86::avx512f_mm512_loadu_epi32function
4892core::core_arch::x86::avx512f_mm512_loadu_epi64function
4893core::core_arch::x86::avx512f_mm512_loadu_pdfunction
4894core::core_arch::x86::avx512f_mm512_loadu_psfunction
4895core::core_arch::x86::avx512f_mm512_loadu_si512function
4896core::core_arch::x86::avx512f_mm512_mask_compressstoreu_epi32function
4897core::core_arch::x86::avx512f_mm512_mask_compressstoreu_epi64function
4898core::core_arch::x86::avx512f_mm512_mask_compressstoreu_pdfunction
4899core::core_arch::x86::avx512f_mm512_mask_compressstoreu_psfunction
4900core::core_arch::x86::avx512f_mm512_mask_cvtepi32_storeu_epi16function
4901core::core_arch::x86::avx512f_mm512_mask_cvtepi32_storeu_epi8function
4902core::core_arch::x86::avx512f_mm512_mask_cvtepi64_storeu_epi16function
4903core::core_arch::x86::avx512f_mm512_mask_cvtepi64_storeu_epi32function
4904core::core_arch::x86::avx512f_mm512_mask_cvtepi64_storeu_epi8function
4905core::core_arch::x86::avx512f_mm512_mask_cvtsepi32_storeu_epi16function
4906core::core_arch::x86::avx512f_mm512_mask_cvtsepi32_storeu_epi8function
4907core::core_arch::x86::avx512f_mm512_mask_cvtsepi64_storeu_epi16function
4908core::core_arch::x86::avx512f_mm512_mask_cvtsepi64_storeu_epi32function
4909core::core_arch::x86::avx512f_mm512_mask_cvtsepi64_storeu_epi8function
4910core::core_arch::x86::avx512f_mm512_mask_cvtusepi32_storeu_epi16function
4911core::core_arch::x86::avx512f_mm512_mask_cvtusepi32_storeu_epi8function
4912core::core_arch::x86::avx512f_mm512_mask_cvtusepi64_storeu_epi16function
4913core::core_arch::x86::avx512f_mm512_mask_cvtusepi64_storeu_epi32function
4914core::core_arch::x86::avx512f_mm512_mask_cvtusepi64_storeu_epi8function
4915core::core_arch::x86::avx512f_mm512_mask_expandloadu_epi32function
4916core::core_arch::x86::avx512f_mm512_mask_expandloadu_epi64function
4917core::core_arch::x86::avx512f_mm512_mask_expandloadu_pdfunction
4918core::core_arch::x86::avx512f_mm512_mask_expandloadu_psfunction
4919core::core_arch::x86::avx512f_mm512_mask_i32gather_epi32function
4920core::core_arch::x86::avx512f_mm512_mask_i32gather_epi64function
4921core::core_arch::x86::avx512f_mm512_mask_i32gather_pdfunction
4922core::core_arch::x86::avx512f_mm512_mask_i32gather_psfunction
4923core::core_arch::x86::avx512f_mm512_mask_i32logather_epi64function
4924core::core_arch::x86::avx512f_mm512_mask_i32logather_pdfunction
4925core::core_arch::x86::avx512f_mm512_mask_i32loscatter_epi64function
4926core::core_arch::x86::avx512f_mm512_mask_i32loscatter_pdfunction
4927core::core_arch::x86::avx512f_mm512_mask_i32scatter_epi32function
4928core::core_arch::x86::avx512f_mm512_mask_i32scatter_epi64function
4929core::core_arch::x86::avx512f_mm512_mask_i32scatter_pdfunction
4930core::core_arch::x86::avx512f_mm512_mask_i32scatter_psfunction
4931core::core_arch::x86::avx512f_mm512_mask_i64gather_epi32function
4932core::core_arch::x86::avx512f_mm512_mask_i64gather_epi64function
4933core::core_arch::x86::avx512f_mm512_mask_i64gather_pdfunction
4934core::core_arch::x86::avx512f_mm512_mask_i64gather_psfunction
4935core::core_arch::x86::avx512f_mm512_mask_i64scatter_epi32function
4936core::core_arch::x86::avx512f_mm512_mask_i64scatter_epi64function
4937core::core_arch::x86::avx512f_mm512_mask_i64scatter_pdfunction
4938core::core_arch::x86::avx512f_mm512_mask_i64scatter_psfunction
4939core::core_arch::x86::avx512f_mm512_mask_load_epi32function
4940core::core_arch::x86::avx512f_mm512_mask_load_epi64function
4941core::core_arch::x86::avx512f_mm512_mask_load_pdfunction
4942core::core_arch::x86::avx512f_mm512_mask_load_psfunction
4943core::core_arch::x86::avx512f_mm512_mask_loadu_epi32function
4944core::core_arch::x86::avx512f_mm512_mask_loadu_epi64function
4945core::core_arch::x86::avx512f_mm512_mask_loadu_pdfunction
4946core::core_arch::x86::avx512f_mm512_mask_loadu_psfunction
4947core::core_arch::x86::avx512f_mm512_mask_store_epi32function
4948core::core_arch::x86::avx512f_mm512_mask_store_epi64function
4949core::core_arch::x86::avx512f_mm512_mask_store_pdfunction
4950core::core_arch::x86::avx512f_mm512_mask_store_psfunction
4951core::core_arch::x86::avx512f_mm512_mask_storeu_epi32function
4952core::core_arch::x86::avx512f_mm512_mask_storeu_epi64function
4953core::core_arch::x86::avx512f_mm512_mask_storeu_pdfunction
4954core::core_arch::x86::avx512f_mm512_mask_storeu_psfunction
4955core::core_arch::x86::avx512f_mm512_maskz_expandloadu_epi32function
4956core::core_arch::x86::avx512f_mm512_maskz_expandloadu_epi64function
4957core::core_arch::x86::avx512f_mm512_maskz_expandloadu_pdfunction
4958core::core_arch::x86::avx512f_mm512_maskz_expandloadu_psfunction
4959core::core_arch::x86::avx512f_mm512_maskz_load_epi32function
4960core::core_arch::x86::avx512f_mm512_maskz_load_epi64function
4961core::core_arch::x86::avx512f_mm512_maskz_load_pdfunction
4962core::core_arch::x86::avx512f_mm512_maskz_load_psfunction
4963core::core_arch::x86::avx512f_mm512_maskz_loadu_epi32function
4964core::core_arch::x86::avx512f_mm512_maskz_loadu_epi64function
4965core::core_arch::x86::avx512f_mm512_maskz_loadu_pdfunction
4966core::core_arch::x86::avx512f_mm512_maskz_loadu_psfunction
4967core::core_arch::x86::avx512f_mm512_store_epi32function
4968core::core_arch::x86::avx512f_mm512_store_epi64function
4969core::core_arch::x86::avx512f_mm512_store_pdfunction
4970core::core_arch::x86::avx512f_mm512_store_psfunction
4971core::core_arch::x86::avx512f_mm512_store_si512function
4972core::core_arch::x86::avx512f_mm512_storeu_epi32function
4973core::core_arch::x86::avx512f_mm512_storeu_epi64function
4974core::core_arch::x86::avx512f_mm512_storeu_pdfunction
4975core::core_arch::x86::avx512f_mm512_storeu_psfunction
4976core::core_arch::x86::avx512f_mm512_storeu_si512function
4977core::core_arch::x86::avx512f_mm512_stream_load_si512function
4978core::core_arch::x86::avx512f_mm512_stream_pdfunction

After using this intrinsic, but before any other access to the memory that this intrinsic mutates, a call to _mm_sfence must be performed by the thread that used the intrinsic. In particular, functions that call this intrinsic should generally call _mm_sfence before they return.

See _mm_sfence for details.

PostToFunc
4979core::core_arch::x86::avx512f_mm512_stream_psfunction

After using this intrinsic, but before any other access to the memory that this intrinsic mutates, a call to _mm_sfence must be performed by the thread that used the intrinsic. In particular, functions that call this intrinsic should generally call _mm_sfence before they return.

See _mm_sfence for details.

PostToFunc
4980core::core_arch::x86::avx512f_mm512_stream_si512function

After using this intrinsic, but before any other access to the memory that this intrinsic mutates, a call to _mm_sfence must be performed by the thread that used the intrinsic. In particular, functions that call this intrinsic should generally call _mm_sfence before they return.

See _mm_sfence for details.

PostToFunc
4981core::core_arch::x86::avx512f_mm_i32scatter_epi32function
4982core::core_arch::x86::avx512f_mm_i32scatter_epi64function
4983core::core_arch::x86::avx512f_mm_i32scatter_pdfunction
4984core::core_arch::x86::avx512f_mm_i32scatter_psfunction
4985core::core_arch::x86::avx512f_mm_i64scatter_epi32function
4986core::core_arch::x86::avx512f_mm_i64scatter_epi64function
4987core::core_arch::x86::avx512f_mm_i64scatter_pdfunction
4988core::core_arch::x86::avx512f_mm_i64scatter_psfunction
4989core::core_arch::x86::avx512f_mm_load_epi32function
4990core::core_arch::x86::avx512f_mm_load_epi64function
4991core::core_arch::x86::avx512f_mm_loadu_epi32function
4992core::core_arch::x86::avx512f_mm_loadu_epi64function
4993core::core_arch::x86::avx512f_mm_mask_compressstoreu_epi32function
4994core::core_arch::x86::avx512f_mm_mask_compressstoreu_epi64function
4995core::core_arch::x86::avx512f_mm_mask_compressstoreu_pdfunction
4996core::core_arch::x86::avx512f_mm_mask_compressstoreu_psfunction
4997core::core_arch::x86::avx512f_mm_mask_cvtepi32_storeu_epi16function
4998core::core_arch::x86::avx512f_mm_mask_cvtepi32_storeu_epi8function
4999core::core_arch::x86::avx512f_mm_mask_cvtepi64_storeu_epi16function
5000core::core_arch::x86::avx512f_mm_mask_cvtepi64_storeu_epi32function
5001core::core_arch::x86::avx512f_mm_mask_cvtepi64_storeu_epi8function
5002core::core_arch::x86::avx512f_mm_mask_cvtsepi32_storeu_epi16function
5003core::core_arch::x86::avx512f_mm_mask_cvtsepi32_storeu_epi8function
5004core::core_arch::x86::avx512f_mm_mask_cvtsepi64_storeu_epi16function
5005core::core_arch::x86::avx512f_mm_mask_cvtsepi64_storeu_epi32function
5006core::core_arch::x86::avx512f_mm_mask_cvtsepi64_storeu_epi8function
5007core::core_arch::x86::avx512f_mm_mask_cvtusepi32_storeu_epi16function
5008core::core_arch::x86::avx512f_mm_mask_cvtusepi32_storeu_epi8function
5009core::core_arch::x86::avx512f_mm_mask_cvtusepi64_storeu_epi16function
5010core::core_arch::x86::avx512f_mm_mask_cvtusepi64_storeu_epi32function
5011core::core_arch::x86::avx512f_mm_mask_cvtusepi64_storeu_epi8function
5012core::core_arch::x86::avx512f_mm_mask_expandloadu_epi32function
5013core::core_arch::x86::avx512f_mm_mask_expandloadu_epi64function
5014core::core_arch::x86::avx512f_mm_mask_expandloadu_pdfunction
5015core::core_arch::x86::avx512f_mm_mask_expandloadu_psfunction
5016core::core_arch::x86::avx512f_mm_mask_i32scatter_epi32function
5017core::core_arch::x86::avx512f_mm_mask_i32scatter_epi64function
5018core::core_arch::x86::avx512f_mm_mask_i32scatter_pdfunction
5019core::core_arch::x86::avx512f_mm_mask_i32scatter_psfunction
5020core::core_arch::x86::avx512f_mm_mask_i64scatter_epi32function
5021core::core_arch::x86::avx512f_mm_mask_i64scatter_epi64function
5022core::core_arch::x86::avx512f_mm_mask_i64scatter_pdfunction
5023core::core_arch::x86::avx512f_mm_mask_i64scatter_psfunction
5024core::core_arch::x86::avx512f_mm_mask_load_epi32function
5025core::core_arch::x86::avx512f_mm_mask_load_epi64function
5026core::core_arch::x86::avx512f_mm_mask_load_pdfunction
5027core::core_arch::x86::avx512f_mm_mask_load_psfunction
5028core::core_arch::x86::avx512f_mm_mask_load_sdfunction
5029core::core_arch::x86::avx512f_mm_mask_load_ssfunction
5030core::core_arch::x86::avx512f_mm_mask_loadu_epi32function
5031core::core_arch::x86::avx512f_mm_mask_loadu_epi64function
5032core::core_arch::x86::avx512f_mm_mask_loadu_pdfunction
5033core::core_arch::x86::avx512f_mm_mask_loadu_psfunction
5034core::core_arch::x86::avx512f_mm_mask_store_epi32function
5035core::core_arch::x86::avx512f_mm_mask_store_epi64function
5036core::core_arch::x86::avx512f_mm_mask_store_pdfunction
5037core::core_arch::x86::avx512f_mm_mask_store_psfunction
5038core::core_arch::x86::avx512f_mm_mask_store_sdfunction
5039core::core_arch::x86::avx512f_mm_mask_store_ssfunction
5040core::core_arch::x86::avx512f_mm_mask_storeu_epi32function
5041core::core_arch::x86::avx512f_mm_mask_storeu_epi64function
5042core::core_arch::x86::avx512f_mm_mask_storeu_pdfunction
5043core::core_arch::x86::avx512f_mm_mask_storeu_psfunction
5044core::core_arch::x86::avx512f_mm_maskz_expandloadu_epi32function
5045core::core_arch::x86::avx512f_mm_maskz_expandloadu_epi64function
5046core::core_arch::x86::avx512f_mm_maskz_expandloadu_pdfunction
5047core::core_arch::x86::avx512f_mm_maskz_expandloadu_psfunction
5048core::core_arch::x86::avx512f_mm_maskz_load_epi32function
5049core::core_arch::x86::avx512f_mm_maskz_load_epi64function
5050core::core_arch::x86::avx512f_mm_maskz_load_pdfunction
5051core::core_arch::x86::avx512f_mm_maskz_load_psfunction
5052core::core_arch::x86::avx512f_mm_maskz_load_sdfunction
5053core::core_arch::x86::avx512f_mm_maskz_load_ssfunction
5054core::core_arch::x86::avx512f_mm_maskz_loadu_epi32function
5055core::core_arch::x86::avx512f_mm_maskz_loadu_epi64function
5056core::core_arch::x86::avx512f_mm_maskz_loadu_pdfunction
5057core::core_arch::x86::avx512f_mm_maskz_loadu_psfunction
5058core::core_arch::x86::avx512f_mm_mmask_i32gather_epi32function
5059core::core_arch::x86::avx512f_mm_mmask_i32gather_epi64function
5060core::core_arch::x86::avx512f_mm_mmask_i32gather_pdfunction
5061core::core_arch::x86::avx512f_mm_mmask_i32gather_psfunction
5062core::core_arch::x86::avx512f_mm_mmask_i64gather_epi32function
5063core::core_arch::x86::avx512f_mm_mmask_i64gather_epi64function
5064core::core_arch::x86::avx512f_mm_mmask_i64gather_pdfunction
5065core::core_arch::x86::avx512f_mm_mmask_i64gather_psfunction
5066core::core_arch::x86::avx512f_mm_store_epi32function
5067core::core_arch::x86::avx512f_mm_store_epi64function
5068core::core_arch::x86::avx512f_mm_storeu_epi32function
5069core::core_arch::x86::avx512f_mm_storeu_epi64function
5070core::core_arch::x86::avx512f_store_mask16function
5071core::core_arch::x86::avx512fp16_mm256_load_phfunction
5072core::core_arch::x86::avx512fp16_mm256_loadu_phfunction
5073core::core_arch::x86::avx512fp16_mm256_store_phfunction
5074core::core_arch::x86::avx512fp16_mm256_storeu_phfunction
5075core::core_arch::x86::avx512fp16_mm512_load_phfunction
5076core::core_arch::x86::avx512fp16_mm512_loadu_phfunction
5077core::core_arch::x86::avx512fp16_mm512_store_phfunction
5078core::core_arch::x86::avx512fp16_mm512_storeu_phfunction
5079core::core_arch::x86::avx512fp16_mm_load_phfunction
5080core::core_arch::x86::avx512fp16_mm_load_shfunction
5081core::core_arch::x86::avx512fp16_mm_loadu_phfunction
5082core::core_arch::x86::avx512fp16_mm_mask_load_shfunction
5083core::core_arch::x86::avx512fp16_mm_mask_store_shfunction
5084core::core_arch::x86::avx512fp16_mm_maskz_load_shfunction
5085core::core_arch::x86::avx512fp16_mm_store_phfunction
5086core::core_arch::x86::avx512fp16_mm_store_shfunction
5087core::core_arch::x86::avx512fp16_mm_storeu_phfunction
5088core::core_arch::x86::avx512vbmi2_mm256_mask_compressstoreu_epi16function
5089core::core_arch::x86::avx512vbmi2_mm256_mask_compressstoreu_epi8function
5090core::core_arch::x86::avx512vbmi2_mm256_mask_expandloadu_epi16function
5091core::core_arch::x86::avx512vbmi2_mm256_mask_expandloadu_epi8function
5092core::core_arch::x86::avx512vbmi2_mm256_maskz_expandloadu_epi16function
5093core::core_arch::x86::avx512vbmi2_mm256_maskz_expandloadu_epi8function
5094core::core_arch::x86::avx512vbmi2_mm512_mask_compressstoreu_epi16function
5095core::core_arch::x86::avx512vbmi2_mm512_mask_compressstoreu_epi8function
5096core::core_arch::x86::avx512vbmi2_mm512_mask_expandloadu_epi16function
5097core::core_arch::x86::avx512vbmi2_mm512_mask_expandloadu_epi8function
5098core::core_arch::x86::avx512vbmi2_mm512_maskz_expandloadu_epi16function
5099core::core_arch::x86::avx512vbmi2_mm512_maskz_expandloadu_epi8function
5100core::core_arch::x86::avx512vbmi2_mm_mask_compressstoreu_epi16function
5101core::core_arch::x86::avx512vbmi2_mm_mask_compressstoreu_epi8function
5102core::core_arch::x86::avx512vbmi2_mm_mask_expandloadu_epi16function
5103core::core_arch::x86::avx512vbmi2_mm_mask_expandloadu_epi8function
5104core::core_arch::x86::avx512vbmi2_mm_maskz_expandloadu_epi16function
5105core::core_arch::x86::avx512vbmi2_mm_maskz_expandloadu_epi8function
5106core::core_arch::x86::avx512vp2intersect_mm256_2intersect_epi32function
5107core::core_arch::x86::avx512vp2intersect_mm256_2intersect_epi64function
5108core::core_arch::x86::avx512vp2intersect_mm512_2intersect_epi32function
5109core::core_arch::x86::avx512vp2intersect_mm512_2intersect_epi64function
5110core::core_arch::x86::avx512vp2intersect_mm_2intersect_epi32function
5111core::core_arch::x86::avx512vp2intersect_mm_2intersect_epi64function
5112core::core_arch::x86::avxneconvert_mm256_bcstnebf16_psfunction
5113core::core_arch::x86::avxneconvert_mm256_bcstnesh_psfunction
5114core::core_arch::x86::avxneconvert_mm256_cvtneebf16_psfunction
5115core::core_arch::x86::avxneconvert_mm256_cvtneeph_psfunction
5116core::core_arch::x86::avxneconvert_mm256_cvtneobf16_psfunction
5117core::core_arch::x86::avxneconvert_mm256_cvtneoph_psfunction
5118core::core_arch::x86::avxneconvert_mm_bcstnebf16_psfunction
5119core::core_arch::x86::avxneconvert_mm_bcstnesh_psfunction
5120core::core_arch::x86::avxneconvert_mm_cvtneebf16_psfunction
5121core::core_arch::x86::avxneconvert_mm_cvtneeph_psfunction
5122core::core_arch::x86::avxneconvert_mm_cvtneobf16_psfunction
5123core::core_arch::x86::avxneconvert_mm_cvtneoph_psfunction
5124core::core_arch::x86::bt_bittestfunction
5125core::core_arch::x86::bt_bittestandcomplementfunction
5126core::core_arch::x86::bt_bittestandresetfunction
5127core::core_arch::x86::bt_bittestandsetfunction
5128core::core_arch::x86::clflushopt_mm_clflushoptfunction

Unlike the prefetch intrinsics, CLFLUSHOPT is subject to all the permission checking and faults associated with a byte load, so p must point to a byte that is valid for reads.

ValidRead, Assoc
5129core::core_arch::x86::fxsr_fxrstorfunction
5130core::core_arch::x86::fxsr_fxsavefunction
5131core::core_arch::x86::kl_mm_aesdec128kl_u8function
5132core::core_arch::x86::kl_mm_aesdec256kl_u8function
5133core::core_arch::x86::kl_mm_aesdecwide128kl_u8function
5134core::core_arch::x86::kl_mm_aesdecwide256kl_u8function
5135core::core_arch::x86::kl_mm_aesenc128kl_u8function
5136core::core_arch::x86::kl_mm_aesenc256kl_u8function
5137core::core_arch::x86::kl_mm_aesencwide128kl_u8function
5138core::core_arch::x86::kl_mm_aesencwide256kl_u8function
5139core::core_arch::x86::kl_mm_encodekey128_u32function
5140core::core_arch::x86::kl_mm_encodekey256_u32function
5141core::core_arch::x86::kl_mm_loadiwkeyfunction
5142core::core_arch::x86::rdtsc__rdtscpfunction
5143core::core_arch::x86::rdtsc_rdtscfunction
5144core::core_arch::x86::rtm_xabortfunction
5145core::core_arch::x86::rtm_xbeginfunction
5146core::core_arch::x86::rtm_xendfunction
5147core::core_arch::x86::rtm_xtestfunction
5148core::core_arch::x86::sse_MM_GET_EXCEPTION_MASKfunction
5149core::core_arch::x86::sse_MM_GET_EXCEPTION_STATEfunction
5150core::core_arch::x86::sse_MM_GET_FLUSH_ZERO_MODEfunction
5151core::core_arch::x86::sse_MM_GET_ROUNDING_MODEfunction
5152core::core_arch::x86::sse_MM_SET_EXCEPTION_MASKfunction
5153core::core_arch::x86::sse_MM_SET_EXCEPTION_STATEfunction
5154core::core_arch::x86::sse_MM_SET_FLUSH_ZERO_MODEfunction
5155core::core_arch::x86::sse_MM_SET_ROUNDING_MODEfunction
5156core::core_arch::x86::sse_mm_getcsrfunction
5157core::core_arch::x86::sse_mm_load1_psfunction
5158core::core_arch::x86::sse_mm_load_psfunction
5159core::core_arch::x86::sse_mm_load_ps1function
5160core::core_arch::x86::sse_mm_load_ssfunction
5161core::core_arch::x86::sse_mm_loadr_psfunction
5162core::core_arch::x86::sse_mm_loadu_psfunction
5163core::core_arch::x86::sse_mm_setcsrfunction
5164core::core_arch::x86::sse_mm_store1_psfunction
5165core::core_arch::x86::sse_mm_store_psfunction
5166core::core_arch::x86::sse_mm_store_ps1function
5167core::core_arch::x86::sse_mm_store_ssfunction
5168core::core_arch::x86::sse_mm_storer_psfunction
5169core::core_arch::x86::sse_mm_storeu_psfunction
5170core::core_arch::x86::sse_mm_stream_psfunction

After using this intrinsic, but before any other access to the memory that this intrinsic mutates, a call to _mm_sfence must be performed by the thread that used the intrinsic. In particular, functions that call this intrinsic should generally call _mm_sfence before they return.

See _mm_sfence for details.

PostToFunc
5171core::core_arch::x86::sse2_mm_clflushfunction

Unlike the prefetch intrinsics, CLFLUSH is subject to all the permission checking and faults associated with a byte load, so p must point to a byte that is valid for reads.

ValidRead, Assoc
5172core::core_arch::x86::sse2_mm_load1_pdfunction
5173core::core_arch::x86::sse2_mm_load_pdfunction
5174core::core_arch::x86::sse2_mm_load_pd1function
5175core::core_arch::x86::sse2_mm_load_sdfunction
5176core::core_arch::x86::sse2_mm_load_si128function
5177core::core_arch::x86::sse2_mm_loadh_pdfunction
5178core::core_arch::x86::sse2_mm_loadl_epi64function
5179core::core_arch::x86::sse2_mm_loadl_pdfunction
5180core::core_arch::x86::sse2_mm_loadr_pdfunction
5181core::core_arch::x86::sse2_mm_loadu_pdfunction
5182core::core_arch::x86::sse2_mm_loadu_si128function
5183core::core_arch::x86::sse2_mm_loadu_si16function
5184core::core_arch::x86::sse2_mm_loadu_si32function
5185core::core_arch::x86::sse2_mm_loadu_si64function
5186core::core_arch::x86::sse2_mm_maskmoveu_si128function

After using this intrinsic, but before any other access to the memory that this intrinsic mutates, a call to _mm_sfence must be performed by the thread that used the intrinsic. In particular, functions that call this intrinsic should generally call _mm_sfence before they return.

See _mm_sfence for details.

PostToFunc
5187core::core_arch::x86::sse2_mm_store1_pdfunction
5188core::core_arch::x86::sse2_mm_store_pdfunction
5189core::core_arch::x86::sse2_mm_store_pd1function
5190core::core_arch::x86::sse2_mm_store_sdfunction
5191core::core_arch::x86::sse2_mm_store_si128function
5192core::core_arch::x86::sse2_mm_storeh_pdfunction
5193core::core_arch::x86::sse2_mm_storel_epi64function
5194core::core_arch::x86::sse2_mm_storel_pdfunction
5195core::core_arch::x86::sse2_mm_storer_pdfunction
5196core::core_arch::x86::sse2_mm_storeu_pdfunction
5197core::core_arch::x86::sse2_mm_storeu_si128function
5198core::core_arch::x86::sse2_mm_storeu_si16function
5199core::core_arch::x86::sse2_mm_storeu_si32function
5200core::core_arch::x86::sse2_mm_storeu_si64function
5201core::core_arch::x86::sse2_mm_stream_pdfunction

After using this intrinsic, but before any other access to the memory that this intrinsic mutates, a call to _mm_sfence must be performed by the thread that used the intrinsic. In particular, functions that call this intrinsic should generally call _mm_sfence before they return.

See _mm_sfence for details.

PostToFunc
5202core::core_arch::x86::sse2_mm_stream_si128function

After using this intrinsic, but before any other access to the memory that this intrinsic mutates, a call to _mm_sfence must be performed by the thread that used the intrinsic. In particular, functions that call this intrinsic should generally call _mm_sfence before they return.

See _mm_sfence for details.

PostToFunc
5203core::core_arch::x86::sse2_mm_stream_si32function

After using this intrinsic, but before any other access to the memory that this intrinsic mutates, a call to _mm_sfence must be performed by the thread that used the intrinsic. In particular, functions that call this intrinsic should generally call _mm_sfence before they return.

See _mm_sfence for details.

PostToFunc
5204core::core_arch::x86::sse3_mm_lddqu_si128function
5205core::core_arch::x86::sse3_mm_loaddup_pdfunction
5206core::core_arch::x86::sse41_mm_stream_load_si128function
5207core::core_arch::x86::sse4a_mm_stream_sdfunction

After using this intrinsic, but before any other access to the memory that this intrinsic mutates, a call to _mm_sfence must be performed by the thread that used the intrinsic. In particular, functions that call this intrinsic should generally call _mm_sfence before they return.

See _mm_sfence for details.

PostToFunc
5208core::core_arch::x86::sse4a_mm_stream_ssfunction

After using this intrinsic, but before any other access to the memory that this intrinsic mutates, a call to _mm_sfence must be performed by the thread that used the intrinsic. In particular, functions that call this intrinsic should generally call _mm_sfence before they return.

See _mm_sfence for details.

PostToFunc
5209core::core_arch::x86::xsave_xgetbvfunction
5210core::core_arch::x86::xsave_xrstorfunction
5211core::core_arch::x86::xsave_xrstorsfunction
5212core::core_arch::x86::xsave_xsavefunction
5213core::core_arch::x86::xsave_xsavecfunction
5214core::core_arch::x86::xsave_xsaveoptfunction
5215core::core_arch::x86::xsave_xsavesfunction
5216core::core_arch::x86::xsave_xsetbvfunction
5217core::core_arch::x86_64::amx__tile_cmmimfp16psfunction
5218core::core_arch::x86_64::amx__tile_cmmrlfp16psfunction
5219core::core_arch::x86_64::amx__tile_cvtrowd2psfunction
5220core::core_arch::x86_64::amx__tile_cvtrowps2bf16hfunction
5221core::core_arch::x86_64::amx__tile_cvtrowps2bf16lfunction
5222core::core_arch::x86_64::amx__tile_cvtrowps2phhfunction
5223core::core_arch::x86_64::amx__tile_cvtrowps2phlfunction
5224core::core_arch::x86_64::amx__tile_dpbf16psfunction
5225core::core_arch::x86_64::amx__tile_dpbf8psfunction
5226core::core_arch::x86_64::amx__tile_dpbhf8psfunction
5227core::core_arch::x86_64::amx__tile_dpbssdfunction
5228core::core_arch::x86_64::amx__tile_dpbsudfunction
5229core::core_arch::x86_64::amx__tile_dpbusdfunction
5230core::core_arch::x86_64::amx__tile_dpbuudfunction
5231core::core_arch::x86_64::amx__tile_dpfp16psfunction
5232core::core_arch::x86_64::amx__tile_dphbf8psfunction
5233core::core_arch::x86_64::amx__tile_dphf8psfunction
5234core::core_arch::x86_64::amx__tile_loaddfunction
5235core::core_arch::x86_64::amx__tile_loaddrsfunction
5236core::core_arch::x86_64::amx__tile_movrowfunction
5237core::core_arch::x86_64::amx__tile_storedfunction
5238core::core_arch::x86_64::amx__tile_stream_loaddfunction
5239core::core_arch::x86_64::amx__tile_stream_loaddrsfunction
5240core::core_arch::x86_64::amx__tile_zerofunction
5241core::core_arch::x86_64::amx_tile_cmmimfp16psfunction
5242core::core_arch::x86_64::amx_tile_cmmrlfp16psfunction
5243core::core_arch::x86_64::amx_tile_cvtrowd2psfunction
5244core::core_arch::x86_64::amx_tile_cvtrowd2psifunction
5245core::core_arch::x86_64::amx_tile_cvtrowps2bf16hfunction
5246core::core_arch::x86_64::amx_tile_cvtrowps2bf16hifunction
5247core::core_arch::x86_64::amx_tile_cvtrowps2bf16lfunction
5248core::core_arch::x86_64::amx_tile_cvtrowps2bf16lifunction
5249core::core_arch::x86_64::amx_tile_cvtrowps2phhfunction
5250core::core_arch::x86_64::amx_tile_cvtrowps2phhifunction
5251core::core_arch::x86_64::amx_tile_cvtrowps2phlfunction
5252core::core_arch::x86_64::amx_tile_cvtrowps2phlifunction
5253core::core_arch::x86_64::amx_tile_dpbf16psfunction
5254core::core_arch::x86_64::amx_tile_dpbf8psfunction
5255core::core_arch::x86_64::amx_tile_dpbhf8psfunction
5256core::core_arch::x86_64::amx_tile_dpbssdfunction
5257core::core_arch::x86_64::amx_tile_dpbsudfunction
5258core::core_arch::x86_64::amx_tile_dpbusdfunction
5259core::core_arch::x86_64::amx_tile_dpbuudfunction
5260core::core_arch::x86_64::amx_tile_dpfp16psfunction
5261core::core_arch::x86_64::amx_tile_dphbf8psfunction
5262core::core_arch::x86_64::amx_tile_dphf8psfunction
5263core::core_arch::x86_64::amx_tile_loadconfigfunction
5264core::core_arch::x86_64::amx_tile_loaddfunction
5265core::core_arch::x86_64::amx_tile_loaddrsfunction
5266core::core_arch::x86_64::amx_tile_movrowfunction
5267core::core_arch::x86_64::amx_tile_movrowifunction
5268core::core_arch::x86_64::amx_tile_releasefunction
5269core::core_arch::x86_64::amx_tile_storeconfigfunction
5270core::core_arch::x86_64::amx_tile_storedfunction
5271core::core_arch::x86_64::amx_tile_stream_loaddfunction
5272core::core_arch::x86_64::amx_tile_stream_loaddrsfunction
5273core::core_arch::x86_64::amx_tile_zerofunction
5274core::core_arch::x86_64::bt_bittest64function
5275core::core_arch::x86_64::bt_bittestandcomplement64function
5276core::core_arch::x86_64::bt_bittestandreset64function
5277core::core_arch::x86_64::bt_bittestandset64function
5278core::core_arch::x86_64::cmpxchg16bcmpxchg16bfunction
5279core::core_arch::x86_64::fxsr_fxrstor64function
5280core::core_arch::x86_64::fxsr_fxsave64function
5281core::core_arch::x86_64::movrs_movrs_i16function
5282core::core_arch::x86_64::movrs_movrs_i32function
5283core::core_arch::x86_64::movrs_movrs_i64function
5284core::core_arch::x86_64::movrs_movrs_i8function
5285core::core_arch::x86_64::sse2_mm_stream_si64function

After using this intrinsic, but before any other access to the memory that this intrinsic mutates, a call to _mm_sfence must be performed by the thread that used the intrinsic. In particular, functions that call this intrinsic should generally call _mm_sfence before they return.

See _mm_sfence for details.

PostToFunc
5286core::core_arch::x86_64::xsave_xrstor64function
5287core::core_arch::x86_64::xsave_xrstors64function
5288core::core_arch::x86_64::xsave_xsave64function
5289core::core_arch::x86_64::xsave_xsavec64function
5290core::core_arch::x86_64::xsave_xsaveopt64function
5291core::core_arch::x86_64::xsave_xsaves64function
5292core::core_simd::castSimdCasttrait

Implementing this trait asserts that the type is a valid vector element for the simd_cast or simd_as intrinsics.

5293core::core_simd::masksMaskElementtrait

Type must be a signed integer.

5294core::core_simd::masks::Maskfrom_simd_uncheckedmethod

All elements must be either 0 or -1.

5295core::core_simd::masks::Maskset_uncheckedmethod

index must be less than self.len().

5296core::core_simd::masks::Masktest_uncheckedmethod

index must be less than self.len().

5297core::core_simd::simd::num::float::SimdFloatto_int_uncheckedtrait_method

The value must:

  • Not be NaN
  • Not be infinite
  • Be representable in the return type, after truncating off its fractional part

If these requirements are infeasible or costly, consider using the safe function [cast], which saturates on conversion.

5298core::core_simd::vectorSimdElementtrait

This trait, when implemented, asserts the compiler can monomorphize #[repr(simd)] structs with the marked type as an element. Strictly, it is valid to impl if the vector will not be miscompiled. Practically, it is user-unfriendly to impl it if the vector won't compile, even when no soundness guarantees are broken by allowing the user to try.

5299core::core_simd::vector::Simdgather_ptrmethod

Each read must satisfy the same conditions as core::ptr::read.

5300core::core_simd::vector::Simdgather_select_ptrmethod

Enabled elements must satisfy the same conditions as core::ptr::read.

5301core::core_simd::vector::Simdgather_select_uncheckedmethod

Calling this function with an enabled out-of-bounds index is [undefined behavior] even if the resulting value is not used.

5302core::core_simd::vector::Simdload_select_ptrmethod

Enabled ptr elements must be safe to read as if by core::ptr::read.

ValidRead
5303core::core_simd::vector::Simdload_select_uncheckedmethod

Enabled loads must not exceed the length of slice.

InBound
5304core::core_simd::vector::Simdscatter_ptrmethod

Each write must satisfy the same conditions as core::ptr::write.

5305core::core_simd::vector::Simdscatter_select_ptrmethod

Enabled pointers must satisfy the same conditions as core::ptr::write.

5306core::core_simd::vector::Simdscatter_select_uncheckedmethod

Calling this function with an enabled out-of-bounds index is [undefined behavior], and may lead to memory corruption.

MayInvalid
5307core::core_simd::vector::Simdstore_select_ptrmethod

Memory addresses for element are calculated pointer::wrapping_offset and each enabled element must satisfy the same conditions as core::ptr::write.

5308core::core_simd::vector::Simdstore_select_uncheckedmethod

Every enabled element must be in bounds for the slice.

InBound
5309core::core_simd::vector::Simdto_int_uncheckedmethod

The value must:

  • Not be NaN
  • Not be infinite
  • Be representable in the return type, after truncating off its fractional part

If these requirements are infeasible or costly, consider using the safe function [cast], which saturates on conversion.

5310core::f128to_int_uncheckedmethod

The value must:

  • Not be NaN
  • Not be infinite
  • Be representable in the return type Int, after truncating off its fractional part
5311core::f16to_int_uncheckedmethod

The value must:

  • Not be NaN
  • Not be infinite
  • Be representable in the return type Int, after truncating off its fractional part
5312core::f32to_int_uncheckedmethod

The value must:

  • Not be NaN
  • Not be infinite
  • Be representable in the return type Int, after truncating off its fractional part
5313core::f64to_int_uncheckedmethod

The value must:

  • Not be NaN
  • Not be infinite
  • Be representable in the return type Int, after truncating off its fractional part
5314core::ffiVaArgSafetrait

When C passes variable arguments, signed integers smaller than c_int are promoted to c_int, unsigned integers smaller than c_uint are promoted to c_uint, and c_float is promoted to c_double. Implementing this trait for types that are subject to this promotion rule is invalid.

This trait is only implemented for 128-bit integers when the platform defines the __int128 type.

5315core::ffi::c_str::CStrclone_to_uninitmethod

Behavior is undefined if any of the following conditions are violated:

  • dest must be [valid] for writes for size_of_val(self) bytes.
  • dest must be properly aligned to align_of_val(self).
Align
5316core::ffi::c_str::CStrfrom_bytes_with_nul_uncheckedmethod

The provided slice must be nul-terminated and not contain any interior nul bytes.

ValidCStr
5317core::ffi::c_str::CStrfrom_ptrmethod
  • The memory pointed to by ptr must contain a valid nul terminator at the end of the string.
  • ptr must be [valid] for reads of bytes up to and including the nul terminator. This means in particular:
  • The entire memory range of this CStr must be contained within a single allocation!
  • ptr must be non-null even for a zero-length cstr.
  • The memory referenced by the returned CStr must not be mutated for the duration of lifetime 'a.
  • The nul terminator must be within isize::MAX from ptr

> Note: This operation is intended to be a 0-cost cast but it is > currently implemented with an up-front calculation of the length of > the string. This is not guaranteed to always be the case.

NonNull, InBound, ValidNum, NonMutate
5318core::ffi::va_list::VaListnext_argmethod

This function is safe to call only if all of the following conditions are satisfied:

  • There is another c-variadic argument to read.
  • The actual type of the argument U is compatible with T (as defined below).
  • If U and T are both integer types, then the value passed by the caller must be representable in both types.
  • If T is not Copy, then it must not have already been read using next_arg on a clone[VaList::clone]d copy of this VaList. (Currently, all types implementing VaArgSafe also implement Copy, but this may change in the future.)

Types T and U are compatible when:

  • T and U are the same type.
  • T and U are integer types of the same size.
  • T and U are both pointers, and their target types are compatible.
  • T is a pointer to c_void and U is a pointer to i8 or u8, or vice versa.
5319core::fieldFieldtrait

Given a valid value of type Self::Base, there exists a valid value of type Self::Type at byte offset OFFSET

ContainerOf
5320core::futureasync_drop_in_placefunction

The pointer _to_drop must be valid for both reads and writes, not only for the duration of this function call, but also until the returned future has completed. See [ptr::drop_in_place] for additional safety concerns.

Valid
5321core::hintassert_uncheckedfunction

cond must be true. It is immediate UB to call this with false.

5322core::hintunreachable_uncheckedfunction

Reaching this function is Undefined Behavior.

As the compiler assumes that all forms of Undefined Behavior can never happen, it will eliminate all branches in the surrounding code that it can determine will invariably lead to a call to unreachable_unchecked().

If the assumptions embedded in using this function turn out to be wrong - that is, if the site which is calling unreachable_unchecked() is actually reachable at runtime - the compiler may have generated nonsensical machine instructions for this situation, including in seemingly unrelated code, causing difficult-to-debug problems.

Use this function sparingly. Consider using the unreachable! macro, which may prevent some optimizations but will safely panic in case it is actually reached at runtime. Benchmark your code to find out if using unreachable_unchecked() comes with a performance benefit.

5323core::i128backward_uncheckedmethod

It is undefined behavior for this operation to overflow the range of values supported by Self. If you cannot guarantee that this will not overflow, use backward or backward_checked instead.

5324core::i128disjoint_bitormethod
5325core::i128forward_uncheckedmethod

It is undefined behavior for this operation to overflow the range of values supported by Self. If you cannot guarantee that this will not overflow, use forward or forward_checked instead.

5326core::i128unchecked_addmethod

This results in undefined behavior when self + rhs > i128::MAX or self + rhs < i128::MIN, i.e. when checked_add would return None.

Unwrap
5327core::i128unchecked_castmethod

This results in undefined behavior if the integer value of self is bigger than T::MAX, or smaller than T::MIN, where T is the target type.

5328core::i128unchecked_cast_frommethod

This results in undefined behavior when value will overflow when converted to this type.

5329core::i128unchecked_div_exactmethod

This results in undefined behavior when rhs == 0, self % rhs != 0, or self == i128::MIN && rhs == -1, i.e. when checked_div_exact(Self::checked_div_exact) would return None.

5330core::i128unchecked_mulmethod

This results in undefined behavior when self rhs > i128::MAX or self rhs < i128::MIN, i.e. when checked_mul would return None.

Unwrap
5331core::i128unchecked_negmethod

This results in undefined behavior when self == i128::MIN, i.e. when checked_neg would return None.

5332core::i128unchecked_shlmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shl would return None.

5333core::i128unchecked_shl_exactmethod

This results in undefined behavior when rhs >= self.leading_zeros() && rhs >= self.leading_ones() i.e. when i128::shl_exact would return None.

5334core::i128unchecked_shrmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shr would return None.

5335core::i128unchecked_shr_exactmethod

This results in undefined behavior when rhs > self.trailing_zeros() || rhs >= i128::BITS i.e. when i128::shr_exact would return None.

5336core::i128unchecked_submethod

This results in undefined behavior when self - rhs > i128::MAX or self - rhs < i128::MIN, i.e. when checked_sub would return None.

Unwrap
5337core::i16backward_uncheckedmethod

It is undefined behavior for this operation to overflow the range of values supported by Self. If you cannot guarantee that this will not overflow, use backward or backward_checked instead.

5338core::i16disjoint_bitormethod
5339core::i16forward_uncheckedmethod

It is undefined behavior for this operation to overflow the range of values supported by Self. If you cannot guarantee that this will not overflow, use forward or forward_checked instead.

5340core::i16unchecked_addmethod

This results in undefined behavior when self + rhs > i16::MAX or self + rhs < i16::MIN, i.e. when checked_add would return None.

Unwrap
5341core::i16unchecked_castmethod

This results in undefined behavior if the integer value of self is bigger than T::MAX, or smaller than T::MIN, where T is the target type.

5342core::i16unchecked_cast_frommethod

This results in undefined behavior when value will overflow when converted to this type.

5343core::i16unchecked_div_exactmethod

This results in undefined behavior when rhs == 0, self % rhs != 0, or self == i16::MIN && rhs == -1, i.e. when checked_div_exact(Self::checked_div_exact) would return None.

5344core::i16unchecked_mulmethod

This results in undefined behavior when self rhs > i16::MAX or self rhs < i16::MIN, i.e. when checked_mul would return None.

Unwrap
5345core::i16unchecked_negmethod

This results in undefined behavior when self == i16::MIN, i.e. when checked_neg would return None.

5346core::i16unchecked_shlmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shl would return None.

5347core::i16unchecked_shl_exactmethod

This results in undefined behavior when rhs >= self.leading_zeros() && rhs >= self.leading_ones() i.e. when i16::shl_exact would return None.

5348core::i16unchecked_shrmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shr would return None.

5349core::i16unchecked_shr_exactmethod

This results in undefined behavior when rhs > self.trailing_zeros() || rhs >= i16::BITS i.e. when i16::shr_exact would return None.

5350core::i16unchecked_submethod

This results in undefined behavior when self - rhs > i16::MAX or self - rhs < i16::MIN, i.e. when checked_sub would return None.

Unwrap
5351core::i32backward_uncheckedmethod

It is undefined behavior for this operation to overflow the range of values supported by Self. If you cannot guarantee that this will not overflow, use backward or backward_checked instead.

5352core::i32disjoint_bitormethod
5353core::i32forward_uncheckedmethod

It is undefined behavior for this operation to overflow the range of values supported by Self. If you cannot guarantee that this will not overflow, use forward or forward_checked instead.

5354core::i32unchecked_addmethod

This results in undefined behavior when self + rhs > i32::MAX or self + rhs < i32::MIN, i.e. when checked_add would return None.

Unwrap
5355core::i32unchecked_castmethod

This results in undefined behavior if the integer value of self is bigger than T::MAX, or smaller than T::MIN, where T is the target type.

5356core::i32unchecked_cast_frommethod

This results in undefined behavior when value will overflow when converted to this type.

5357core::i32unchecked_div_exactmethod

This results in undefined behavior when rhs == 0, self % rhs != 0, or self == i32::MIN && rhs == -1, i.e. when checked_div_exact(Self::checked_div_exact) would return None.

5358core::i32unchecked_mulmethod

This results in undefined behavior when self rhs > i32::MAX or self rhs < i32::MIN, i.e. when checked_mul would return None.

Unwrap
5359core::i32unchecked_negmethod

This results in undefined behavior when self == i32::MIN, i.e. when checked_neg would return None.

5360core::i32unchecked_shlmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shl would return None.

5361core::i32unchecked_shl_exactmethod

This results in undefined behavior when rhs >= self.leading_zeros() && rhs >= self.leading_ones() i.e. when i32::shl_exact would return None.

5362core::i32unchecked_shrmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shr would return None.

5363core::i32unchecked_shr_exactmethod

This results in undefined behavior when rhs > self.trailing_zeros() || rhs >= i32::BITS i.e. when i32::shr_exact would return None.

5364core::i32unchecked_submethod

This results in undefined behavior when self - rhs > i32::MAX or self - rhs < i32::MIN, i.e. when checked_sub would return None.

Unwrap
5365core::i64backward_uncheckedmethod

It is undefined behavior for this operation to overflow the range of values supported by Self. If you cannot guarantee that this will not overflow, use backward or backward_checked instead.

5366core::i64disjoint_bitormethod
5367core::i64forward_uncheckedmethod

It is undefined behavior for this operation to overflow the range of values supported by Self. If you cannot guarantee that this will not overflow, use forward or forward_checked instead.

5368core::i64unchecked_addmethod

This results in undefined behavior when self + rhs > i64::MAX or self + rhs < i64::MIN, i.e. when checked_add would return None.

Unwrap
5369core::i64unchecked_castmethod

This results in undefined behavior if the integer value of self is bigger than T::MAX, or smaller than T::MIN, where T is the target type.

5370core::i64unchecked_cast_frommethod

This results in undefined behavior when value will overflow when converted to this type.

5371core::i64unchecked_div_exactmethod

This results in undefined behavior when rhs == 0, self % rhs != 0, or self == i64::MIN && rhs == -1, i.e. when checked_div_exact(Self::checked_div_exact) would return None.

5372core::i64unchecked_mulmethod

This results in undefined behavior when self rhs > i64::MAX or self rhs < i64::MIN, i.e. when checked_mul would return None.

Unwrap
5373core::i64unchecked_negmethod

This results in undefined behavior when self == i64::MIN, i.e. when checked_neg would return None.

5374core::i64unchecked_shlmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shl would return None.

5375core::i64unchecked_shl_exactmethod

This results in undefined behavior when rhs >= self.leading_zeros() && rhs >= self.leading_ones() i.e. when i64::shl_exact would return None.

5376core::i64unchecked_shrmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shr would return None.

5377core::i64unchecked_shr_exactmethod

This results in undefined behavior when rhs > self.trailing_zeros() || rhs >= i64::BITS i.e. when i64::shr_exact would return None.

5378core::i64unchecked_submethod

This results in undefined behavior when self - rhs > i64::MAX or self - rhs < i64::MIN, i.e. when checked_sub would return None.

Unwrap
5379core::i8backward_uncheckedmethod

It is undefined behavior for this operation to overflow the range of values supported by Self. If you cannot guarantee that this will not overflow, use backward or backward_checked instead.

5380core::i8disjoint_bitormethod
5381core::i8forward_uncheckedmethod

It is undefined behavior for this operation to overflow the range of values supported by Self. If you cannot guarantee that this will not overflow, use forward or forward_checked instead.

5382core::i8unchecked_addmethod

This results in undefined behavior when self + rhs > i8::MAX or self + rhs < i8::MIN, i.e. when checked_add would return None.

Unwrap
5383core::i8unchecked_castmethod

This results in undefined behavior if the integer value of self is bigger than T::MAX, or smaller than T::MIN, where T is the target type.

5384core::i8unchecked_cast_frommethod

This results in undefined behavior when value will overflow when converted to this type.

5385core::i8unchecked_div_exactmethod

This results in undefined behavior when rhs == 0, self % rhs != 0, or self == i8::MIN && rhs == -1, i.e. when checked_div_exact(Self::checked_div_exact) would return None.

5386core::i8unchecked_mulmethod

This results in undefined behavior when self rhs > i8::MAX or self rhs < i8::MIN, i.e. when checked_mul would return None.

Unwrap
5387core::i8unchecked_negmethod

This results in undefined behavior when self == i8::MIN, i.e. when checked_neg would return None.

5388core::i8unchecked_shlmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shl would return None.

5389core::i8unchecked_shl_exactmethod

This results in undefined behavior when rhs >= self.leading_zeros() && rhs >= self.leading_ones() i.e. when i8::shl_exact would return None.

5390core::i8unchecked_shrmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shr would return None.

5391core::i8unchecked_shr_exactmethod

This results in undefined behavior when rhs > self.trailing_zeros() || rhs >= i8::BITS i.e. when i8::shr_exact would return None.

5392core::i8unchecked_submethod

This results in undefined behavior when self - rhs > i8::MAX or self - rhs < i8::MIN, i.e. when checked_sub would return None.

Unwrap
5393core::index::Clampget_uncheckedmethod

Calling this method with an out-of-bounds index or a dangling slice pointer is [undefined behavior] even if the resulting pointer is not used.

5394core::index::Clampget_unchecked_mutmethod

Calling this method with an out-of-bounds index or a dangling slice pointer is [undefined behavior] even if the resulting pointer is not used.

5395core::index::Lastget_uncheckedmethod

Calling this method with an out-of-bounds index or a dangling slice pointer is [undefined behavior] even if the resulting pointer is not used.

5396core::index::Lastget_unchecked_mutmethod

Calling this method with an out-of-bounds index or a dangling slice pointer is [undefined behavior] even if the resulting pointer is not used.

5397core::intrinsicsalign_of_valfunction

See crate::mem::align_of_val_raw for safety conditions.

5398core::intrinsicsarith_offsetfunction

Unlike the offset intrinsic, this intrinsic does not restrict the resulting pointer to point into or at the end of an allocated object, and it wraps with two's complement arithmetic. The resulting value is not necessarily valid to be used to actually access memory.

The stabilized version of this intrinsic is pointer::wrapping_offset.

Allocated
5399core::intrinsicsassumefunction
5400core::intrinsicsatomic_andfunction
5401core::intrinsicsatomic_cxchgfunction
5402core::intrinsicsatomic_cxchgweakfunction
5403core::intrinsicsatomic_fencefunction
5404core::intrinsicsatomic_loadfunction
5405core::intrinsicsatomic_maxfunction
5406core::intrinsicsatomic_minfunction
5407core::intrinsicsatomic_nandfunction
5408core::intrinsicsatomic_orfunction
5409core::intrinsicsatomic_singlethreadfencefunction
5410core::intrinsicsatomic_storefunction
5411core::intrinsicsatomic_umaxfunction
5412core::intrinsicsatomic_uminfunction
5413core::intrinsicsatomic_xaddfunction
5414core::intrinsicsatomic_xchgfunction
5415core::intrinsicsatomic_xorfunction
5416core::intrinsicsatomic_xsubfunction
5417core::intrinsicscatch_unwindfunction
5418core::intrinsicscompare_bytesfunction

left and right must each be [valid] for reads of bytes bytes.

Note that this applies to the whole range, not just until the first byte that differs. That allows optimizations that can read in large chunks.

5419core::intrinsicsconst_allocatefunction
  • The align argument must be a power of two.
  • At compile time, a compile error occurs if this constraint is violated.
  • At runtime, it is not checked.
5420core::intrinsicsconst_deallocatefunction
  • The align argument must be a power of two.
  • At compile time, a compile error occurs if this constraint is violated.
  • At runtime, it is not checked.
  • If the ptr is created in an another const, this intrinsic doesn't deallocate it.
  • If the ptr is pointing to a local variable, this intrinsic doesn't deallocate it.
5421core::intrinsicsconst_make_globalfunction
5422core::intrinsicscopyfunction
5423core::intrinsicscopy_nonoverlappingfunction
5424core::intrinsicsctlz_nonzerofunction
5425core::intrinsicscttz_nonzerofunction
5426core::intrinsicsdisjoint_bitorfunction

Requires that (a & b) == 0, or equivalently that (a | b) == (a + b).

Otherwise it's immediate UB.

5427core::intrinsicsexact_divfunction
5428core::intrinsicsfadd_fastfunction
5429core::intrinsicsfdiv_fastfunction
5430core::intrinsicsfloat_to_int_uncheckedfunction
5431core::intrinsicsfmul_fastfunction
5432core::intrinsicsfrem_fastfunction
5433core::intrinsicsfsub_fastfunction
5434core::intrinsicsnontemporal_storefunction
5435core::intrinsicsoffsetfunction

If the computed offset is non-zero, then both the starting and resulting pointer must be either in bounds or at the end of an allocation. If either pointer is out of bounds or arithmetic overflow occurs then this operation is undefined behavior.

The stabilized version of this intrinsic is pointer::offset.

InBound, NonZero
5436core::intrinsicsptr_offset_fromfunction
5437core::intrinsicsptr_offset_from_unsignedfunction
5438core::intrinsicsraw_eqfunction

It's UB to call this if any of the bytes in a or b are uninitialized. Note that this is a stricter criterion than just the values being fully-initialized: if T has padding, it's UB to call this intrinsic.

At compile-time, it is furthermore UB to call this if any of the bytes in a or b have provenance.

(The implementation is allowed to branch on the results of comparisons, which is UB if any of their inputs are undef.)

5439core::intrinsicsread_via_copyfunction
5440core::intrinsicssize_of_valfunction

See crate::mem::size_of_val_raw for safety conditions.

5441core::intrinsicsslice_get_uncheckedfunction
  • index < PtrMetadata(slice_ptr), so the indexing is in-bounds for the slice
  • the resulting offsetting is in-bounds of the allocation, which is always the case for references, but needs to be upheld manually for pointers
5442core::intrinsicstransmute_uncheckedfunction
5443core::intrinsicstyped_swap_nonoverlappingfunction

Behavior is undefined if any of the following conditions are violated:

  • Both x and y must be [valid] for both reads and writes.
  • Both x and y must be properly aligned.
  • The region of memory beginning at x must not overlap with the region of memory beginning at y.
  • The memory pointed by x and y must both contain values of type T.
Align
5444core::intrinsicsunaligned_volatile_loadfunction
5445core::intrinsicsunaligned_volatile_storefunction
5446core::intrinsicsunchecked_addfunction
5447core::intrinsicsunchecked_divfunction
5448core::intrinsicsunchecked_funnel_shlfunction
5449core::intrinsicsunchecked_funnel_shrfunction
5450core::intrinsicsunchecked_mulfunction
5451core::intrinsicsunchecked_remfunction
5452core::intrinsicsunchecked_shlfunction
5453core::intrinsicsunchecked_shrfunction
5454core::intrinsicsunchecked_subfunction
5455core::intrinsicsunreachablefunction
5456core::intrinsicsva_argfunction

This function is only sound to call when:

  • there is a next variable argument available.
  • the next argument's type must be ABI-compatible with the type T.
  • the next argument must have a properly initialized value of type T.

Calling this function with an incompatible type, an invalid value, or when there are no more variable arguments, is unsound.

Init
5457core::intrinsicsva_endfunction

ap must not be used to access variable arguments after this call.

5458core::intrinsicsvolatile_copy_memoryfunction
5459core::intrinsicsvolatile_copy_nonoverlapping_memoryfunction

The safety requirements are consistent with copy_nonoverlapping while the read and write behaviors are volatile, which means it will not be optimized out unless _count or size_of::<T>() is equal to zero.

NonVolatile
5460core::intrinsicsvolatile_loadfunction
5461core::intrinsicsvolatile_set_memoryfunction

The safety requirements are consistent with write_bytes while the write behavior is volatile, which means it will not be optimized out unless _count or size_of::<T>() is equal to zero.

NonVolatile
5462core::intrinsicsvolatile_storefunction
5463core::intrinsicsvtable_alignfunction

ptr must point to a vtable.

5464core::intrinsicsvtable_sizefunction

ptr must point to a vtable.

5465core::intrinsicswrite_bytesfunction
5466core::intrinsicswrite_via_movefunction
5467core::intrinsics::boundsBuiltinDereftrait

Must actually be such a type.

5468core::intrinsics::boundsFloatPrimitivetrait

Must actually be such a type.

5469core::intrinsics::fallback::DisjointBitOrdisjoint_bitortrait_method
5470core::intrinsics::fallback::FunnelShiftunchecked_funnel_shltrait_method
5471core::intrinsics::fallback::FunnelShiftunchecked_funnel_shrtrait_method
5472core::intrinsics::simdsimd_addfunction
5473core::intrinsics::simdsimd_andfunction
5474core::intrinsics::simdsimd_arith_offsetfunction
5475core::intrinsics::simdsimd_asfunction
5476core::intrinsics::simdsimd_bitmaskfunction

x must contain only 0 and !0.

5477core::intrinsics::simdsimd_bitreversefunction
5478core::intrinsics::simdsimd_bswapfunction
5479core::intrinsics::simdsimd_carryless_mulfunction
5480core::intrinsics::simdsimd_castfunction

Casting from integer types is always safe. Casting between two float types is also always safe.

Casting floats to integers truncates, following the same rules as to_int_unchecked. Specifically, each element must: Not be NaN Not be infinite * Be representable in the return type, after truncating off its fractional part

5481core::intrinsics::simdsimd_cast_ptrfunction
5482core::intrinsics::simdsimd_ceilfunction
5483core::intrinsics::simdsimd_ctlzfunction
5484core::intrinsics::simdsimd_ctpopfunction
5485core::intrinsics::simdsimd_cttzfunction
5486core::intrinsics::simdsimd_divfunction

For integers, rhs must not contain any zero elements. Additionally for signed integers, <int>::MIN / -1 is undefined behavior.

5487core::intrinsics::simdsimd_eqfunction
5488core::intrinsics::simdsimd_expose_provenancefunction
5489core::intrinsics::simdsimd_extractfunction

idx must be const and in-bounds of the vector.

5490core::intrinsics::simdsimd_extract_dynfunction

idx must be in-bounds of the vector.

5491core::intrinsics::simdsimd_fabsfunction
5492core::intrinsics::simdsimd_fcosfunction
5493core::intrinsics::simdsimd_fexpfunction
5494core::intrinsics::simdsimd_fexp2function
5495core::intrinsics::simdsimd_flogfunction
5496core::intrinsics::simdsimd_flog10function
5497core::intrinsics::simdsimd_flog2function
5498core::intrinsics::simdsimd_floorfunction
5499core::intrinsics::simdsimd_fmafunction
5500core::intrinsics::simdsimd_fsinfunction
5501core::intrinsics::simdsimd_fsqrtfunction
5502core::intrinsics::simdsimd_funnel_shlfunction

Each element of shift must be in 0..<int>::BITS.

5503core::intrinsics::simdsimd_funnel_shrfunction

Each element of shift must be in 0..<int>::BITS.

5504core::intrinsics::simdsimd_gatherfunction

Each pointer in ptr whose corresponding value in mask is !0 must be readable as if by ptr::read[crate::ptr::read] (e.g. aligned to the element type).

mask must only contain 0 or !0 values.

Align, ValidRead
5505core::intrinsics::simdsimd_gefunction
5506core::intrinsics::simdsimd_gtfunction
5507core::intrinsics::simdsimd_insertfunction

idx must be in-bounds of the vector.

5508core::intrinsics::simdsimd_insert_dynfunction

idx must be in-bounds of the vector.

5509core::intrinsics::simdsimd_lefunction
5510core::intrinsics::simdsimd_ltfunction
5511core::intrinsics::simdsimd_masked_loadfunction

ptr must be aligned according to the ALIGN parameter, see SimdAlign for details.

Each pointer offset from ptr whose corresponding value in mask is !0 must be readable as if by ptr::read[crate::ptr::read].

mask must only contain 0 or !0 values.

Align, ValidRead
5512core::intrinsics::simdsimd_masked_storefunction

ptr must be aligned according to the ALIGN parameter, see SimdAlign for details.

Each pointer offset from ptr whose corresponding value in mask is !0 must be writable as if by ptr::write[crate::ptr::write].

mask must only contain 0 or !0 values.

Align, ValidWrite
5513core::intrinsics::simdsimd_maximum_number_nszfunction
5514core::intrinsics::simdsimd_minimum_number_nszfunction
5515core::intrinsics::simdsimd_mulfunction
5516core::intrinsics::simdsimd_nefunction
5517core::intrinsics::simdsimd_negfunction
5518core::intrinsics::simdsimd_orfunction
5519core::intrinsics::simdsimd_reduce_add_orderedfunction
5520core::intrinsics::simdsimd_reduce_add_unorderedfunction
5521core::intrinsics::simdsimd_reduce_allfunction

x must contain only 0 or !0.

5522core::intrinsics::simdsimd_reduce_andfunction
5523core::intrinsics::simdsimd_reduce_anyfunction

x must contain only 0 or !0.

5524core::intrinsics::simdsimd_reduce_maxfunction
5525core::intrinsics::simdsimd_reduce_minfunction
5526core::intrinsics::simdsimd_reduce_mul_orderedfunction
5527core::intrinsics::simdsimd_reduce_mul_unorderedfunction
5528core::intrinsics::simdsimd_reduce_orfunction
5529core::intrinsics::simdsimd_reduce_xorfunction
5530core::intrinsics::simdsimd_relaxed_fmafunction
5531core::intrinsics::simdsimd_remfunction

For integers, rhs must not contain any zero elements. Additionally for signed integers, <int>::MIN / -1 is undefined behavior.

5532core::intrinsics::simdsimd_roundfunction
5533core::intrinsics::simdsimd_round_ties_evenfunction
5534core::intrinsics::simdsimd_saturating_addfunction
5535core::intrinsics::simdsimd_saturating_subfunction
5536core::intrinsics::simdsimd_scatterfunction

Each pointer in ptr whose corresponding value in mask is !0 must be writable as if by ptr::write[crate::ptr::write] (e.g. aligned to the element type).

mask must only contain 0 or !0 values.

Align, ValidWrite
5537core::intrinsics::simdsimd_selectfunction

mask must only contain 0 and !0.

5538core::intrinsics::simdsimd_select_bitmaskfunction
5539core::intrinsics::simdsimd_shlfunction

Each element of rhs must be in 0..<int>::BITS.

5540core::intrinsics::simdsimd_shrfunction

Each element of rhs must be in 0..<int>::BITS.

5541core::intrinsics::simdsimd_shufflefunction
5542core::intrinsics::simdsimd_splatfunction
5543core::intrinsics::simdsimd_subfunction
5544core::intrinsics::simdsimd_truncfunction
5545core::intrinsics::simdsimd_with_exposed_provenancefunction
5546core::intrinsics::simdsimd_xorfunction
5547core::intrinsics::simd::scalablesve_tuple_create2function
5548core::intrinsics::simd::scalablesve_tuple_create3function
5549core::intrinsics::simd::scalablesve_tuple_create4function
5550core::intrinsics::simd::scalablesve_tuple_getfunction

IDX must be in-bounds of the tuple.

5551core::intrinsics::simd::scalablesve_tuple_setfunction

IDX must be in-bounds of the tuple.

5552core::io::borrowed_buf::BorrowedBufset_initmethod

All the elements of the buffer must be initialized.

Init
5553core::io::borrowed_buf::BorrowedCursoradvancemethod

The caller must ensure that the first n elements of the cursor have been initialized.

Init
5554core::io::borrowed_buf::BorrowedCursoras_mutmethod

The caller must not uninitialize any elements of the cursor if it is initialized.

5555core::io::borrowed_buf::BorrowedCursorset_initmethod

All the elements of the cursor must be initialized.

Init
5556core::isizebackward_uncheckedmethod

It is undefined behavior for this operation to overflow the range of values supported by Self. If you cannot guarantee that this will not overflow, use backward or backward_checked instead.

5557core::isizedisjoint_bitormethod
5558core::isizeforward_uncheckedmethod

It is undefined behavior for this operation to overflow the range of values supported by Self. If you cannot guarantee that this will not overflow, use forward or forward_checked instead.

5559core::isizeunchecked_addmethod

This results in undefined behavior when self + rhs > isize::MAX or self + rhs < isize::MIN, i.e. when checked_add would return None.

Unwrap
5560core::isizeunchecked_castmethod

This results in undefined behavior if the integer value of self is bigger than T::MAX, or smaller than T::MIN, where T is the target type.

5561core::isizeunchecked_cast_frommethod

This results in undefined behavior when value will overflow when converted to this type.

5562core::isizeunchecked_div_exactmethod

This results in undefined behavior when rhs == 0, self % rhs != 0, or self == isize::MIN && rhs == -1, i.e. when checked_div_exact(Self::checked_div_exact) would return None.

5563core::isizeunchecked_mulmethod

This results in undefined behavior when self rhs > isize::MAX or self rhs < isize::MIN, i.e. when checked_mul would return None.

Unwrap
5564core::isizeunchecked_negmethod

This results in undefined behavior when self == isize::MIN, i.e. when checked_neg would return None.

5565core::isizeunchecked_shlmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shl would return None.

5566core::isizeunchecked_shl_exactmethod

This results in undefined behavior when rhs >= self.leading_zeros() && rhs >= self.leading_ones() i.e. when isize::shl_exact would return None.

5567core::isizeunchecked_shrmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shr would return None.

5568core::isizeunchecked_shr_exactmethod

This results in undefined behavior when rhs > self.trailing_zeros() || rhs >= isize::BITS i.e. when isize::shr_exact would return None.

5569core::isizeunchecked_submethod

This results in undefined behavior when self - rhs > isize::MAX or self - rhs < isize::MIN, i.e. when checked_sub would return None.

Unwrap
5570core::iterTrustedLentrait

This trait must only be implemented when the contract is upheld. Consumers of this trait must inspect Iterator::size_hint()’s upper bound.

5571core::iterTrustedSteptrait

The implementation of Step for the given type must guarantee all invariants of all methods are upheld. See the Step trait's documentation for details. Consumers are free to rely on the invariants in unsafe code.

5572core::iter::range::Stepbackward_uncheckedtrait_method

It is undefined behavior for this operation to overflow the range of values supported by Self. If you cannot guarantee that this will not overflow, use backward or backward_checked instead.

5573core::iter::range::Stepforward_uncheckedtrait_method

It is undefined behavior for this operation to overflow the range of values supported by Self. If you cannot guarantee that this will not overflow, use forward or forward_checked instead.

5574core::markerFreezetrait

This trait is a core part of the language, it is just expressed as a trait in libcore for convenience. Do not implement it for other types.

5575core::markerUnsafeUnpintrait
5576core::memTransmuteFromtrait

If Dst: TransmuteFrom<Src, ASSUMPTIONS>, the compiler guarantees that Src is soundly union-transmutable into a value of type Dst, provided that the programmer has guaranteed that the given ASSUMPTIONS(Assume) are satisfied.

A union-transmute is any bit-reinterpretation conversion in the form of:

```rust pub unsafe fn transmute_via_union<Src, Dst>(src: Src) -> Dst { use core::mem::ManuallyDrop;

#[repr(C)] union Transmute<Src, Dst> { src: ManuallyDrop<Src>, dst: ManuallyDrop<Dst>, }

let transmute = Transmute { src: ManuallyDrop::new(src), };

let dst = unsafe { transmute.dst };

ManuallyDrop::into_inner(dst) } ```

Note that this construction is more permissive than mem::transmute_copy(super::transmute_copy); union-transmutes permit conversions that extend the bits of Src with trailing padding to fill trailing uninitialized bytes of Self; e.g.:

```rust #![feature(transmutability)]

use core::mem::{Assume, TransmuteFrom};

let src = 42u8; // size = 1

#[repr(C, align(2))] struct Dst(u8); // size = 2 let _ = unsafe { <Dst as TransmuteFrom<u8, { Assume::SAFETY }>>::transmute(src) }; ```

5577core::memalign_of_val_rawfunction

This function is safe to call if the pointer is safe to reborrow as &T (in which case you could also call align_of_val). Otherwise, the following conditions must hold:

  • If T is Sized, this function is always safe to call.
  • If the unsized tail of T is:
  • a [slice] [U], str, or a [trait object] dyn Trait, then the size of the entire value (dynamic tail length + statically sized prefix) must fit in isize. For the special case where the dynamic tail length is 0, this function is safe to call.
  • No other kind of unsized tail currently exists that satisfies the trait bounds for this function. If more kinds of unsized tails get introduced in the future, the documentation of this function will have to be extended before it can be used for such types.

Here, unsized tail refers to the type obtained by recursively descending through the last field of a tuple or struct until we arrived at a built-in unsized type.

As a consequence of these rules, it is the case that whenever it is allowed to convert val into a shared reference, then it is also allowed to invoke this function.

5578core::memconjure_zstfunction
  • T must be [inhabited], i.e. possible to construct. This means that types like zero-variant enums and ! are unsound to conjure.
  • You must use the value only in ways which do not violate any safety invariants of the type.

While it's easy to create a valid instance of an inhabited ZST, since having no bits in its representation means there's only one possible value, that doesn't mean that it's always sound to do so.

For example, a library could design zero-sized tokens that are !Default + !Clone, limiting their creation to functions that initialize some state or establish a scope. Conjuring such a token could break invariants and lead to unsoundness.

5579core::memsize_of_val_rawfunction

This function is safe to call if the pointer is safe to reborrow as &T (in which case you could also call size_of_val). Otherwise, the following conditions must hold:

  • If T is Sized, this function is always safe to call.
  • If the unsized tail of T is:
  • a [slice] [U], str, or a [trait object] dyn Trait, then the size of the entire value (dynamic tail length + statically sized prefix) must fit in isize. For the special case where the dynamic tail length is 0, this function is safe to call.
  • No other kind of unsized tail currently exists that satisfies the trait bounds for this function. If more kinds of unsized tails get introduced in the future, the documentation of this function will have to be extended before it can be used for such types.

Here, unsized tail refers to the type obtained by recursively descending through the last field of a tuple or struct until we arrived at a built-in unsized type.

As a consequence of these rules, it is the case that whenever it is allowed to convert val into a shared reference, then it is also allowed to invoke this function.

5580core::memtransmutefunction

The safety obligations of the caller depend on the value of ASSUME: - If ASSUME.alignment(Assume::alignment), the caller must guarantee that the addresses of references in the returned Self satisfy the alignment requirements of their referent types. - If ASSUME.lifetimes(Assume::lifetimes), the caller must guarantee that references in the returned Self will not outlive their referents. - If ASSUME.safety(Assume::safety), the returned value might not satisfy the library safety invariants of Self, and the caller must guarantee that undefined behavior does not arise from uses of the returned value. - If ASSUME.validity(Assume::validity), the caller must guarantee that src is a bit-valid instance of Self.

When satisfying the above obligations (if any), the caller must not assume that this trait provides any inherent guarantee of layout portability or stability.

Align
5581core::memtransmute_copyfunction
  • Requires size_of_val::<Src>(src) >= size_of::<Dst>()
  • The first size_of::<Dst>() bytes behind src must be readable
  • The first size_of::<Dst>() bytes behind src must be [valid] when interpreted as a Dst.

On top of that, remember that most types have additional invariants beyond merely being considered initialized at the type level. For example, a 1-initialized Vec<T> is considered initialized (under the current implementation; this does not constitute a stable guarantee) because the only requirement the compiler knows about it is that the data pointer must be non-null. Creating such a Vec<T> does not cause immediate undefined behavior, but will cause undefined behavior with most safe operations (including dropping it).

NonNull
5582core::memtransmute_neofunction
5583core::memtransmute_prefixfunction

If size_of::<Src>() >= size_of::<Dst>(), the first size_of::<Dst>() bytes of src must be be valid when interpreted as a Dst. (In this case, the preconditions are the same as for transmute_copy(&ManuallyDrop::new(src)).)

If size_of::<Src>() <= size_of::<Dst>(), the bytes of src padded with uninitialized bytes afterwards up to a total size of size_of::<Dst>() must be valid when interpreted as a Dst.

In both cases, any safety preconditions of the Dst type must also be upheld.

5584core::memuninitializedfunction
5585core::memzeroedfunction
5586core::mem::alignment::Alignmentnew_uncheckedmethod

align must be a power of two.

Equivalently, it must be 1 << exp for some exp in 0..usize::BITS. It must not be zero.

5587core::mem::alignment::Alignmentof_val_rawmethod

This function is safe to call if the pointer is safe to reborrow as &T (in which case you could also call of_val[Self::of_val]). Otherwise, the following conditions must hold:

  • If T is Sized, this function is always safe to call.
  • If the unsized tail of T is:
  • a [slice], then the length of the slice tail must be an initialized integer, and the size of the entire value (dynamic tail length + statically sized prefix) must fit in isize. For the special case where the dynamic tail length is 0, this function is safe to call.
  • a [trait object], then the vtable part of the pointer must point to a valid vtable acquired by an unsizing coercion, and the size of the entire value (dynamic tail length + statically sized prefix) must fit in isize.
  • an (unstable) [extern type], then this function is always safe to call, but may panic or otherwise return the wrong value, as the extern type's layout is not known. This is the same behavior as Alignment::of_val on a reference to a type with an extern type tail.
  • otherwise, it is conservatively not allowed to call this function.
Valid
5588core::mem::manually_drop::ManuallyDropdropmethod

This function runs the destructor of the contained value. Other than changes made by the destructor itself, the memory is left unchanged, and so as far as the compiler is concerned still holds a bit-pattern which is valid for the type T.

However, this "zombie" value should not be exposed to safe code, and this function should not be called more than once. To use a value after it's been dropped, or drop a value multiple times, can cause Undefined Behavior (depending on what drop does). This is normally prevented by the type system, but users of ManuallyDrop must uphold those guarantees without assistance from the compiler.

Invariant
5589core::mem::manually_drop::ManuallyDroptakemethod

This function semantically moves out the contained value without preventing further usage, leaving the state of this container unchanged. It is your responsibility to ensure that this ManuallyDrop is not used again.

5590core::mem::maybe_uninit::MaybeUninitarray_assume_initmethod

It is up to the caller to guarantee that all elements of the array are in an initialized state.

Init
5591core::mem::maybe_uninit::MaybeUninitassume_initmethod

It is up to the caller to guarantee that the MaybeUninit<T> really is in an initialized state, i.e., a state that is considered ["valid" for type T][validity]. Calling this when the content is not yet fully initialized causes immediate undefined behavior. The [type-level documentation][inv] contains more information about this initialization invariant.

It is a common mistake to assume that this function is safe to call on integers because they can hold all bit patterns. It is also a common mistake to think that calling this function is UB if any byte is uninitialized. Both of these assumptions are wrong. If that is surprising to you, please read the [type-level documentation][inv].

On top of that, remember that most types have additional invariants beyond merely being considered initialized at the type level. For example, a 1-initialized Vec<T> is considered initialized (under the current implementation; this does not constitute a stable guarantee) because the only requirement the compiler knows about it is that the data pointer must be non-null. Creating such a Vec<T> does not cause immediate undefined behavior, but will cause undefined behavior with most safe operations (including dropping it).

NonNull, Init
5592core::mem::maybe_uninit::MaybeUninitassume_init_dropmethod

It is up to the caller to guarantee that the MaybeUninit<T> really is in an initialized state. Calling this when the content is not yet fully initialized causes undefined behavior.

On top of that, all additional invariants of the type T must be satisfied, as the Drop implementation of T (or its members) may rely on this. For example, setting a Vec<T> to an invalid but non-null address makes it initialized (under the current implementation; this does not constitute a stable guarantee), because the only requirement the compiler knows about it is that the data pointer must be non-null. Dropping such a Vec<T> however will cause undefined behavior.

NonNull, Init
5593core::mem::maybe_uninit::MaybeUninitassume_init_mutmethod

Calling this when the content is not yet fully initialized causes undefined behavior: it is up to the caller to guarantee that the MaybeUninit<T> really is in an initialized state. For instance, .assume_init_mut() cannot be used to initialize a MaybeUninit.

Init
5594core::mem::maybe_uninit::MaybeUninitassume_init_readmethod

It is up to the caller to guarantee that the MaybeUninit<T> really is in an initialized state. Calling this when the content is not yet fully initialized causes undefined behavior. The [type-level documentation][inv] contains more information about this initialization invariant.

Moreover, similar to the ptr::read function, this function creates a bitwise copy of the contents, regardless whether the contained type implements the Copy trait or not. When using multiple copies of the data (by calling assume_init_read multiple times, or first calling assume_init_read and then assume_init), it is your responsibility to ensure that data may indeed be duplicated.

Init
5595core::mem::maybe_uninit::MaybeUninitassume_init_refmethod

Calling this when the content is not yet fully initialized causes undefined behavior: it is up to the caller to guarantee that the MaybeUninit<T> really is in an initialized state.

Init
5596core::mem::transmutability::TransmuteFromtransmutetrait_method

The safety obligations of the caller depend on the value of ASSUME: - If ASSUME.alignment(Assume::alignment), the caller must guarantee that the addresses of references in the returned Self satisfy the alignment requirements of their referent types. - If ASSUME.lifetimes(Assume::lifetimes), the caller must guarantee that references in the returned Self will not outlive their referents. - If ASSUME.safety(Assume::safety), the returned value might not satisfy the library safety invariants of Self, and the caller must guarantee that undefined behavior does not arise from uses of the returned value. - If ASSUME.validity(Assume::validity), the caller must guarantee that src is a bit-valid instance of Self.

When satisfying the above obligations (if any), the caller must not assume that this trait provides any inherent guarantee of layout portability or stability.

Align
5597core::net::ip_addr::Ipv4Addrbackward_uncheckedmethod

It is undefined behavior for this operation to overflow the range of values supported by Self. If you cannot guarantee that this will not overflow, use backward or backward_checked instead.

5598core::net::ip_addr::Ipv4Addrforward_uncheckedmethod

It is undefined behavior for this operation to overflow the range of values supported by Self. If you cannot guarantee that this will not overflow, use forward or forward_checked instead.

5599core::net::ip_addr::Ipv6Addrbackward_uncheckedmethod

It is undefined behavior for this operation to overflow the range of values supported by Self. If you cannot guarantee that this will not overflow, use backward or backward_checked instead.

5600core::net::ip_addr::Ipv6Addrforward_uncheckedmethod

It is undefined behavior for this operation to overflow the range of values supported by Self. If you cannot guarantee that this will not overflow, use forward or forward_checked instead.

5601core::numZeroablePrimitivetrait

Types implementing this trait must be primitives that are valid when zeroed.

The associated Self::NonZeroInner type must have the same size+align as Self, but with a niche and bit validity making it so the following transmutes are sound:

  • Self::NonZeroInner to Option<Self::NonZeroInner>
  • Option<Self::NonZeroInner> to Self

(And, consequently, Self::NonZeroInner to Self.)

NonZero
5602core::num::nonzero::NonZerobackward_uncheckedmethod

It is undefined behavior for this operation to overflow the range of values supported by Self. If you cannot guarantee that this will not overflow, use backward or backward_checked instead.

5603core::num::nonzero::NonZeroforward_uncheckedmethod

It is undefined behavior for this operation to overflow the range of values supported by Self. If you cannot guarantee that this will not overflow, use forward or forward_checked instead.

5604core::num::nonzero::NonZerofrom_mut_uncheckedmethod

The referenced value must not be zero.

NonZero
5605core::num::nonzero::NonZeronew_uncheckedmethod

The value must not be zero.

NonZero
5606core::num::nonzero::NonZerounchecked_addmethod

This results in undefined behavior when self + rhs > u8::MAX.


This results in undefined behavior when self + rhs > usize::MAX.


This results in undefined behavior when self + rhs > u128::MAX.


This results in undefined behavior when self + rhs > u64::MAX.


This results in undefined behavior when self + rhs > u32::MAX.


This results in undefined behavior when self + rhs > u16::MAX.

5607core::num::nonzero::NonZerounchecked_mulmethod

This results in undefined behavior when self * rhs > usize::MAX.


This results in undefined behavior when self rhs > i128::MAX, or self rhs < i128::MIN.


This results in undefined behavior when self * rhs > u128::MAX.


This results in undefined behavior when self * rhs > u64::MAX.


This results in undefined behavior when self * rhs > u32::MAX.


This results in undefined behavior when self rhs > i16::MAX, or self rhs < i16::MIN.


This results in undefined behavior when self * rhs > u16::MAX.


This results in undefined behavior when self * rhs > u8::MAX.


This results in undefined behavior when self rhs > i64::MAX, or self rhs < i64::MIN.


This results in undefined behavior when self rhs > i8::MAX, or self rhs < i8::MIN.


This results in undefined behavior when self rhs > isize::MAX, or self rhs < isize::MIN.


This results in undefined behavior when self rhs > i32::MAX, or self rhs < i32::MIN.

5608core::opsDerefPuretrait
5609core::ops::range::Boundget_uncheckedmethod

Calling this method with an out-of-bounds index or a dangling slice pointer is [undefined behavior] even if the resulting pointer is not used.

5610core::ops::range::Boundget_unchecked_mutmethod

Calling this method with an out-of-bounds index or a dangling slice pointer is [undefined behavior] even if the resulting pointer is not used.

5611core::ops::range::Rangeget_uncheckedmethod

Calling this method with an out-of-bounds index or a dangling slice pointer is [undefined behavior] even if the resulting pointer is not used.

5612core::ops::range::Rangeget_unchecked_mutmethod

Calling this method with an out-of-bounds index or a dangling slice pointer is [undefined behavior] even if the resulting pointer is not used.

5613core::ops::range::RangeFromget_uncheckedmethod

Calling this method with an out-of-bounds index or a dangling slice pointer is [undefined behavior] even if the resulting pointer is not used.

5614core::ops::range::RangeFromget_unchecked_mutmethod

Calling this method with an out-of-bounds index or a dangling slice pointer is [undefined behavior] even if the resulting pointer is not used.

5615core::ops::range::RangeFullget_uncheckedmethod

Calling this method with an out-of-bounds index or a dangling slice pointer is [undefined behavior] even if the resulting pointer is not used.

5616core::ops::range::RangeFullget_unchecked_mutmethod

Calling this method with an out-of-bounds index or a dangling slice pointer is [undefined behavior] even if the resulting pointer is not used.

5617core::ops::range::RangeInclusiveget_uncheckedmethod

Calling this method with an out-of-bounds index or a dangling slice pointer is [undefined behavior] even if the resulting pointer is not used.

5618core::ops::range::RangeInclusiveget_unchecked_mutmethod

Calling this method with an out-of-bounds index or a dangling slice pointer is [undefined behavior] even if the resulting pointer is not used.

5619core::ops::range::RangeToget_uncheckedmethod

Calling this method with an out-of-bounds index or a dangling slice pointer is [undefined behavior] even if the resulting pointer is not used.

5620core::ops::range::RangeToget_unchecked_mutmethod

Calling this method with an out-of-bounds index or a dangling slice pointer is [undefined behavior] even if the resulting pointer is not used.

5621core::ops::range::RangeToInclusiveget_uncheckedmethod

Calling this method with an out-of-bounds index or a dangling slice pointer is [undefined behavior] even if the resulting pointer is not used.

5622core::ops::range::RangeToInclusiveget_unchecked_mutmethod

Calling this method with an out-of-bounds index or a dangling slice pointer is [undefined behavior] even if the resulting pointer is not used.

5623core::option::Optionunwrap_uncheckedmethod

Calling this method on None is [undefined behavior].

5624core::pinPinCoerceUnsizedtrait

Given a pointer of this type, the concrete type returned by its deref method and (if it implements DerefMut) its deref_mut method must be the same type and must not change without a modification. The following operations are not considered modifications:

  • Moving the pointer.
  • Performing unsizing coercions on the pointer.
  • Performing dynamic dispatch with the pointer.
  • Calling deref or deref_mut on the pointer.

The concrete type of a trait object is the type that the vtable corresponds to. The concrete type of a slice is an array of the same element type and the length specified in the metadata. The concrete type of a sized type is the type itself.

Typed
5625core::pin::Pinget_unchecked_mutmethod

This function is unsafe. You must guarantee that you will never move the data out of the mutable reference you receive when you call this function, so that the invariants on the Pin type can be upheld.

If the underlying data is Unpin, Pin::get_mut should be used instead.

5626core::pin::Pininto_inner_uncheckedmethod

This function is unsafe. You must guarantee that you will continue to treat the pointer Ptr as pinned after you call this function, so that the invariants on the Pin type can be upheld. If the code using the resulting Ptr does not continue to maintain the pinning invariants that is a violation of the API contract and may lead to undefined behavior in later (safe) operations.

Note that you must be able to guarantee that the data pointed to by Ptr will be treated as pinned all the way until its drop handler is complete!

For more information, see the [pin module docs][self]

If the underlying data is Unpin, Pin::into_inner should be used instead.

5627core::pin::Pinmap_uncheckedmethod

This function is unsafe. You must guarantee that the data you return will not move so long as the argument value does not move (for example, because it is one of the fields of that value), and also that you do not move out of the argument you receive to the interior function.

5628core::pin::Pinmap_unchecked_mutmethod

This function is unsafe. You must guarantee that the data you return will not move so long as the argument value does not move (for example, because it is one of the fields of that value), and also that you do not move out of the argument you receive to the interior function.

5629core::pin::Pinnew_uncheckedmethod

This constructor is unsafe because we cannot guarantee that the data pointed to by pointer is pinned. At its core, pinning a value means making the guarantee that the value's data will not be moved nor have its storage invalidated until it gets dropped. For a more thorough explanation of pinning, see the [pin module docs].

If the caller that is constructing this Pin<Ptr> does not ensure that the data Ptr points to is pinned, that is a violation of the API contract and may lead to undefined behavior in later (even safe) operations.

By using this method, you are also making a promise about the Deref, DerefMut, and Drop implementations of Ptr, if they exist. Most importantly, they must not move out of their self arguments: Pin::as_mut and Pin::as_ref will call DerefMut::deref_mut and Deref::deref on the pointer type Ptr and expect these methods to uphold the pinning invariants. Moreover, by calling this method you promise that the reference Ptr dereferences to will not be moved out of again; in particular, it must not be possible to obtain a &mut Ptr::Target and then move out of that reference (using, for example mem::swap).

For example, calling Pin::new_unchecked on an &'a mut T is unsafe because while you are able to pin it for the given lifetime 'a, you have no control over whether it is kept pinned once 'a ends, and therefore cannot uphold the guarantee that a value, once pinned, remains pinned until it is dropped:

``` use std::mem; use std::pin::Pin;

fn move_pinned_ref<T>(mut a: T, mut b: T) { unsafe { let p: Pin<&mut T> = Pin::new_unchecked(&mut a); // This should mean the pointee a can never move again. } mem::swap(&mut a, &mut b); // Potential UB down the road ⚠️ // The address of a changed to b's stack slot, so a got moved even // though we have previously pinned it! We have violated the pinning API contract. } `` A value, once pinned, must remain pinned until it is dropped (unless its type implements Unpin). Because Pin<&mut T> does not own the value, dropping the Pin will not drop the value and will not end the pinning contract. So moving the value after dropping the Pin<&mut T>` is still a violation of the API contract.

Similarly, calling Pin::new_unchecked on an Rc<T> is unsafe because there could be aliases to the same data that are not subject to the pinning restrictions: ``` use std::rc::Rc; use std::pin::Pin;

fn move_pinned_rc<T>(mut x: Rc<T>) { // This should mean the pointee can never move again. let pin = unsafe { Pin::new_unchecked(Rc::clone(&x)) }; { let p: Pin<&T> = pin.as_ref(); // ... } drop(pin);

let content = Rc::get_mut(&mut x).unwrap(); // Potential UB down the road ⚠️ // Now, if x was the only reference, we have a mutable reference to // data that we pinned above, which we could use to move it as we have // seen in the previous example. We have violated the pinning API contract. } ```

Unwrap, Pinned
5630core::pointeraddmethod

If any of the following conditions are violated, the result is Undefined Behavior:

  • The offset in bytes, count * size_of::<T>(), computed on mathematical integers (without "wrapping around"), must fit in an isize.
  • Let result be self.addr() + count * size_of::<T>(), computed on mathematical integers. This must fit in a usize.
  • If the computed offset is non-zero, then self must be [derived from][crate::ptr#provenance] a pointer to some [allocation], and the entire memory range between self and result (i.e., self.addr()..result) must be in bounds of that allocation.

Allocations can never be larger than isize::MAX bytes and they can only contain addresses representable by usize, so technically the last condition implies the first two. This implies, for instance, that vec.as_ptr().add(vec.len()) (for vec: Vec<T>) is always safe.

Consider using wrapping_add(#method.wrapping_add) instead if these constraints are difficult to satisfy. The only advantage of this method is that it enables more aggressive compiler optimizations.

InBound, NonZero
5631core::pointeras_mutmethod

When calling this method, you have to ensure that either the pointer is null or the pointer is convertible to a reference.

5632core::pointeras_mut_uncheckedmethod

When calling this method, you have to ensure that the pointer is convertible to a reference.

5633core::pointeras_refmethod

When calling this method, you have to ensure that either the pointer is null or the pointer is convertible to a reference.

5634core::pointeras_ref_uncheckedmethod

When calling this method, you have to ensure that the pointer is convertible to a reference.


When calling this method, you have to ensure that the pointer is convertible to a reference.

5635core::pointeras_uninit_mutmethod

When calling this method, you have to ensure that either the pointer is null or the pointer is convertible to a reference. Note that because the created reference is to MaybeUninit<T>, the source pointer can point to uninitialized memory.

5636core::pointeras_uninit_refmethod

When calling this method, you have to ensure that either the pointer is null or the pointer is convertible to a reference. Note that because the created reference is to MaybeUninit<T>, the source pointer can point to uninitialized memory.

5637core::pointeras_uninit_slicemethod

When calling this method, you have to ensure that either the pointer is null or all of the following are true:

  • The pointer must be [valid] for reads for ptr.len() * size_of::<T>() many bytes, and it must be properly aligned. This means in particular:
  • The entire memory range of this slice must be contained within a single [allocation]! Slices can never span across multiple allocations.
  • The pointer must be aligned even for zero-length slices. One reason for this is that enum layout optimizations may rely on references (including slices of any length) being aligned and non-null to distinguish them from other data. You can obtain a pointer that is usable as data for zero-length slices using NonNull::dangling().
  • The total size ptr.len() * size_of::<T>() of the slice must be no larger than isize::MAX. See the safety documentation of pointer::offset.
  • You must enforce Rust's aliasing rules, since the returned lifetime 'a is arbitrarily chosen and does not necessarily reflect the actual lifetime of the data. In particular, while this reference exists, the memory the pointer points to must not get mutated (except inside UnsafeCell).

This applies even if the result of this method is unused!

See also slice::from_raw_parts[].

NonNull, Align, Alias
5638core::pointeras_uninit_slice_mutmethod

When calling this method, you have to ensure that either the pointer is null or all of the following is true:

  • The pointer must be [valid] for reads and writes for ptr.len() * size_of::<T>() many bytes, and it must be properly aligned. This means in particular:
  • The entire memory range of this slice must be contained within a single [allocation]! Slices can never span across multiple allocations.
  • The pointer must be aligned even for zero-length slices. One reason for this is that enum layout optimizations may rely on references (including slices of any length) being aligned and non-null to distinguish them from other data. You can obtain a pointer that is usable as data for zero-length slices using NonNull::dangling().
  • The total size ptr.len() * size_of::<T>() of the slice must be no larger than isize::MAX. See the safety documentation of pointer::offset.
  • You must enforce Rust's aliasing rules, since the returned lifetime 'a is arbitrarily chosen and does not necessarily reflect the actual lifetime of the data. In particular, while this reference exists, the memory the pointer points to must not get accessed (read or written) through any other pointer.

This applies even if the result of this method is unused!

See also slice::from_raw_parts_mut[].

NonNull, Align, Alias
5639core::pointerbyte_addmethod
5640core::pointerbyte_offsetmethod
5641core::pointerbyte_offset_frommethod
5642core::pointerbyte_offset_from_unsignedmethod
5643core::pointerbyte_submethod
5644core::pointercopy_frommethod
5645core::pointercopy_from_nonoverlappingmethod
5646core::pointercopy_tomethod
5647core::pointercopy_to_nonoverlappingmethod
5648core::pointerdrop_in_placemethod
5649core::pointerget_uncheckedmethod

Calling this method with an out-of-bounds index or a dangling slice pointer is [undefined behavior] even if the resulting pointer is not used.

5650core::pointerget_unchecked_mutmethod

Calling this method with an out-of-bounds index or a dangling slice pointer is [undefined behavior] even if the resulting pointer is not used.

5651core::pointeroffsetmethod

If any of the following conditions are violated, the result is Undefined Behavior:

  • The offset in bytes, count * size_of::<T>(), computed on mathematical integers (without "wrapping around"), must fit in an isize.
  • Let result be self.addr() + count * size_of::<T>(), computed on mathematical integers. This must fit in a usize.
  • If the computed offset is non-zero, then self must be [derived from][crate::ptr#provenance] a pointer to some [allocation], and the entire memory range between self and result (i.e., min(self.addr(), result)..max(self.addr(), result)) must be in bounds of that allocation.

Allocations can never be larger than isize::MAX bytes and they can only contain addresses representable by usize, so technically the last condition implies the first two. This implies, for instance, that vec.as_ptr().offset(vec.len() as isize) (for vec: Vec<T>) is always safe.

Consider using wrapping_offset(#method.wrapping_offset) instead if these constraints are difficult to satisfy. The only advantage of this method is that it enables more aggressive compiler optimizations.

InBound, NonZero
5652core::pointeroffset_frommethod

If any of the following conditions are violated, the result is Undefined Behavior:

  • self and origin must either
  • point to the same address, or
  • both be [derived from][crate::ptr#provenance] a pointer to the same [allocation], and the memory range between the two pointers must be in bounds of that object. (See below for an example.)
  • The distance between the pointers, in bytes, must be an exact multiple of the size of T.

As a consequence, the absolute distance between the pointers, in bytes, computed on mathematical integers (without "wrapping around"), cannot overflow an isize. This is implied by the in-bounds requirement, and the fact that no allocation can be larger than isize::MAX bytes.

The requirement for pointers to be derived from the same allocation is primarily needed for const-compatibility: the distance between pointers into different allocated objects is not known at compile-time. However, the requirement also exists at runtime and may be exploited by optimizations. If you wish to compute the difference between pointers that are not guaranteed to be from the same allocation, use (self.addr() as isize - origin.addr() as isize) / size_of::<T>().

Allocated, InBound
5653core::pointeroffset_from_unsignedmethod
  • The distance between the pointers must be non-negative (self >= origin)
  • All the safety conditions of offset_from(#method.offset_from) apply to this method as well; see it for the full details.

Importantly, despite the return type of this method being able to represent a larger offset, it's still not permitted to pass pointers which differ by more than isize::MAX bytes. As such, the result of this method will always be less than or equal to isize::MAX as usize.

InBound
5654core::pointerreadmethod
5655core::pointerread_unalignedmethod
5656core::pointerread_volatilemethod
5657core::pointerreplacemethod
5658core::pointersplit_at_mutmethod

mid must be [in-bounds] of the underlying [allocation]. Which means self must be dereferenceable and span a single allocation that is at least mid size_of::<T>() bytes long. Not upholding these requirements is [undefined behavior]* even if the resulting pointers are not used.

Since len being in-bounds is not a safety invariant of *mut [T] the safety requirements of this method are the same as for split_at_mut_unchecked. The explicit bounds check is only as useful as len is correct.

ValidPtr
5659core::pointersplit_at_mut_uncheckedmethod

mid must be [in-bounds] of the underlying [allocation]. Which means self must be dereferenceable and span a single allocation that is at least mid size_of::<T>() bytes long. Not upholding these requirements is [undefined behavior]* even if the resulting pointers are not used.

ValidPtr
5660core::pointersubmethod

If any of the following conditions are violated, the result is Undefined Behavior:

  • The offset in bytes, count * size_of::<T>(), computed on mathematical integers (without "wrapping around"), must fit in an isize.
  • Let result be self.addr() - count * size_of::<T>(), computed on mathematical integers. This must fit in a usize.
  • If the computed offset is non-zero, then self must be [derived from][crate::ptr#provenance] a pointer to some [allocation], and the entire memory range between self and result (i.e., result..self.addr()) must be in bounds of that allocation.

Allocations can never be larger than isize::MAX bytes and they can only contain addresses representable by usize, so technically the last condition implies the first two.

Consider using wrapping_sub(#method.wrapping_sub) instead if these constraints are difficult to satisfy. The only advantage of this method is that it enables more aggressive compiler optimizations.

InBound, NonZero
5661core::pointerswapmethod
5662core::pointerwritemethod
5663core::pointerwrite_bytesmethod
5664core::pointerwrite_unalignedmethod
5665core::pointerwrite_volatilemethod
5666core::prelude::v1Sendtrait
5667core::prelude::v1Synctrait
5668core::ptrcopyfunction

Behavior is undefined if any of the following conditions are violated:

  • src must be [valid] for reads of count * size_of::<T>() bytes or that number must be 0.
  • dst must be [valid] for writes of count size_of::<T>() bytes or that number must be 0, and dst must remain valid even when src is read for count size_of::<T>() bytes. (This means if the memory ranges overlap, the dst pointer must not be invalidated by src reads.)
  • Both src and dst must be properly aligned.

Like read, copy creates a bitwise copy of T, regardless of whether T is Copy. If T is not Copy, using both the values in the region beginning at src and the region beginning at dst can [violate memory safety][read-ownership].

Note that even if the effectively copied size (count * size_of::<T>()) is 0, the pointers must be properly aligned.

Align, Valid, Alive
5669core::ptrcopy_nonoverlappingfunction

Behavior is undefined if any of the following conditions are violated:

  • src must be [valid] for reads of count * size_of::<T>() bytes or that number must be 0.
  • dst must be [valid] for writes of count * size_of::<T>() bytes or that number must be 0.
  • Both src and dst must be properly aligned.
  • The region of memory beginning at src with a size of count size_of::<T>() bytes must not* overlap with the region of memory beginning at dst with the same size.

Like read, copy_nonoverlapping creates a bitwise copy of T, regardless of whether T is Copy. If T is not Copy, using both the values in the region beginning at src and the region beginning at dst can [violate memory safety][read-ownership].

Note that even if the effectively copied size (count * size_of::<T>()) is 0, the pointers must be properly aligned.

Align, Valid
5670core::ptrdrop_in_placefunction

Behavior is undefined if any of the following conditions are violated:

  • to_drop must be [valid] for both reads and writes.
  • to_drop must be properly aligned, even if T has size 0.
  • to_drop must be nonnull, even if T has size 0.
  • The value to_drop points to must be valid for dropping, which may mean it must uphold additional invariants. These invariants depend on the type of the value being dropped. For instance, when dropping a Box, the box's pointer to the heap must be valid.
  • While drop_in_place is executing, the only way to access parts of to_drop is through the &mut self references supplied to the Drop::drop methods that drop_in_place invokes.

Additionally, if T is not Copy, using the pointed-to value after calling drop_in_place can cause undefined behavior. Note that *to_drop = foo counts as a use because it will cause the value to be dropped again. write() can be used to overwrite data without causing it to be dropped.

NonNull, Align, Valid
5671core::ptrreadfunction

Behavior is undefined if any of the following conditions are violated:

  • src must be [valid] for reads or T must be a ZST.
  • src must be properly aligned. Use read_unaligned if this is not the case.
  • src must point to a properly initialized value of type T.

Note that even if T has size 0, the pointer must be properly aligned.

Align, Init
5672core::ptrread_unalignedfunction

Behavior is undefined if any of the following conditions are violated:

  • src must be [valid] for reads.
  • src must point to a properly initialized value of type T.

Like read, read_unaligned creates a bitwise copy of T, regardless of whether T is Copy. If T is not Copy, using both the returned value and the value at *src can [violate memory safety][read-ownership].

Valid, Init
5673core::ptrread_volatilefunction

Like read, read_volatile creates a bitwise copy of T, regardless of whether T is Copy. If T is not Copy, using both the returned value and the value at *src can [violate memory safety][read-ownership]. However, storing non-Copy types in volatile memory is almost certainly incorrect.

Behavior is undefined if any of the following conditions are violated:

  • src must be either [valid] for reads, or T must be a ZST, or src must point to memory outside of all Rust allocations and reading from that memory must:
  • not trap, and
  • not cause any memory inside a Rust allocation to be modified.
  • src must be properly aligned.
  • Reading from src must produce a properly initialized value of type T.

Note that even if T has size 0, the pointer must be properly aligned.

Align, Valid, Init, NonVolatile
5674core::ptrreplacefunction

Behavior is undefined if any of the following conditions are violated:

  • dst must be [valid] for both reads and writes or T must be a ZST.
  • dst must be properly aligned.
  • dst must point to a properly initialized value of type T.

Note that even if T has size 0, the pointer must be properly aligned.

Align, Init
5675core::ptrswapfunction

Behavior is undefined if any of the following conditions are violated:

  • Both x and y must be [valid] for both reads and writes. They must remain valid even when the other pointer is written. (This means if the memory ranges overlap, the two pointers must not be subject to aliasing restrictions relative to each other.)
  • Both x and y must be properly aligned.

Note that even if T has size 0, the pointers must be properly aligned.

Align, Valid, Alias, Alive
5676core::ptrswap_nonoverlappingfunction

Behavior is undefined if any of the following conditions are violated:

  • Both x and y must be [valid] for both reads and writes of count * size_of::<T>() bytes.
  • Both x and y must be properly aligned.
  • The region of memory beginning at x with a size of count size_of::<T>() bytes must not* overlap with the region of memory beginning at y with the same size.

Note that even if the effectively copied size (count * size_of::<T>()) is 0, the pointers must be properly aligned.

Align
5677core::ptrwritefunction

Behavior is undefined if any of the following conditions are violated:

  • dst must be [valid] for writes or T must be a ZST.
  • dst must be properly aligned. Use write_unaligned if this is not the case.

Note that even if T has size 0, the pointer must be properly aligned.

Align
5678core::ptrwrite_bytesfunction

Behavior is undefined if any of the following conditions are violated:

  • dst must be [valid] for writes of count * size_of::<T>() bytes.
  • dst must be properly aligned.

Note that even if the effectively copied size (count * size_of::<T>()) is 0, the pointer must be properly aligned.

Additionally, note that changing *dst in this way can easily lead to undefined behavior (UB) later if the written bytes are not a valid representation of some T. For instance, the following is an incorrect use of this function:

``rust,no_run unsafe { let mut value: u8 = 0; let ptr: mut bool = &mut value as mut u8 as *mut bool; let _bool = ptr.read(); // This is fine, ptr points to a valid bool. ptr.write_bytes(42u8, 1); // This function itself does not cause UB... let _bool = ptr.read(); // ...but it makes this operation UB! ⚠️ } ``

Align
5679core::ptrwrite_unalignedfunction

Behavior is undefined if any of the following conditions are violated:

  • dst must be [valid] for writes.
5680core::ptrwrite_volatilefunction

Behavior is undefined if any of the following conditions are violated:

  • dst must be either [valid] for writes, or T must be a ZST, or dst must point to memory outside of all Rust allocations and writing to that memory must:
  • not trap, and
  • not cause any memory inside a Rust allocation to be modified.
  • dst must be properly aligned.

Note that even if T has size 0, the pointer must be properly aligned.

Align
5681core::ptr::non_null::NonNulladdmethod

If any of the following conditions are violated, the result is Undefined Behavior:

  • The offset in bytes, count * size_of::<T>(), computed on mathematical integers (without "wrapping around"), must fit in an isize.
  • Let result be self.addr() + count * size_of::<T>(), computed on mathematical integers. This must fit in a usize.
  • If the computed offset is non-zero, then self must be [derived from][crate::ptr#provenance] a pointer to some [allocation], and the entire memory range between self and result (i.e., self.addr()..result) must be in bounds of that allocation.

Allocations can never be larger than isize::MAX bytes and they can only contain addresses representable by usize, so technically the last condition implies the first two. This implies, for instance, that vec.as_ptr().add(vec.len()) (for vec: Vec<T>) is always safe.

InBound, NonZero
5682core::ptr::non_null::NonNullas_mutmethod

When calling this method, you have to ensure that the pointer is convertible to a reference.

5683core::ptr::non_null::NonNullas_refmethod

When calling this method, you have to ensure that the pointer is convertible to a reference.

5684core::ptr::non_null::NonNullas_uninit_mutmethod

When calling this method, you have to ensure that the pointer is convertible to a reference. Note that because the created reference is to MaybeUninit<T>, the source pointer can point to uninitialized memory.

5685core::ptr::non_null::NonNullas_uninit_refmethod

When calling this method, you have to ensure that the pointer is convertible to a reference. Note that because the created reference is to MaybeUninit<T>, the source pointer can point to uninitialized memory.

5686core::ptr::non_null::NonNullas_uninit_slicemethod

When calling this method, you have to ensure that all of the following is true:

  • The pointer must be [valid] for reads for ptr.len() * size_of::<T>() many bytes, and it must be properly aligned. This means in particular:
  • The entire memory range of this slice must be contained within a single allocation! Slices can never span across multiple allocations.
  • The pointer must be aligned even for zero-length slices. One reason for this is that enum layout optimizations may rely on references (including slices of any length) being aligned and non-null to distinguish them from other data. You can obtain a pointer that is usable as data for zero-length slices using NonNull::dangling().
  • The total size ptr.len() * size_of::<T>() of the slice must be no larger than isize::MAX. See the safety documentation of pointer::offset.
  • You must enforce Rust's aliasing rules, since the returned lifetime 'a is arbitrarily chosen and does not necessarily reflect the actual lifetime of the data. In particular, while this reference exists, the memory the pointer points to must not get mutated (except inside UnsafeCell).

This applies even if the result of this method is unused!

See also slice::from_raw_parts.

NonNull, Align, Alias
5687core::ptr::non_null::NonNullas_uninit_slice_mutmethod

When calling this method, you have to ensure that all of the following is true:

  • The pointer must be [valid] for reads and writes for ptr.len() * size_of::<T>() many bytes, and it must be properly aligned. This means in particular:
  • The entire memory range of this slice must be contained within a single allocation! Slices can never span across multiple allocations.
  • The pointer must be aligned even for zero-length slices. One reason for this is that enum layout optimizations may rely on references (including slices of any length) being aligned and non-null to distinguish them from other data. You can obtain a pointer that is usable as data for zero-length slices using NonNull::dangling().
  • The total size ptr.len() * size_of::<T>() of the slice must be no larger than isize::MAX. See the safety documentation of pointer::offset.
  • You must enforce Rust's aliasing rules, since the returned lifetime 'a is arbitrarily chosen and does not necessarily reflect the actual lifetime of the data. In particular, while this reference exists, the memory the pointer points to must not get accessed (read or written) through any other pointer.

This applies even if the result of this method is unused!

See also slice::from_raw_parts_mut.

NonNull, Align, Alias
5688core::ptr::non_null::NonNullbyte_addmethod
5689core::ptr::non_null::NonNullbyte_offsetmethod
5690core::ptr::non_null::NonNullbyte_offset_frommethod
5691core::ptr::non_null::NonNullbyte_offset_from_unsignedmethod
5692core::ptr::non_null::NonNullbyte_submethod
5693core::ptr::non_null::NonNullcopy_frommethod
5694core::ptr::non_null::NonNullcopy_from_nonoverlappingmethod
5695core::ptr::non_null::NonNullcopy_tomethod
5696core::ptr::non_null::NonNullcopy_to_nonoverlappingmethod
5697core::ptr::non_null::NonNulldrop_in_placemethod
5698core::ptr::non_null::NonNullget_unchecked_mutmethod

Calling this method with an out-of-bounds index or a dangling slice pointer is [undefined behavior] even if the resulting pointer is not used.

5699core::ptr::non_null::NonNullnew_uncheckedmethod

ptr must be non-null.

NonNull
5700core::ptr::non_null::NonNulloffsetmethod

If any of the following conditions are violated, the result is Undefined Behavior:

  • The offset in bytes, count * size_of::<T>(), computed on mathematical integers (without "wrapping around"), must fit in an isize.
  • Let result be self.addr() + count * size_of::<T>(), computed on mathematical integers. This must fit in a usize.
  • If the computed offset is non-zero, then self must be [derived from][crate::ptr#provenance] a pointer to some [allocation], and the entire memory range between self and result (i.e., min(self.addr(), result)..max(self.addr(), result)) must be in bounds of that allocation.

Allocations can never be larger than isize::MAX bytes and they can only contain addresses representable by usize, so technically the last condition implies the first two. This implies, for instance, that vec.as_ptr().offset(vec.len() as isize) (for vec: Vec<T>) is always safe.

InBound, NonZero
5701core::ptr::non_null::NonNulloffset_frommethod

If any of the following conditions are violated, the result is Undefined Behavior:

  • self and origin must either
  • point to the same address, or
  • both be derived from a pointer to the same [allocation], and the memory range between the two pointers must be in bounds of that object. (See below for an example.)
  • The distance between the pointers, in bytes, must be an exact multiple of the size of T.

As a consequence, the absolute distance between the pointers, in bytes, computed on mathematical integers (without "wrapping around"), cannot overflow an isize. This is implied by the in-bounds requirement, and the fact that no allocation can be larger than isize::MAX bytes.

The requirement for pointers to be derived from the same allocation is primarily needed for const-compatibility: the distance between pointers into different allocated objects is not known at compile-time. However, the requirement also exists at runtime and may be exploited by optimizations. If you wish to compute the difference between pointers that are not guaranteed to be from the same allocation, use (self.addr() as isize - origin.addr() as isize) / size_of::<T>().

Allocated, InBound
5702core::ptr::non_null::NonNulloffset_from_unsignedmethod
  • The distance between the pointers must be non-negative (self >= origin)
  • All the safety conditions of offset_from(#method.offset_from) apply to this method as well; see it for the full details.

Importantly, despite the return type of this method being able to represent a larger offset, it's still not permitted to pass pointers which differ by more than isize::MAX bytes. As such, the result of this method will always be less than or equal to isize::MAX as usize.

InBound
5703core::ptr::non_null::NonNullreadmethod
5704core::ptr::non_null::NonNullread_unalignedmethod
5705core::ptr::non_null::NonNullread_volatilemethod
5706core::ptr::non_null::NonNullreplacemethod
5707core::ptr::non_null::NonNullsubmethod

If any of the following conditions are violated, the result is Undefined Behavior:

  • The offset in bytes, count * size_of::<T>(), computed on mathematical integers (without "wrapping around"), must fit in an isize.
  • Let result be self.addr() - count * size_of::<T>(), computed on mathematical integers. This must fit in a usize.
  • If the computed offset is non-zero, then self must be [derived from][crate::ptr#provenance] a pointer to some [allocation], and the entire memory range between self and result (i.e., result..self.addr()) must be in bounds of that allocation.

Allocations can never be larger than isize::MAX bytes and they can only contain addresses representable by usize, so technically the last condition implies the first two.

InBound, NonZero
5708core::ptr::non_null::NonNullswapmethod
5709core::ptr::non_null::NonNullwritemethod
5710core::ptr::non_null::NonNullwrite_bytesmethod
5711core::ptr::non_null::NonNullwrite_unalignedmethod
5712core::ptr::non_null::NonNullwrite_volatilemethod
5713core::range::Rangeget_uncheckedmethod

Calling this method with an out-of-bounds index or a dangling slice pointer is [undefined behavior] even if the resulting pointer is not used.

5714core::range::Rangeget_unchecked_mutmethod

Calling this method with an out-of-bounds index or a dangling slice pointer is [undefined behavior] even if the resulting pointer is not used.

5715core::range::RangeFromget_uncheckedmethod

Calling this method with an out-of-bounds index or a dangling slice pointer is [undefined behavior] even if the resulting pointer is not used.

5716core::range::RangeFromget_unchecked_mutmethod

Calling this method with an out-of-bounds index or a dangling slice pointer is [undefined behavior] even if the resulting pointer is not used.

5717core::range::RangeInclusiveget_uncheckedmethod

Calling this method with an out-of-bounds index or a dangling slice pointer is [undefined behavior] even if the resulting pointer is not used.

5718core::range::RangeInclusiveget_unchecked_mutmethod

Calling this method with an out-of-bounds index or a dangling slice pointer is [undefined behavior] even if the resulting pointer is not used.

5719core::range::RangeToInclusiveget_uncheckedmethod

Calling this method with an out-of-bounds index or a dangling slice pointer is [undefined behavior] even if the resulting pointer is not used.

5720core::range::RangeToInclusiveget_unchecked_mutmethod

Calling this method with an out-of-bounds index or a dangling slice pointer is [undefined behavior] even if the resulting pointer is not used.

5721core::result::Resultunwrap_err_uncheckedmethod

Calling this method on an Ok is [undefined behavior].

5722core::result::Resultunwrap_uncheckedmethod

Calling this method on an Err is [undefined behavior].

5723core::sliceGetDisjointMutIndextrait

If is_in_bounds() returns true and is_overlapping() returns false, it must be safe to index the slice with the indices.

5724core::sliceSliceIndextrait
5725core::slicealign_tomethod

This method is essentially a transmute with respect to the elements in the returned middle slice, so all the usual caveats pertaining to transmute::<T, U> also apply here.

5726core::slicealign_to_mutmethod

This method is essentially a transmute with respect to the elements in the returned middle slice, so all the usual caveats pertaining to transmute::<T, U> also apply here.

5727core::sliceas_ascii_uncheckedmethod

Every byte in the slice must be in 0..=127, or else this is UB.

5728core::sliceas_chunks_uncheckedmethod

This may only be called when - The slice splits exactly into N-element chunks (aka self.len() % N == 0). - N != 0.

5729core::sliceas_chunks_unchecked_mutmethod

This may only be called when - The slice splits exactly into N-element chunks (aka self.len() % N == 0). - N != 0.

5730core::sliceassume_init_dropmethod

It is up to the caller to guarantee that every MaybeUninit<T> in the slice really is in an initialized state. Calling this when the content is not yet fully initialized causes undefined behavior.

On top of that, all additional invariants of the type T must be satisfied, as the Drop implementation of T (or its members) may rely on this. For example, setting a Vec<T> to an invalid but non-null address makes it initialized (under the current implementation; this does not constitute a stable guarantee), because the only requirement the compiler knows about it is that the data pointer must be non-null. Dropping such a Vec<T> however will cause undefined behaviour.

NonNull, Init
5731core::sliceassume_init_mutmethod

Calling this when the content is not yet fully initialized causes undefined behavior: it is up to the caller to guarantee that every MaybeUninit<T> in the slice really is in an initialized state. For instance, .assume_init_mut() cannot be used to initialize a MaybeUninit slice.

Init
5732core::sliceassume_init_refmethod

Calling this when the content is not yet fully initialized causes undefined behavior: it is up to the caller to guarantee that every MaybeUninit<T> in the slice really is in an initialized state.

Init
5733core::sliceclone_to_uninitmethod

Behavior is undefined if any of the following conditions are violated:

  • dest must be [valid] for writes for size_of_val(self) bytes.
  • dest must be properly aligned to align_of_val(self).
Align
5734core::slicefrom_mut_ptr_rangefunction

Behavior is undefined if any of the following conditions are violated:

  • The start pointer of the range must be a non-null, [valid] and properly aligned pointer to the first element of a slice.
  • The end pointer must be a [valid] and properly aligned pointer to one past the last element, such that the offset from the end to the start pointer is the length of the slice.
  • The entire memory range of this slice must be contained within a single allocation! Slices can never span across multiple allocations.
  • The range must contain N consecutive properly initialized values of type T.
  • The memory referenced by the returned slice must not be accessed through any other pointer (not derived from the return value) for the duration of lifetime 'a. Both read and write accesses are forbidden.
  • The total length of the range must be no larger than isize::MAX, and adding that size to start must not "wrap around" the address space. See the safety documentation of pointer::offset.

Note that a range created from slice::as_mut_ptr_range fulfills these requirements.

NonNull, Align, Init, NonAccessable
5735core::slicefrom_ptr_rangefunction

Behavior is undefined if any of the following conditions are violated:

  • The start pointer of the range must be a non-null, [valid] and properly aligned pointer to the first element of a slice.
  • The end pointer must be a [valid] and properly aligned pointer to one past the last element, such that the offset from the end to the start pointer is the length of the slice.
  • The entire memory range of this slice must be contained within a single allocation! Slices can never span across multiple allocations.
  • The range must contain N consecutive properly initialized values of type T.
  • The memory referenced by the returned slice must not be mutated for the duration of lifetime 'a, except inside an UnsafeCell.
  • The total length of the range must be no larger than isize::MAX, and adding that size to start must not "wrap around" the address space. See the safety documentation of pointer::offset.

Note that a range created from slice::as_ptr_range fulfills these requirements.

NonNull, Align, Init, NonMutate
5736core::slicefrom_raw_partsfunction

Behavior is undefined if any of the following conditions are violated:

  • data must be non-null, [valid] for reads for len * size_of::<T>() many bytes, and it must be properly aligned. This means in particular:
  • The entire memory range of this slice must be contained within a single allocation! Slices can never span across multiple allocations. See below for an example incorrectly not taking this into account.
  • data must be non-null and aligned even for zero-length slices or slices of ZSTs. One reason for this is that enum layout optimizations may rely on references (including slices of any length) being aligned and non-null to distinguish them from other data. You can obtain a pointer that is usable as data for zero-length slices using NonNull::dangling().
  • data must point to len consecutive properly initialized values of type T.
  • The memory referenced by the returned slice must not be mutated for the duration of lifetime 'a, except inside an UnsafeCell.
  • The total size len * size_of::<T>() of the slice must be no larger than isize::MAX, and adding that size to data must not "wrap around" the address space. See the safety documentation of pointer::offset.
NonNull, Align, Init, NonMutate
5737core::slicefrom_raw_parts_mutfunction

Behavior is undefined if any of the following conditions are violated:

  • data must be non-null, [valid] for both reads and writes for len * size_of::<T>() many bytes, and it must be properly aligned. This means in particular:
  • The entire memory range of this slice must be contained within a single allocation! Slices can never span across multiple allocations.
  • data must be non-null and aligned even for zero-length slices or slices of ZSTs. One reason for this is that enum layout optimizations may rely on references (including slices of any length) being aligned and non-null to distinguish them from other data. You can obtain a pointer that is usable as data for zero-length slices using NonNull::dangling().
  • data must point to len consecutive properly initialized values of type T.
  • The memory referenced by the returned slice must not be accessed through any other pointer (not derived from the return value) for the duration of lifetime 'a. Both read and write accesses are forbidden.
  • The total size len * size_of::<T>() of the slice must be no larger than isize::MAX, and adding that size to data must not "wrap around" the address space. See the safety documentation of pointer::offset.
NonNull, Align, Init, NonAccessable
5738core::sliceget_disjoint_unchecked_mutmethod

Calling this method with overlapping or out-of-bounds indices is [undefined behavior] even if the resulting references are not used.

5739core::sliceget_uncheckedmethod

Calling this method with an out-of-bounds index is [undefined behavior] even if the resulting reference is not used.

You can think of this like .get(index).unwrap_unchecked(). It's UB to call .get_unchecked(len), even if you immediately convert to a pointer. And it's UB to call .get_unchecked(..len + 1), .get_unchecked(..=len), or similar.

Unwrap
5740core::sliceget_unchecked_mutmethod

Calling this method with an out-of-bounds index is [undefined behavior] even if the resulting reference is not used.

You can think of this like .get_mut(index).unwrap_unchecked(). It's UB to call .get_unchecked_mut(len), even if you immediately convert to a pointer. And it's UB to call .get_unchecked_mut(..len + 1), .get_unchecked_mut(..=len), or similar.

Unwrap
5741core::slicesplit_at_mut_uncheckedmethod

Calling this method with an out-of-bounds index is [undefined behavior] even if the resulting reference is not used. The caller has to ensure that 0 <= mid <= self.len().

5742core::slicesplit_at_uncheckedmethod

Calling this method with an out-of-bounds index is [undefined behavior] even if the resulting reference is not used. The caller has to ensure that 0 <= mid <= self.len().

5743core::sliceswap_uncheckedmethod

Calling this method with an out-of-bounds index is [undefined behavior]. The caller has to ensure that a < self.len() and b < self.len().

5744core::slice::index::SliceIndexget_uncheckedtrait_method

Calling this method with an out-of-bounds index or a dangling slice pointer is [undefined behavior] even if the resulting pointer is not used.

5745core::slice::index::SliceIndexget_unchecked_muttrait_method

Calling this method with an out-of-bounds index or a dangling slice pointer is [undefined behavior] even if the resulting pointer is not used.

5746core::stras_ascii_uncheckedmethod

Every character in this string must be ASCII, or else this is UB.

5747core::stras_bytes_mutmethod

The caller must ensure that the content of the slice is valid UTF-8 before the borrow ends and the underlying str is used.

Use of a str whose contents are not valid UTF-8 is undefined behavior.

ValidString
5748core::strclone_to_uninitmethod

Behavior is undefined if any of the following conditions are violated:

  • dest must be [valid] for writes for size_of_val(self) bytes.
  • dest must be properly aligned to align_of_val(self).
Align
5749core::strfrom_raw_partsfunction
5750core::strfrom_raw_parts_mutfunction
5751core::strfrom_utf8_uncheckedfunction

The bytes passed in must be valid UTF-8.

ValidString
5752core::strfrom_utf8_uncheckedmethod

The bytes passed in must be valid UTF-8.

ValidString
5753core::strfrom_utf8_unchecked_mutmethod
5754core::strfrom_utf8_unchecked_mutfunction
5755core::strget_uncheckedmethod

Callers of this function are responsible that these preconditions are satisfied:

  • The starting index must not exceed the ending index;
  • Indexes must be within bounds of the original slice;
  • Indexes must lie on UTF-8 sequence boundaries.

Failing that, the returned string slice may reference invalid memory or violate the invariants communicated by the str type.

InBound
5756core::strget_unchecked_mutmethod

Callers of this function are responsible that these preconditions are satisfied:

  • The starting index must not exceed the ending index;
  • Indexes must be within bounds of the original slice;
  • Indexes must lie on UTF-8 sequence boundaries.

Failing that, the returned string slice may reference invalid memory or violate the invariants communicated by the str type.

InBound
5757core::strnext_code_pointfunction

bytes must produce a valid UTF-8-like (UTF-8 or WTF-8) string

ValidString
5758core::strslice_mut_uncheckedmethod

Callers of this function are responsible that three preconditions are satisfied:

  • begin must not exceed end.
  • begin and end must be byte positions within the string slice.
  • begin and end must lie on UTF-8 sequence boundaries.
InBound
5759core::strslice_uncheckedmethod

Callers of this function are responsible that three preconditions are satisfied:

  • begin must not exceed end.
  • begin and end must be byte positions within the string slice.
  • begin and end must lie on UTF-8 sequence boundaries.
InBound
5760core::str::iter::SplitNclone_to_uninitmethod

Behavior is undefined if any of the following conditions are violated:

  • dest must be [valid] for writes for size_of_val(self) bytes.
  • dest must be properly aligned to align_of_val(self).
Align
5761core::str::patternReverseSearchertrait
5762core::str::patternSearchertrait
5763core::sync::atomicAtomicPrimitivetrait
5764core::sync::atomic::Atomicfrom_ptrmethod
  • ptr must be aligned to align_of::<AtomicU32>() (note that on some platforms this can be bigger than align_of::<u32>()).
  • ptr must be [valid] for both reads and writes for the whole lifetime 'a.
  • You must adhere to the [Memory model for atomic accesses]. In particular, it is not allowed to mix conflicting atomic and non-atomic accesses, or atomic accesses of different sizes, without synchronization.

  • ptr must be aligned to align_of::<AtomicI32>() (note that on some platforms this can be bigger than align_of::<i32>()).
  • ptr must be [valid] for both reads and writes for the whole lifetime 'a.
  • You must adhere to the [Memory model for atomic accesses]. In particular, it is not allowed to mix conflicting atomic and non-atomic accesses, or atomic accesses of different sizes, without synchronization.

  • ptr must be aligned to align_of::<AtomicUsize>() (note that on some platforms this can be bigger than align_of::<usize>()).
  • ptr must be [valid] for both reads and writes for the whole lifetime 'a.
  • You must adhere to the [Memory model for atomic accesses]. In particular, it is not allowed to mix conflicting atomic and non-atomic accesses, or atomic accesses of different sizes, without synchronization.

  • ptr must be aligned to align_of::<AtomicU16>() (note that on some platforms this can be bigger than align_of::<u16>()).
  • ptr must be [valid] for both reads and writes for the whole lifetime 'a.
  • You must adhere to the [Memory model for atomic accesses]. In particular, it is not allowed to mix conflicting atomic and non-atomic accesses, or atomic accesses of different sizes, without synchronization.

  • ptr must be aligned to align_of::<AtomicIsize>() (note that on some platforms this can be bigger than align_of::<isize>()).
  • ptr must be [valid] for both reads and writes for the whole lifetime 'a.
  • You must adhere to the [Memory model for atomic accesses]. In particular, it is not allowed to mix conflicting atomic and non-atomic accesses, or atomic accesses of different sizes, without synchronization.

  • ptr must be aligned to align_of::<AtomicI8>() (note that this is always true, since align_of::<AtomicI8>() == 1).
  • ptr must be [valid] for both reads and writes for the whole lifetime 'a.
  • You must adhere to the [Memory model for atomic accesses]. In particular, it is not allowed to mix conflicting atomic and non-atomic accesses, or atomic accesses of different sizes, without synchronization.

  • ptr must be aligned to align_of::<AtomicI16>() (note that on some platforms this can be bigger than align_of::<i16>()).
  • ptr must be [valid] for both reads and writes for the whole lifetime 'a.
  • You must adhere to the [Memory model for atomic accesses]. In particular, it is not allowed to mix conflicting atomic and non-atomic accesses, or atomic accesses of different sizes, without synchronization.

  • ptr must be aligned to align_of::<AtomicU128>() (note that on some platforms this can be bigger than align_of::<u128>()).
  • ptr must be [valid] for both reads and writes for the whole lifetime 'a.
  • You must adhere to the [Memory model for atomic accesses]. In particular, it is not allowed to mix conflicting atomic and non-atomic accesses, or atomic accesses of different sizes, without synchronization.

  • ptr must be aligned to align_of::<AtomicU8>() (note that this is always true, since align_of::<AtomicU8>() == 1).
  • ptr must be [valid] for both reads and writes for the whole lifetime 'a.
  • You must adhere to the [Memory model for atomic accesses]. In particular, it is not allowed to mix conflicting atomic and non-atomic accesses, or atomic accesses of different sizes, without synchronization.

  • ptr must be aligned to align_of::<AtomicI128>() (note that on some platforms this can be bigger than align_of::<i128>()).
  • ptr must be [valid] for both reads and writes for the whole lifetime 'a.
  • You must adhere to the [Memory model for atomic accesses]. In particular, it is not allowed to mix conflicting atomic and non-atomic accesses, or atomic accesses of different sizes, without synchronization.

  • ptr must be aligned to align_of::<AtomicU64>() (note that on some platforms this can be bigger than align_of::<u64>()).
  • ptr must be [valid] for both reads and writes for the whole lifetime 'a.
  • You must adhere to the [Memory model for atomic accesses]. In particular, it is not allowed to mix conflicting atomic and non-atomic accesses, or atomic accesses of different sizes, without synchronization.

  • ptr must be aligned to align_of::<AtomicPtr<T>>() (note that on some platforms this can be bigger than align_of::<*mut T>()).
  • ptr must be [valid] for both reads and writes for the whole lifetime 'a.
  • You must adhere to the [Memory model for atomic accesses]. In particular, it is not allowed to mix conflicting atomic and non-atomic accesses, or atomic accesses of different sizes, without synchronization.

  • ptr must be aligned to align_of::<AtomicI64>() (note that on some platforms this can be bigger than align_of::<i64>()).
  • ptr must be [valid] for both reads and writes for the whole lifetime 'a.
  • You must adhere to the [Memory model for atomic accesses]. In particular, it is not allowed to mix conflicting atomic and non-atomic accesses, or atomic accesses of different sizes, without synchronization.

  • ptr must be aligned to align_of::<AtomicBool>() (note that this is always true, since align_of::<AtomicBool>() == 1).
  • ptr must be [valid] for both reads and writes for the whole lifetime 'a.
  • You must adhere to the [Memory model for atomic accesses]. In particular, it is not allowed to mix conflicting atomic and non-atomic accesses, or atomic accesses of different sizes, without synchronization.
Align
5765core::task::wake::LocalWakerfrom_rawmethod
5766core::task::wake::LocalWakernewmethod

The behavior of the returned Waker is undefined if the contract defined in RawWakerVTable's documentation is not upheld.

5767core::task::wake::Wakerfrom_rawmethod

The behavior of the returned Waker is undefined if the contract defined in RawWaker's and RawWakerVTable's documentation is not upheld.

(Authors wishing to avoid unsafe code may implement the Wake trait instead, at the cost of a required heap allocation.)

5768core::task::wake::Wakernewmethod

The behavior of the returned Waker is undefined if the contract defined in RawWakerVTable's documentation is not upheld.

(Authors wishing to avoid unsafe code may implement the Wake trait instead, at the cost of a required heap allocation.)

5769core::u128backward_uncheckedmethod

It is undefined behavior for this operation to overflow the range of values supported by Self. If you cannot guarantee that this will not overflow, use backward or backward_checked instead.

5770core::u128disjoint_bitormethod
5771core::u128forward_uncheckedmethod

It is undefined behavior for this operation to overflow the range of values supported by Self. If you cannot guarantee that this will not overflow, use forward or forward_checked instead.

5772core::u128unchecked_addmethod

This results in undefined behavior when self + rhs > u128::MAX, i.e. when checked_add would return None.

Unwrap
5773core::u128unchecked_castmethod

This results in undefined behavior if the integer value of self is bigger than T::MAX, or smaller than T::MIN, where T is the target type.

5774core::u128unchecked_cast_frommethod

This results in undefined behavior when value will overflow when converted to this type.

5775core::u128unchecked_disjoint_bitormethod

Requires that (self & other) == 0, otherwise it's immediate UB.

Equivalently, requires that (self | other) == (self + other).

5776core::u128unchecked_div_exactmethod

This results in undefined behavior when rhs == 0 or self % rhs != 0, i.e. when checked_div_exact(Self::checked_div_exact) would return None.

5777core::u128unchecked_funnel_shlmethod

This results in undefined behavior if n is greater than or equal to u128::BITS, i.e. when funnel_shl(Self::funnel_shl) would panic.

5778core::u128unchecked_funnel_shrmethod

This results in undefined behavior if n is greater than or equal to u128::BITS, i.e. when funnel_shr(Self::funnel_shr) would panic.

5779core::u128unchecked_mulmethod

This results in undefined behavior when self * rhs > u128::MAX, i.e. when checked_mul would return None.

Unwrap
5780core::u128unchecked_shlmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shl would return None.

5781core::u128unchecked_shl_exactmethod

This results in undefined behavior when rhs > self.leading_zeros() || rhs >= u128::BITS i.e. when u128::shl_exact would return None.

5782core::u128unchecked_shrmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shr would return None.

5783core::u128unchecked_shr_exactmethod

This results in undefined behavior when rhs > self.trailing_zeros() || rhs >= u128::BITS i.e. when u128::shr_exact would return None.

5784core::u128unchecked_submethod

This results in undefined behavior when self - rhs < u128::MIN, i.e. when checked_sub would return None.

Unwrap
5785core::u16backward_uncheckedmethod

It is undefined behavior for this operation to overflow the range of values supported by Self. If you cannot guarantee that this will not overflow, use backward or backward_checked instead.

5786core::u16disjoint_bitormethod
5787core::u16forward_uncheckedmethod

It is undefined behavior for this operation to overflow the range of values supported by Self. If you cannot guarantee that this will not overflow, use forward or forward_checked instead.

5788core::u16unchecked_addmethod

This results in undefined behavior when self + rhs > u16::MAX, i.e. when checked_add would return None.

Unwrap
5789core::u16unchecked_castmethod

This results in undefined behavior if the integer value of self is bigger than T::MAX, or smaller than T::MIN, where T is the target type.

5790core::u16unchecked_cast_frommethod

This results in undefined behavior when value will overflow when converted to this type.

5791core::u16unchecked_disjoint_bitormethod

Requires that (self & other) == 0, otherwise it's immediate UB.

Equivalently, requires that (self | other) == (self + other).

5792core::u16unchecked_div_exactmethod

This results in undefined behavior when rhs == 0 or self % rhs != 0, i.e. when checked_div_exact(Self::checked_div_exact) would return None.

5793core::u16unchecked_funnel_shlmethod

This results in undefined behavior if n is greater than or equal to u16::BITS, i.e. when funnel_shl(Self::funnel_shl) would panic.

5794core::u16unchecked_funnel_shrmethod

This results in undefined behavior if n is greater than or equal to u16::BITS, i.e. when funnel_shr(Self::funnel_shr) would panic.

5795core::u16unchecked_mulmethod

This results in undefined behavior when self * rhs > u16::MAX, i.e. when checked_mul would return None.

Unwrap
5796core::u16unchecked_shlmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shl would return None.

5797core::u16unchecked_shl_exactmethod

This results in undefined behavior when rhs > self.leading_zeros() || rhs >= u16::BITS i.e. when u16::shl_exact would return None.

5798core::u16unchecked_shrmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shr would return None.

5799core::u16unchecked_shr_exactmethod

This results in undefined behavior when rhs > self.trailing_zeros() || rhs >= u16::BITS i.e. when u16::shr_exact would return None.

5800core::u16unchecked_submethod

This results in undefined behavior when self - rhs < u16::MIN, i.e. when checked_sub would return None.

Unwrap
5801core::u32backward_uncheckedmethod

It is undefined behavior for this operation to overflow the range of values supported by Self. If you cannot guarantee that this will not overflow, use backward or backward_checked instead.

5802core::u32disjoint_bitormethod
5803core::u32forward_uncheckedmethod

It is undefined behavior for this operation to overflow the range of values supported by Self. If you cannot guarantee that this will not overflow, use forward or forward_checked instead.

5804core::u32unchecked_addmethod

This results in undefined behavior when self + rhs > u32::MAX, i.e. when checked_add would return None.

Unwrap
5805core::u32unchecked_castmethod

This results in undefined behavior if the integer value of self is bigger than T::MAX, or smaller than T::MIN, where T is the target type.

5806core::u32unchecked_cast_frommethod

This results in undefined behavior when value will overflow when converted to this type.

5807core::u32unchecked_disjoint_bitormethod

Requires that (self & other) == 0, otherwise it's immediate UB.

Equivalently, requires that (self | other) == (self + other).

5808core::u32unchecked_div_exactmethod

This results in undefined behavior when rhs == 0 or self % rhs != 0, i.e. when checked_div_exact(Self::checked_div_exact) would return None.

5809core::u32unchecked_funnel_shlmethod

This results in undefined behavior if n is greater than or equal to u32::BITS, i.e. when funnel_shl(Self::funnel_shl) would panic.

5810core::u32unchecked_funnel_shrmethod

This results in undefined behavior if n is greater than or equal to u32::BITS, i.e. when funnel_shr(Self::funnel_shr) would panic.

5811core::u32unchecked_mulmethod

This results in undefined behavior when self * rhs > u32::MAX, i.e. when checked_mul would return None.

Unwrap
5812core::u32unchecked_shlmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shl would return None.

5813core::u32unchecked_shl_exactmethod

This results in undefined behavior when rhs > self.leading_zeros() || rhs >= u32::BITS i.e. when u32::shl_exact would return None.

5814core::u32unchecked_shrmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shr would return None.

5815core::u32unchecked_shr_exactmethod

This results in undefined behavior when rhs > self.trailing_zeros() || rhs >= u32::BITS i.e. when u32::shr_exact would return None.

5816core::u32unchecked_submethod

This results in undefined behavior when self - rhs < u32::MIN, i.e. when checked_sub would return None.

Unwrap
5817core::u64backward_uncheckedmethod

It is undefined behavior for this operation to overflow the range of values supported by Self. If you cannot guarantee that this will not overflow, use backward or backward_checked instead.

5818core::u64disjoint_bitormethod
5819core::u64forward_uncheckedmethod

It is undefined behavior for this operation to overflow the range of values supported by Self. If you cannot guarantee that this will not overflow, use forward or forward_checked instead.

5820core::u64unchecked_addmethod

This results in undefined behavior when self + rhs > u64::MAX, i.e. when checked_add would return None.

Unwrap
5821core::u64unchecked_castmethod

This results in undefined behavior if the integer value of self is bigger than T::MAX, or smaller than T::MIN, where T is the target type.

5822core::u64unchecked_cast_frommethod

This results in undefined behavior when value will overflow when converted to this type.

5823core::u64unchecked_disjoint_bitormethod

Requires that (self & other) == 0, otherwise it's immediate UB.

Equivalently, requires that (self | other) == (self + other).

5824core::u64unchecked_div_exactmethod

This results in undefined behavior when rhs == 0 or self % rhs != 0, i.e. when checked_div_exact(Self::checked_div_exact) would return None.

5825core::u64unchecked_funnel_shlmethod

This results in undefined behavior if n is greater than or equal to u64::BITS, i.e. when funnel_shl(Self::funnel_shl) would panic.

5826core::u64unchecked_funnel_shrmethod

This results in undefined behavior if n is greater than or equal to u64::BITS, i.e. when funnel_shr(Self::funnel_shr) would panic.

5827core::u64unchecked_mulmethod

This results in undefined behavior when self * rhs > u64::MAX, i.e. when checked_mul would return None.

Unwrap
5828core::u64unchecked_shlmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shl would return None.

5829core::u64unchecked_shl_exactmethod

This results in undefined behavior when rhs > self.leading_zeros() || rhs >= u64::BITS i.e. when u64::shl_exact would return None.

5830core::u64unchecked_shrmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shr would return None.

5831core::u64unchecked_shr_exactmethod

This results in undefined behavior when rhs > self.trailing_zeros() || rhs >= u64::BITS i.e. when u64::shr_exact would return None.

5832core::u64unchecked_submethod

This results in undefined behavior when self - rhs < u64::MIN, i.e. when checked_sub would return None.

Unwrap
5833core::u8as_ascii_uncheckedmethod

This byte must be valid ASCII, or else this is UB.

5834core::u8backward_uncheckedmethod

It is undefined behavior for this operation to overflow the range of values supported by Self. If you cannot guarantee that this will not overflow, use backward or backward_checked instead.

5835core::u8disjoint_bitormethod
5836core::u8forward_uncheckedmethod

It is undefined behavior for this operation to overflow the range of values supported by Self. If you cannot guarantee that this will not overflow, use forward or forward_checked instead.

5837core::u8unchecked_addmethod

This results in undefined behavior when self + rhs > u8::MAX, i.e. when checked_add would return None.

Unwrap
5838core::u8unchecked_castmethod

This results in undefined behavior if the integer value of self is bigger than T::MAX, or smaller than T::MIN, where T is the target type.

5839core::u8unchecked_cast_frommethod

This results in undefined behavior when value will overflow when converted to this type.

5840core::u8unchecked_disjoint_bitormethod

Requires that (self & other) == 0, otherwise it's immediate UB.

Equivalently, requires that (self | other) == (self + other).

5841core::u8unchecked_div_exactmethod

This results in undefined behavior when rhs == 0 or self % rhs != 0, i.e. when checked_div_exact(Self::checked_div_exact) would return None.

5842core::u8unchecked_funnel_shlmethod

This results in undefined behavior if n is greater than or equal to u8::BITS, i.e. when funnel_shl(Self::funnel_shl) would panic.

5843core::u8unchecked_funnel_shrmethod

This results in undefined behavior if n is greater than or equal to u8::BITS, i.e. when funnel_shr(Self::funnel_shr) would panic.

5844core::u8unchecked_mulmethod

This results in undefined behavior when self * rhs > u8::MAX, i.e. when checked_mul would return None.

Unwrap
5845core::u8unchecked_shlmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shl would return None.

5846core::u8unchecked_shl_exactmethod

This results in undefined behavior when rhs > self.leading_zeros() || rhs >= u8::BITS i.e. when u8::shl_exact would return None.

5847core::u8unchecked_shrmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shr would return None.

5848core::u8unchecked_shr_exactmethod

This results in undefined behavior when rhs > self.trailing_zeros() || rhs >= u8::BITS i.e. when u8::shr_exact would return None.

5849core::u8unchecked_submethod

This results in undefined behavior when self - rhs < u8::MIN, i.e. when checked_sub would return None.

Unwrap
5850core::usizebackward_uncheckedmethod

It is undefined behavior for this operation to overflow the range of values supported by Self. If you cannot guarantee that this will not overflow, use backward or backward_checked instead.

5851core::usizedisjoint_bitormethod
5852core::usizeforward_uncheckedmethod

It is undefined behavior for this operation to overflow the range of values supported by Self. If you cannot guarantee that this will not overflow, use forward or forward_checked instead.

5853core::usizeget_uncheckedmethod

Calling this method with an out-of-bounds index or a dangling slice pointer is [undefined behavior] even if the resulting pointer is not used.

5854core::usizeget_unchecked_mutmethod

Calling this method with an out-of-bounds index or a dangling slice pointer is [undefined behavior] even if the resulting pointer is not used.

5855core::usizeunchecked_addmethod

This results in undefined behavior when self + rhs > usize::MAX, i.e. when checked_add would return None.

Unwrap
5856core::usizeunchecked_castmethod

This results in undefined behavior if the integer value of self is bigger than T::MAX, or smaller than T::MIN, where T is the target type.

5857core::usizeunchecked_cast_frommethod

This results in undefined behavior when value will overflow when converted to this type.

5858core::usizeunchecked_disjoint_bitormethod

Requires that (self & other) == 0, otherwise it's immediate UB.

Equivalently, requires that (self | other) == (self + other).

5859core::usizeunchecked_div_exactmethod

This results in undefined behavior when rhs == 0 or self % rhs != 0, i.e. when checked_div_exact(Self::checked_div_exact) would return None.

5860core::usizeunchecked_funnel_shlmethod

This results in undefined behavior if n is greater than or equal to usize::BITS, i.e. when funnel_shl(Self::funnel_shl) would panic.

5861core::usizeunchecked_funnel_shrmethod

This results in undefined behavior if n is greater than or equal to usize::BITS, i.e. when funnel_shr(Self::funnel_shr) would panic.

5862core::usizeunchecked_mulmethod

This results in undefined behavior when self * rhs > usize::MAX, i.e. when checked_mul would return None.

Unwrap
5863core::usizeunchecked_shlmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shl would return None.

5864core::usizeunchecked_shl_exactmethod

This results in undefined behavior when rhs > self.leading_zeros() || rhs >= usize::BITS i.e. when usize::shl_exact would return None.

5865core::usizeunchecked_shrmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shr would return None.

5866core::usizeunchecked_shr_exactmethod

This results in undefined behavior when rhs > self.trailing_zeros() || rhs >= usize::BITS i.e. when usize::shr_exact would return None.

5867core::usizeunchecked_submethod

This results in undefined behavior when self - rhs < usize::MIN, i.e. when checked_sub would return None.

Unwrap
5868std::alloc::Systemallocmethod

layout must have non-zero size. Attempting to allocate for a zero-sized layout will result in undefined behavior.

(Extension subtraits might provide more specific bounds on behavior, e.g., guarantee a sentinel address or a null pointer in response to a zero-size allocation request.)

The allocated block of memory may or may not be initialized.

NonZero
5869std::alloc::Systemalloc_zeroedmethod

The caller has to ensure that layout has non-zero size. Like alloc zero sized layout will result in undefined behavior. However the allocated block of memory is guaranteed to be initialized.

NonZero
5870std::alloc::Systemdeallocmethod

The caller must ensure:

  • ptr is a block of memory currently allocated via this allocator and,
  • layout is the same layout that was used to allocate that block of memory.

Otherwise the behavior is undefined.

Allocated
5871std::alloc::Systemdeallocatemethod
  • ptr must denote a block of memory [currently allocated] via this allocator, and
  • layout must [fit] that block of memory.
Allocated
5872std::alloc::Systemgrowmethod
  • ptr must denote a block of memory [currently allocated] via this allocator.
  • old_layout must [fit] that block of memory (The new_layout argument need not fit it.).
  • new_layout.size() must be greater than or equal to old_layout.size().

Note that new_layout.align() need not be the same as old_layout.align().

Allocated, ValidNum
5873std::alloc::Systemgrow_zeroedmethod
  • ptr must denote a block of memory [currently allocated] via this allocator.
  • old_layout must [fit] that block of memory (The new_layout argument need not fit it.).
  • new_layout.size() must be greater than or equal to old_layout.size().

Note that new_layout.align() need not be the same as old_layout.align().

Allocated, ValidNum
5874std::alloc::Systemreallocmethod

The caller must ensure that:

  • ptr is allocated via this allocator,
  • layout is the same layout that was used to allocate that block of memory,
  • new_size is greater than zero.
  • new_size, when rounded up to the nearest multiple of layout.align(), does not overflow isize (i.e., the rounded value must be less than or equal to isize::MAX).

If these are not followed, the behavior is undefined.

(Extension subtraits might provide more specific bounds on behavior, e.g., guarantee a sentinel address or a null pointer in response to a zero-size allocation request.)

InBound, ValidNum, NonZero
5875std::alloc::Systemshrinkmethod
  • ptr must denote a block of memory [currently allocated] via this allocator.
  • old_layout must [fit] that block of memory (The new_layout argument need not fit it.).
  • new_layout.size() must be smaller than or equal to old_layout.size().

Note that new_layout.align() need not be the same as old_layout.align().

Allocated
5876std::charas_ascii_uncheckedmethod

This char must be within the ASCII range, or else this is UB.

InBound
5877std::charfrom_u32_uncheckedmethod

This function is unsafe, as it may construct invalid char values.

For a safe version of this function, see the from_u32 function.

5878std::collections::hash::map::HashMapget_disjoint_unchecked_mutmethod

Calling this method with overlapping keys is [undefined behavior] even if the resulting references are not used.

5879std::envremove_varfunction

This function is sound to call in a single-threaded program.

This function is also always sound to call on Windows, in single-threaded and multi-threaded programs.

In multi-threaded programs on other operating systems, the only sound option is to not use set_var or remove_var at all.

The exact requirement is: you must ensure that there are no other threads concurrently writing or reading(!) the environment through functions or global variables other than the ones in this module. The problem is that these operating systems do not provide a thread-safe way to read the environment, and most C libraries, including libc itself, do not advertise which functions read from the environment. Even functions from the Rust standard library may read the environment without going through this module, e.g. for DNS lookups from std::net::ToSocketAddrs. No stable guarantee is made about which functions may read from the environment in future versions of a library. All this makes it not practically possible for you to guarantee that no other thread will read the environment, so the only sound option is to not use set_var or remove_var in multi-threaded programs at all.

Discussion of this unsafety on Unix may be found in:

To prevent a child process from inheriting an environment variable, you can instead use Command::env_remove or Command::env_clear.

5880std::envset_varfunction

This function is sound to call in a single-threaded program.

This function is also always sound to call on Windows, in single-threaded and multi-threaded programs.

In multi-threaded programs on other operating systems, the only sound option is to not use set_var or remove_var at all.

The exact requirement is: you must ensure that there are no other threads concurrently writing or reading(!) the environment through functions or global variables other than the ones in this module. The problem is that these operating systems do not provide a thread-safe way to read the environment, and most C libraries, including libc itself, do not advertise which functions read from the environment. Even functions from the Rust standard library may read the environment without going through this module, e.g. for DNS lookups from std::net::ToSocketAddrs. No stable guarantee is made about which functions may read from the environment in future versions of a library. All this makes it not practically possible for you to guarantee that no other thread will read the environment, so the only sound option is to not use set_var or remove_var in multi-threaded programs at all.

Discussion of this unsafety on Unix may be found in:

To pass an environment variable to a child process, you can instead use Command::env.

5881std::f128to_int_uncheckedmethod

The value must:

  • Not be NaN
  • Not be infinite
  • Be representable in the return type Int, after truncating off its fractional part
5882std::f16to_int_uncheckedmethod

The value must:

  • Not be NaN
  • Not be infinite
  • Be representable in the return type Int, after truncating off its fractional part
5883std::f32to_int_uncheckedmethod

The value must:

  • Not be NaN
  • Not be infinite
  • Be representable in the return type Int, after truncating off its fractional part
5884std::f64to_int_uncheckedmethod

The value must:

  • Not be NaN
  • Not be infinite
  • Be representable in the return type Int, after truncating off its fractional part
5885std::ffi::os_str::OsStrclone_to_uninitmethod

Behavior is undefined if any of the following conditions are violated:

  • dest must be [valid] for writes for size_of_val(self) bytes.
  • dest must be properly aligned to align_of_val(self).
Align
5886std::ffi::os_str::OsStrfrom_encoded_bytes_uncheckedmethod

As the encoding is unspecified, callers must pass in bytes that originated as a mixture of validated UTF-8 and bytes from OsStr::as_encoded_bytes from within the same Rust version built for the same target platform. For example, reconstructing an OsStr from bytes sent over the network or stored in a file will likely violate these safety rules.

Due to the encoding being self-synchronizing, the bytes from OsStr::as_encoded_bytes can be split either immediately before or immediately after any valid non-empty UTF-8 substring.

5887std::ffi::os_str::OsStringfrom_encoded_bytes_uncheckedmethod

As the encoding is unspecified, callers must pass in bytes that originated as a mixture of validated UTF-8 and bytes from OsStr::as_encoded_bytes from within the same Rust version built for the same target platform. For example, reconstructing an OsString from bytes sent over the network or stored in a file will likely violate these safety rules.

Due to the encoding being self-synchronizing, the bytes from OsStr::as_encoded_bytes can be split either immediately before or immediately after any valid non-empty UTF-8 substring.

5888std::fs::Dirfrom_raw_fdmethod

The fd passed in must be an [owned file descriptor][io-safety]; in particular, it must be open.

5889std::fs::Filefrom_raw_fdmethod

The fd passed in must be an [owned file descriptor][io-safety]; in particular, it must be open.

5890std::fs::Filefrom_raw_handlemethod

The handle passed in must: - be an [owned handle][io-safety]; in particular, it must be open. - be a handle for a resource that may be freed via CloseHandle (as opposed to RegCloseKey or other close functions).

Note that the handle may have the value INVALID_HANDLE_VALUE (-1), which is sometimes a valid handle value. See [here] for the full story.

5891std::i128unchecked_addmethod

This results in undefined behavior when self + rhs > i128::MAX or self + rhs < i128::MIN, i.e. when checked_add would return None.

Unwrap
5892std::i128unchecked_castmethod

This results in undefined behavior if the integer value of self is bigger than T::MAX, or smaller than T::MIN, where T is the target type.

5893std::i128unchecked_div_exactmethod

This results in undefined behavior when rhs == 0, self % rhs != 0, or self == i128::MIN && rhs == -1, i.e. when checked_div_exact(Self::checked_div_exact) would return None.

5894std::i128unchecked_mulmethod

This results in undefined behavior when self rhs > i128::MAX or self rhs < i128::MIN, i.e. when checked_mul would return None.

Unwrap
5895std::i128unchecked_negmethod

This results in undefined behavior when self == i128::MIN, i.e. when checked_neg would return None.

5896std::i128unchecked_shlmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shl would return None.

5897std::i128unchecked_shl_exactmethod

This results in undefined behavior when rhs >= self.leading_zeros() && rhs >= self.leading_ones() i.e. when i128::shl_exact would return None.

5898std::i128unchecked_shrmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shr would return None.

5899std::i128unchecked_shr_exactmethod

This results in undefined behavior when rhs > self.trailing_zeros() || rhs >= i128::BITS i.e. when i128::shr_exact would return None.

5900std::i128unchecked_submethod

This results in undefined behavior when self - rhs > i128::MAX or self - rhs < i128::MIN, i.e. when checked_sub would return None.

Unwrap
5901std::i16unchecked_addmethod

This results in undefined behavior when self + rhs > i16::MAX or self + rhs < i16::MIN, i.e. when checked_add would return None.

Unwrap
5902std::i16unchecked_castmethod

This results in undefined behavior if the integer value of self is bigger than T::MAX, or smaller than T::MIN, where T is the target type.

5903std::i16unchecked_div_exactmethod

This results in undefined behavior when rhs == 0, self % rhs != 0, or self == i16::MIN && rhs == -1, i.e. when checked_div_exact(Self::checked_div_exact) would return None.

5904std::i16unchecked_mulmethod

This results in undefined behavior when self rhs > i16::MAX or self rhs < i16::MIN, i.e. when checked_mul would return None.

Unwrap
5905std::i16unchecked_negmethod

This results in undefined behavior when self == i16::MIN, i.e. when checked_neg would return None.

5906std::i16unchecked_shlmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shl would return None.

5907std::i16unchecked_shl_exactmethod

This results in undefined behavior when rhs >= self.leading_zeros() && rhs >= self.leading_ones() i.e. when i16::shl_exact would return None.

5908std::i16unchecked_shrmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shr would return None.

5909std::i16unchecked_shr_exactmethod

This results in undefined behavior when rhs > self.trailing_zeros() || rhs >= i16::BITS i.e. when i16::shr_exact would return None.

5910std::i16unchecked_submethod

This results in undefined behavior when self - rhs > i16::MAX or self - rhs < i16::MIN, i.e. when checked_sub would return None.

Unwrap
5911std::i32unchecked_addmethod

This results in undefined behavior when self + rhs > i32::MAX or self + rhs < i32::MIN, i.e. when checked_add would return None.

Unwrap
5912std::i32unchecked_castmethod

This results in undefined behavior if the integer value of self is bigger than T::MAX, or smaller than T::MIN, where T is the target type.

5913std::i32unchecked_div_exactmethod

This results in undefined behavior when rhs == 0, self % rhs != 0, or self == i32::MIN && rhs == -1, i.e. when checked_div_exact(Self::checked_div_exact) would return None.

5914std::i32unchecked_mulmethod

This results in undefined behavior when self rhs > i32::MAX or self rhs < i32::MIN, i.e. when checked_mul would return None.

Unwrap
5915std::i32unchecked_negmethod

This results in undefined behavior when self == i32::MIN, i.e. when checked_neg would return None.

5916std::i32unchecked_shlmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shl would return None.

5917std::i32unchecked_shl_exactmethod

This results in undefined behavior when rhs >= self.leading_zeros() && rhs >= self.leading_ones() i.e. when i32::shl_exact would return None.

5918std::i32unchecked_shrmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shr would return None.

5919std::i32unchecked_shr_exactmethod

This results in undefined behavior when rhs > self.trailing_zeros() || rhs >= i32::BITS i.e. when i32::shr_exact would return None.

5920std::i32unchecked_submethod

This results in undefined behavior when self - rhs > i32::MAX or self - rhs < i32::MIN, i.e. when checked_sub would return None.

Unwrap
5921std::i64unchecked_addmethod

This results in undefined behavior when self + rhs > i64::MAX or self + rhs < i64::MIN, i.e. when checked_add would return None.

Unwrap
5922std::i64unchecked_castmethod

This results in undefined behavior if the integer value of self is bigger than T::MAX, or smaller than T::MIN, where T is the target type.

5923std::i64unchecked_div_exactmethod

This results in undefined behavior when rhs == 0, self % rhs != 0, or self == i64::MIN && rhs == -1, i.e. when checked_div_exact(Self::checked_div_exact) would return None.

5924std::i64unchecked_mulmethod

This results in undefined behavior when self rhs > i64::MAX or self rhs < i64::MIN, i.e. when checked_mul would return None.

Unwrap
5925std::i64unchecked_negmethod

This results in undefined behavior when self == i64::MIN, i.e. when checked_neg would return None.

5926std::i64unchecked_shlmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shl would return None.

5927std::i64unchecked_shl_exactmethod

This results in undefined behavior when rhs >= self.leading_zeros() && rhs >= self.leading_ones() i.e. when i64::shl_exact would return None.

5928std::i64unchecked_shrmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shr would return None.

5929std::i64unchecked_shr_exactmethod

This results in undefined behavior when rhs > self.trailing_zeros() || rhs >= i64::BITS i.e. when i64::shr_exact would return None.

5930std::i64unchecked_submethod

This results in undefined behavior when self - rhs > i64::MAX or self - rhs < i64::MIN, i.e. when checked_sub would return None.

Unwrap
5931std::i8unchecked_addmethod

This results in undefined behavior when self + rhs > i8::MAX or self + rhs < i8::MIN, i.e. when checked_add would return None.

Unwrap
5932std::i8unchecked_castmethod

This results in undefined behavior if the integer value of self is bigger than T::MAX, or smaller than T::MIN, where T is the target type.

5933std::i8unchecked_div_exactmethod

This results in undefined behavior when rhs == 0, self % rhs != 0, or self == i8::MIN && rhs == -1, i.e. when checked_div_exact(Self::checked_div_exact) would return None.

5934std::i8unchecked_mulmethod

This results in undefined behavior when self rhs > i8::MAX or self rhs < i8::MIN, i.e. when checked_mul would return None.

Unwrap
5935std::i8unchecked_negmethod

This results in undefined behavior when self == i8::MIN, i.e. when checked_neg would return None.

5936std::i8unchecked_shlmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shl would return None.

5937std::i8unchecked_shl_exactmethod

This results in undefined behavior when rhs >= self.leading_zeros() && rhs >= self.leading_ones() i.e. when i8::shl_exact would return None.

5938std::i8unchecked_shrmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shr would return None.

5939std::i8unchecked_shr_exactmethod

This results in undefined behavior when rhs > self.trailing_zeros() || rhs >= i8::BITS i.e. when i8::shr_exact would return None.

5940std::i8unchecked_submethod

This results in undefined behavior when self - rhs > i8::MAX or self - rhs < i8::MIN, i.e. when checked_sub would return None.

Unwrap
5941std::io::pipe::PipeReaderfrom_raw_fdmethod

The fd passed in must be an [owned file descriptor][io-safety]; in particular, it must be open.

5942std::io::pipe::PipeReaderfrom_raw_handlemethod

The handle passed in must: - be an [owned handle][io-safety]; in particular, it must be open. - be a handle for a resource that may be freed via CloseHandle (as opposed to RegCloseKey or other close functions).

Note that the handle may have the value INVALID_HANDLE_VALUE (-1), which is sometimes a valid handle value. See [here] for the full story.

5943std::io::pipe::PipeWriterfrom_raw_fdmethod

The fd passed in must be an [owned file descriptor][io-safety]; in particular, it must be open.

5944std::io::pipe::PipeWriterfrom_raw_handlemethod

The handle passed in must: - be an [owned handle][io-safety]; in particular, it must be open. - be a handle for a resource that may be freed via CloseHandle (as opposed to RegCloseKey or other close functions).

Note that the handle may have the value INVALID_HANDLE_VALUE (-1), which is sometimes a valid handle value. See [here] for the full story.

5945std::isizeunchecked_addmethod

This results in undefined behavior when self + rhs > isize::MAX or self + rhs < isize::MIN, i.e. when checked_add would return None.

Unwrap
5946std::isizeunchecked_castmethod

This results in undefined behavior if the integer value of self is bigger than T::MAX, or smaller than T::MIN, where T is the target type.

5947std::isizeunchecked_div_exactmethod

This results in undefined behavior when rhs == 0, self % rhs != 0, or self == isize::MIN && rhs == -1, i.e. when checked_div_exact(Self::checked_div_exact) would return None.

5948std::isizeunchecked_mulmethod

This results in undefined behavior when self rhs > isize::MAX or self rhs < isize::MIN, i.e. when checked_mul would return None.

Unwrap
5949std::isizeunchecked_negmethod

This results in undefined behavior when self == isize::MIN, i.e. when checked_neg would return None.

5950std::isizeunchecked_shlmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shl would return None.

5951std::isizeunchecked_shl_exactmethod

This results in undefined behavior when rhs >= self.leading_zeros() && rhs >= self.leading_ones() i.e. when isize::shl_exact would return None.

5952std::isizeunchecked_shrmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shr would return None.

5953std::isizeunchecked_shr_exactmethod

This results in undefined behavior when rhs > self.trailing_zeros() || rhs >= isize::BITS i.e. when isize::shr_exact would return None.

5954std::isizeunchecked_submethod

This results in undefined behavior when self - rhs > isize::MAX or self - rhs < isize::MIN, i.e. when checked_sub would return None.

Unwrap
5955std::net::tcp::TcpListenerfrom_raw_fdmethod

The fd passed in must be an [owned file descriptor][io-safety]; in particular, it must be open.

5956std::net::tcp::TcpListenerfrom_raw_socketmethod

The socket passed in must: - be an [owned socket][io-safety]; in particular, it must be open. - be a socket that may be freed via closesocket.

5957std::net::tcp::TcpStreamfrom_raw_fdmethod

The fd passed in must be an [owned file descriptor][io-safety]; in particular, it must be open.

5958std::net::tcp::TcpStreamfrom_raw_socketmethod

The socket passed in must: - be an [owned socket][io-safety]; in particular, it must be open. - be a socket that may be freed via closesocket.

5959std::net::udp::UdpSocketfrom_raw_fdmethod

The fd passed in must be an [owned file descriptor][io-safety]; in particular, it must be open.

5960std::net::udp::UdpSocketfrom_raw_socketmethod

The socket passed in must: - be an [owned socket][io-safety]; in particular, it must be open. - be a socket that may be freed via closesocket.

5961std::os::fd::owned::BorrowedFdborrow_rawmethod

The resource pointed to by fd must remain open for the duration of the returned BorrowedFd.

5962std::os::fd::owned::OwnedFdfrom_raw_fdmethod

The resource pointed to by fd must be open and suitable for assuming [ownership][io-safety]. The resource must not require any cleanup other than close.

5963std::os::fd::raw::FromRawFdfrom_raw_fdtrait_method

The fd passed in must be an [owned file descriptor][io-safety]; in particular, it must be open.

5964std::os::fd::raw::RawFdfrom_raw_fdmethod

The fd passed in must be an [owned file descriptor][io-safety]; in particular, it must be open.

5965std::os::linux::process::PidFdfrom_raw_fdmethod

The fd passed in must be an [owned file descriptor][io-safety]; in particular, it must be open.

5966std::os::unix::net::datagram::UnixDatagramfrom_raw_fdmethod

The fd passed in must be an [owned file descriptor][io-safety]; in particular, it must be open.

5967std::os::unix::net::listener::UnixListenerfrom_raw_fdmethod

The fd passed in must be an [owned file descriptor][io-safety]; in particular, it must be open.

5968std::os::unix::net::stream::UnixStreamfrom_raw_fdmethod

The fd passed in must be an [owned file descriptor][io-safety]; in particular, it must be open.

5969std::os::unix::process::CommandExtbefore_exectrait_method
5970std::os::unix::process::CommandExtpre_exectrait_method
5971std::os::windows::ffi::EncodeWideclone_to_uninitmethod

Behavior is undefined if any of the following conditions are violated:

  • dest must be [valid] for writes for size_of_val(self) bytes.
  • dest must be properly aligned to align_of_val(self).
Align
5972std::os::windows::io::handle::BorrowedHandleborrow_rawmethod

The resource pointed to by handle must be a valid open handle, it must remain open for the duration of the returned BorrowedHandle.

Note that it may have the value INVALID_HANDLE_VALUE (-1), which is sometimes a valid handle value. See [here] for the full story.

And, it may have the value NULL (0), which can occur when consoles are detached from processes, or when windows_subsystem is used.

5973std::os::windows::io::handle::HandleOrInvalidfrom_raw_handlemethod

The passed handle value must either satisfy the safety requirements of FromRawHandle::from_raw_handle, or be INVALID_HANDLE_VALUE (-1). Note that not all Windows APIs use INVALID_HANDLE_VALUE for errors; see [here] for the full story.

5974std::os::windows::io::handle::HandleOrNullfrom_raw_handlemethod

The passed handle value must either satisfy the safety requirements of FromRawHandle::from_raw_handle, or be null. Note that not all Windows APIs use null for errors; see [here] for the full story.

5975std::os::windows::io::handle::OwnedHandlefrom_raw_handlemethod

The handle passed in must: - be an [owned handle][io-safety]; in particular, it must be open. - be a handle for a resource that may be freed via CloseHandle (as opposed to RegCloseKey or other close functions).

Note that the handle may have the value INVALID_HANDLE_VALUE (-1), which is sometimes a valid handle value. See [here] for the full story.

5976std::os::windows::io::raw::FromRawHandlefrom_raw_handletrait_method

The handle passed in must: - be an [owned handle][io-safety]; in particular, it must be open. - be a handle for a resource that may be freed via CloseHandle (as opposed to RegCloseKey or other close functions).

Note that the handle may have the value INVALID_HANDLE_VALUE (-1), which is sometimes a valid handle value. See [here] for the full story.

5977std::os::windows::io::raw::FromRawSocketfrom_raw_sockettrait_method

The socket passed in must: - be an [owned socket][io-safety]; in particular, it must be open. - be a socket that may be freed via closesocket.

5978std::os::windows::io::socket::BorrowedSocketborrow_rawmethod

The resource pointed to by socket must remain open for the duration of the returned BorrowedSocket, and it must not have the value INVALID_SOCKET.

5979std::os::windows::io::socket::OwnedSocketfrom_raw_socketmethod

The socket passed in must: - be an [owned socket][io-safety]; in particular, it must be open. - be a socket that may be freed via closesocket.

5980std::os::windows::net::listener::UnixListenerfrom_raw_socketmethod

The socket passed in must: - be an [owned socket][io-safety]; in particular, it must be open. - be a socket that may be freed via closesocket.

5981std::os::windows::net::stream::UnixStreamfrom_raw_socketmethod

The socket passed in must: - be an [owned socket][io-safety]; in particular, it must be open. - be a socket that may be freed via closesocket.

5982std::os::windows::process::ProcThreadAttributeListBuilderraw_attributemethod

This function is marked as unsafe because it deals with raw pointers and sizes. It is the responsibility of the caller to ensure the value lives longer than the resulting ProcThreadAttributeList as well as the validity of the size parameter.

5983std::path::Pathclone_to_uninitmethod

Behavior is undefined if any of the following conditions are violated:

  • dest must be [valid] for writes for size_of_val(self) bytes.
  • dest must be properly aligned to align_of_val(self).
Align
5984std::process::Commandpre_execmethod
5985std::process::Stdiofrom_raw_fdmethod

The fd passed in must be an [owned file descriptor][io-safety]; in particular, it must be open.

5986std::process::Stdiofrom_raw_handlemethod

The handle passed in must: - be an [owned handle][io-safety]; in particular, it must be open. - be a handle for a resource that may be freed via CloseHandle (as opposed to RegCloseKey or other close functions).

Note that the handle may have the value INVALID_HANDLE_VALUE (-1), which is sometimes a valid handle value. See [here] for the full story.

5987std::stras_ascii_uncheckedmethod

Every character in this string must be ASCII, or else this is UB.

5988std::stras_bytes_mutmethod

The caller must ensure that the content of the slice is valid UTF-8 before the borrow ends and the underlying str is used.

Use of a str whose contents are not valid UTF-8 is undefined behavior.

ValidString
5989std::strfrom_utf8_uncheckedmethod

The bytes passed in must be valid UTF-8.

ValidString
5990std::strfrom_utf8_unchecked_mutmethod
5991std::strget_uncheckedmethod

Callers of this function are responsible that these preconditions are satisfied:

  • The starting index must not exceed the ending index;
  • Indexes must be within bounds of the original slice;
  • Indexes must lie on UTF-8 sequence boundaries.

Failing that, the returned string slice may reference invalid memory or violate the invariants communicated by the str type.

InBound
5992std::strget_unchecked_mutmethod

Callers of this function are responsible that these preconditions are satisfied:

  • The starting index must not exceed the ending index;
  • Indexes must be within bounds of the original slice;
  • Indexes must lie on UTF-8 sequence boundaries.

Failing that, the returned string slice may reference invalid memory or violate the invariants communicated by the str type.

InBound
5993std::strslice_mut_uncheckedmethod

Callers of this function are responsible that three preconditions are satisfied:

  • begin must not exceed end.
  • begin and end must be byte positions within the string slice.
  • begin and end must lie on UTF-8 sequence boundaries.
InBound
5994std::strslice_uncheckedmethod

Callers of this function are responsible that three preconditions are satisfied:

  • begin must not exceed end.
  • begin and end must be byte positions within the string slice.
  • begin and end must lie on UTF-8 sequence boundaries.
InBound
5995std::thread::builder::Builderspawn_uncheckedmethod

The caller has to ensure that the spawned thread does not outlive any references in the supplied thread closure and its return type. This can be guaranteed in two ways:

  • ensure that joinJoinHandle::join is called before any referenced data is dropped
  • use only types with 'static lifetime bounds, i.e., those with no or only 'static references (both thread::Builder::spawnBuilder::spawn and thread::spawn enforce this property statically)
5996std::thread::thread::Threadfrom_rawmethod

This function is unsafe because improper use may lead to memory unsafety, even if the returned Thread is never accessed.

Creating a Thread from a pointer other than one returned from Thread::into_raw is undefined behavior.

Calling this function twice on the same raw pointer can lead to a double-free if both Thread instances are dropped.

MayInvalid, Forgotten
5997std::u128unchecked_addmethod

This results in undefined behavior when self + rhs > u128::MAX, i.e. when checked_add would return None.

Unwrap
5998std::u128unchecked_castmethod

This results in undefined behavior if the integer value of self is bigger than T::MAX, or smaller than T::MIN, where T is the target type.

5999std::u128unchecked_disjoint_bitormethod

Requires that (self & other) == 0, otherwise it's immediate UB.

Equivalently, requires that (self | other) == (self + other).

6000std::u128unchecked_div_exactmethod

This results in undefined behavior when rhs == 0 or self % rhs != 0, i.e. when checked_div_exact(Self::checked_div_exact) would return None.

6001std::u128unchecked_funnel_shlmethod

This results in undefined behavior if n is greater than or equal to u128::BITS, i.e. when funnel_shl(Self::funnel_shl) would panic.

6002std::u128unchecked_funnel_shrmethod

This results in undefined behavior if n is greater than or equal to u128::BITS, i.e. when funnel_shr(Self::funnel_shr) would panic.

6003std::u128unchecked_mulmethod

This results in undefined behavior when self * rhs > u128::MAX, i.e. when checked_mul would return None.

Unwrap
6004std::u128unchecked_shlmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shl would return None.

6005std::u128unchecked_shl_exactmethod

This results in undefined behavior when rhs > self.leading_zeros() || rhs >= u128::BITS i.e. when u128::shl_exact would return None.

6006std::u128unchecked_shrmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shr would return None.

6007std::u128unchecked_shr_exactmethod

This results in undefined behavior when rhs > self.trailing_zeros() || rhs >= u128::BITS i.e. when u128::shr_exact would return None.

6008std::u128unchecked_submethod

This results in undefined behavior when self - rhs < u128::MIN, i.e. when checked_sub would return None.

Unwrap
6009std::u16unchecked_addmethod

This results in undefined behavior when self + rhs > u16::MAX, i.e. when checked_add would return None.

Unwrap
6010std::u16unchecked_castmethod

This results in undefined behavior if the integer value of self is bigger than T::MAX, or smaller than T::MIN, where T is the target type.

6011std::u16unchecked_disjoint_bitormethod

Requires that (self & other) == 0, otherwise it's immediate UB.

Equivalently, requires that (self | other) == (self + other).

6012std::u16unchecked_div_exactmethod

This results in undefined behavior when rhs == 0 or self % rhs != 0, i.e. when checked_div_exact(Self::checked_div_exact) would return None.

6013std::u16unchecked_funnel_shlmethod

This results in undefined behavior if n is greater than or equal to u16::BITS, i.e. when funnel_shl(Self::funnel_shl) would panic.

6014std::u16unchecked_funnel_shrmethod

This results in undefined behavior if n is greater than or equal to u16::BITS, i.e. when funnel_shr(Self::funnel_shr) would panic.

6015std::u16unchecked_mulmethod

This results in undefined behavior when self * rhs > u16::MAX, i.e. when checked_mul would return None.

Unwrap
6016std::u16unchecked_shlmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shl would return None.

6017std::u16unchecked_shl_exactmethod

This results in undefined behavior when rhs > self.leading_zeros() || rhs >= u16::BITS i.e. when u16::shl_exact would return None.

6018std::u16unchecked_shrmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shr would return None.

6019std::u16unchecked_shr_exactmethod

This results in undefined behavior when rhs > self.trailing_zeros() || rhs >= u16::BITS i.e. when u16::shr_exact would return None.

6020std::u16unchecked_submethod

This results in undefined behavior when self - rhs < u16::MIN, i.e. when checked_sub would return None.

Unwrap
6021std::u32unchecked_addmethod

This results in undefined behavior when self + rhs > u32::MAX, i.e. when checked_add would return None.

Unwrap
6022std::u32unchecked_castmethod

This results in undefined behavior if the integer value of self is bigger than T::MAX, or smaller than T::MIN, where T is the target type.

6023std::u32unchecked_disjoint_bitormethod

Requires that (self & other) == 0, otherwise it's immediate UB.

Equivalently, requires that (self | other) == (self + other).

6024std::u32unchecked_div_exactmethod

This results in undefined behavior when rhs == 0 or self % rhs != 0, i.e. when checked_div_exact(Self::checked_div_exact) would return None.

6025std::u32unchecked_funnel_shlmethod

This results in undefined behavior if n is greater than or equal to u32::BITS, i.e. when funnel_shl(Self::funnel_shl) would panic.

6026std::u32unchecked_funnel_shrmethod

This results in undefined behavior if n is greater than or equal to u32::BITS, i.e. when funnel_shr(Self::funnel_shr) would panic.

6027std::u32unchecked_mulmethod

This results in undefined behavior when self * rhs > u32::MAX, i.e. when checked_mul would return None.

Unwrap
6028std::u32unchecked_shlmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shl would return None.

6029std::u32unchecked_shl_exactmethod

This results in undefined behavior when rhs > self.leading_zeros() || rhs >= u32::BITS i.e. when u32::shl_exact would return None.

6030std::u32unchecked_shrmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shr would return None.

6031std::u32unchecked_shr_exactmethod

This results in undefined behavior when rhs > self.trailing_zeros() || rhs >= u32::BITS i.e. when u32::shr_exact would return None.

6032std::u32unchecked_submethod

This results in undefined behavior when self - rhs < u32::MIN, i.e. when checked_sub would return None.

Unwrap
6033std::u64unchecked_addmethod

This results in undefined behavior when self + rhs > u64::MAX, i.e. when checked_add would return None.

Unwrap
6034std::u64unchecked_castmethod

This results in undefined behavior if the integer value of self is bigger than T::MAX, or smaller than T::MIN, where T is the target type.

6035std::u64unchecked_disjoint_bitormethod

Requires that (self & other) == 0, otherwise it's immediate UB.

Equivalently, requires that (self | other) == (self + other).

6036std::u64unchecked_div_exactmethod

This results in undefined behavior when rhs == 0 or self % rhs != 0, i.e. when checked_div_exact(Self::checked_div_exact) would return None.

6037std::u64unchecked_funnel_shlmethod

This results in undefined behavior if n is greater than or equal to u64::BITS, i.e. when funnel_shl(Self::funnel_shl) would panic.

6038std::u64unchecked_funnel_shrmethod

This results in undefined behavior if n is greater than or equal to u64::BITS, i.e. when funnel_shr(Self::funnel_shr) would panic.

6039std::u64unchecked_mulmethod

This results in undefined behavior when self * rhs > u64::MAX, i.e. when checked_mul would return None.

Unwrap
6040std::u64unchecked_shlmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shl would return None.

6041std::u64unchecked_shl_exactmethod

This results in undefined behavior when rhs > self.leading_zeros() || rhs >= u64::BITS i.e. when u64::shl_exact would return None.

6042std::u64unchecked_shrmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shr would return None.

6043std::u64unchecked_shr_exactmethod

This results in undefined behavior when rhs > self.trailing_zeros() || rhs >= u64::BITS i.e. when u64::shr_exact would return None.

6044std::u64unchecked_submethod

This results in undefined behavior when self - rhs < u64::MIN, i.e. when checked_sub would return None.

Unwrap
6045std::u8as_ascii_uncheckedmethod

This byte must be valid ASCII, or else this is UB.

6046std::u8unchecked_addmethod

This results in undefined behavior when self + rhs > u8::MAX, i.e. when checked_add would return None.

Unwrap
6047std::u8unchecked_castmethod

This results in undefined behavior if the integer value of self is bigger than T::MAX, or smaller than T::MIN, where T is the target type.

6048std::u8unchecked_disjoint_bitormethod

Requires that (self & other) == 0, otherwise it's immediate UB.

Equivalently, requires that (self | other) == (self + other).

6049std::u8unchecked_div_exactmethod

This results in undefined behavior when rhs == 0 or self % rhs != 0, i.e. when checked_div_exact(Self::checked_div_exact) would return None.

6050std::u8unchecked_funnel_shlmethod

This results in undefined behavior if n is greater than or equal to u8::BITS, i.e. when funnel_shl(Self::funnel_shl) would panic.

6051std::u8unchecked_funnel_shrmethod

This results in undefined behavior if n is greater than or equal to u8::BITS, i.e. when funnel_shr(Self::funnel_shr) would panic.

6052std::u8unchecked_mulmethod

This results in undefined behavior when self * rhs > u8::MAX, i.e. when checked_mul would return None.

Unwrap
6053std::u8unchecked_shlmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shl would return None.

6054std::u8unchecked_shl_exactmethod

This results in undefined behavior when rhs > self.leading_zeros() || rhs >= u8::BITS i.e. when u8::shl_exact would return None.

6055std::u8unchecked_shrmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shr would return None.

6056std::u8unchecked_shr_exactmethod

This results in undefined behavior when rhs > self.trailing_zeros() || rhs >= u8::BITS i.e. when u8::shr_exact would return None.

6057std::u8unchecked_submethod

This results in undefined behavior when self - rhs < u8::MIN, i.e. when checked_sub would return None.

Unwrap
6058std::usizeunchecked_addmethod

This results in undefined behavior when self + rhs > usize::MAX, i.e. when checked_add would return None.

Unwrap
6059std::usizeunchecked_castmethod

This results in undefined behavior if the integer value of self is bigger than T::MAX, or smaller than T::MIN, where T is the target type.

6060std::usizeunchecked_disjoint_bitormethod

Requires that (self & other) == 0, otherwise it's immediate UB.

Equivalently, requires that (self | other) == (self + other).

6061std::usizeunchecked_div_exactmethod

This results in undefined behavior when rhs == 0 or self % rhs != 0, i.e. when checked_div_exact(Self::checked_div_exact) would return None.

6062std::usizeunchecked_funnel_shlmethod

This results in undefined behavior if n is greater than or equal to usize::BITS, i.e. when funnel_shl(Self::funnel_shl) would panic.

6063std::usizeunchecked_funnel_shrmethod

This results in undefined behavior if n is greater than or equal to usize::BITS, i.e. when funnel_shr(Self::funnel_shr) would panic.

6064std::usizeunchecked_mulmethod

This results in undefined behavior when self * rhs > usize::MAX, i.e. when checked_mul would return None.

Unwrap
6065std::usizeunchecked_shlmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shl would return None.

6066std::usizeunchecked_shl_exactmethod

This results in undefined behavior when rhs > self.leading_zeros() || rhs >= usize::BITS i.e. when usize::shl_exact would return None.

6067std::usizeunchecked_shrmethod

This results in undefined behavior if rhs is larger than or equal to the number of bits in self, i.e. when checked_shr would return None.

6068std::usizeunchecked_shr_exactmethod

This results in undefined behavior when rhs > self.trailing_zeros() || rhs >= usize::BITS i.e. when usize::shr_exact would return None.

6069std::usizeunchecked_submethod

This results in undefined behavior when self - rhs < usize::MIN, i.e. when checked_sub would return None.

Unwrap